CN114237548A - Method and system for complex dot product operation based on nonvolatile memory array - Google Patents

Method and system for complex dot product operation based on nonvolatile memory array Download PDF

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CN114237548A
CN114237548A CN202111382949.9A CN202111382949A CN114237548A CN 114237548 A CN114237548 A CN 114237548A CN 202111382949 A CN202111382949 A CN 202111382949A CN 114237548 A CN114237548 A CN 114237548A
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缪峰
梁世军
王聪
阮恭杰
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Abstract

The invention discloses a method for complex number dot multiplication operation based on a nonvolatile memory array, which comprises the following steps: (1) converting an n-dimensional complex input vector X into a 2 n-dimensional real vector X; (2) converting the m x n dimensional complex input matrix H into a 2m x 2n dimensional real matrix H; (3) designing a memory computing hardware array according to the matrix H; (4) realizing matrix vector dot product operation on the array; (5) the 2 m-dimensional real output vector Y is converted into an m-dimensional complex vector Y. The invention also discloses a system for complex dot product operation based on the nonvolatile memory array. The invention completes the parallel matrix vector point multiplication operation of any dimension in the complex number field based on the in-memory computing hardware array, successfully populates the matrix vector point multiplication operation from the real number field to the complex number field, enlarges the application range of the method, and has universality.

Description

Method and system for complex dot product operation based on nonvolatile memory array
Technical Field
The present invention relates to memory computing, and more particularly, to a method and system for complex dot product operation based on a non-volatile memory array.
Background
With the dramatic increase of the social demand on computing power, the existing computing architecture meets the challenges of a power consumption wall, a performance wall, a memory wall, a slow moore law and the like, the innovation of the computing architecture is urgently needed, and the solution path is mainly embodied in two points: the method breaks through a computing architecture and breaks a storage wall, and the in-memory computing is a technology for breaking the storage wall.
The traditional von neumann architecture is the classic architecture of computers and the mainstream architecture of computers and processor chips at present. In the von neumann architecture, a computing (processing) unit is completely separated from a memory, and in the computing process, the computing unit reads data from the memory according to an instruction, completes computation in the computing unit, and stores the result back to the memory. The main difference between memory computing and a traditional von neumann architecture is that computing is embedded into a memory, and the memory plays a role in computing and storing at the same time, and completes computing while storing/reading data. The characteristics of high integration level and low power consumption of memory computing make the memory computing promising as an important basic technology of embedded artificial intelligence (such as intelligent IoT) in the future.
The existing memory computing technology is used for carrying out matrix vector point multiplication operation, and both vectors and matrixes belong to the field of real number fields, so the existing memory computing technology does not have the capability of carrying out parallel matrix vector point multiplication operation on a complex number field, and the application range and the application scene of the memory computing technology are greatly limited due to the lack of completeness.
Disclosure of Invention
The purpose of the invention is as follows: the invention aims to provide a method and a system for complex number point multiplication operation based on a nonvolatile memory array, which solve the problem that parallel matrix vector point multiplication operation cannot be realized on a complex number field.
The technical scheme is as follows: the invention discloses a complex number dot multiplication operation method based on a nonvolatile memory array, which comprises the following steps:
(1) converting an n-dimensional complex input vector X into a 2 n-dimensional real vector X;
(2) converting the m x n dimensional complex input matrix H into a 2m x 2n dimensional real matrix H;
(3) designing a memory computing hardware array according to the matrix H;
(4) realizing matrix vector dot product operation on the array;
(5) the 2 m-dimensional real output vector Y is converted into an m-dimensional complex output vector Y.
The step (1) comprises the following steps:
(11) let the a-th complex vector element x of the input vector xa＝xar+jxai，
Wherein x isarIs xaReal part of (x)aiIs xaJ is an imaginary unit, and a is traversed from 1 to n;
(12) x is to bear2a-1 vector element X as real number vector X2a-1X is to beai2 a-th vector element X as a real number vector X2a。
The step (2) comprises the following steps:
(21) let each complex matrix element h of the m x n complex input matrix hbc＝hbcr+jhbci，
Wherein h isbcElements of the matrix h, representing the b, c, columns of the matrix hbcrIs hbcReal part of, hbciIs hbcJ is an imaginary unit; b is traversed from 1 to m, c is traversed from 1 to n;
(22) h is to bebcrElement H as column 2c-1 of row 2b-1 of matrix H2b-1，2c-1And element H of row 2b, column 2c2b，2cH is to bebciElement H as the 2b, 2c-1 column of matrix H2b，2c-1Will-hbciElement H as column 2c of row 2b-1 of matrix H2b-1，2c。
The step (3) comprises the following steps:
(31) the matrix H is transposed to obtain a matrix G which determines the array structure, i.e. G is HT；
(32) The 2 n-by-2 m memory cells form an array with 2n rows and 2m columns, wherein the conductance of the memory cell in the d row and e column is determined by the matrix element G of the matrix GdeDetermination of where GdeThe matrix element represents the d row and the e column of the matrix G; d is traversed from 1 to 2n and e is traversed from 1 to 2 m.
The step (4) comprises the following steps:
(41) make the array row g input equal to the 2 n-dimensional real input vector Xg vector elements XgMagnitude of voltage; traversing g from 1 to 2 n;
(42) obtaining the current magnitude of the kth column as the kth vector element Y of the real output vector Y with 2m dimensionskK is traversed from 1 to 2 m.
In the step (5), the 2f-1 vector element of the 2 m-dimensional real number output vector Y is marked as YfrAnd the 2 f-th vector element is YfiUsing the 2f-1 th real number vector element Y of YfrAnd 2f real number vector element YfiCombined into a complex number yf＝Yfr+jYfi，
Wherein, YfrIs yfReal part of, YfiIs yfJ is an imaginary unit; then y isfThe f-th vector element, which is the complex output vector y, traverses f from 1 to m.
The invention relates to a system for complex number point multiplication operation based on a nonvolatile memory array, which comprises an input vector conversion unit, an input matrix conversion unit, a memory calculation array unit, a point multiplication operation unit and an output vector conversion unit;
the input vector conversion unit converts an n-dimensional complex input vector X into a 2 n-dimensional real vector X; the input matrix conversion unit converts the m-by-n complex input matrix H into a 2 m-by-2 n real matrix H; the memory computing array unit is designed according to a matrix H; the dot multiplication operation unit realizes X and H matrix vector dot multiplication operation on the array to obtain a 2 m-dimensional real output vector Y; the output vector conversion unit converts a 2 m-dimensional real output vector Y into an m-dimensional complex output vector Y.
The in-memory computing array unit is a nonvolatile memory array, and the array structure matrix G is equal to the transpose of a matrix H, namely G-HT。
The input vector conversion unit comprises a programmable multi-channel signal source, the signal source is programmed, when a computer inputs an n-dimensional complex vector x, the signal source outputs 2n paths of direct current voltage in parallel, and the magnitude of the 2k-1 path of voltage is equal to xkrThe 2k path voltage is equal to xkiTraversing k from 1 to n; the direct current voltage of the k path is used as the input of the k row of the memory computing hardware arrayA voltage.
The output vector conversion unit comprises a programmable multi-channel oscilloscope, the oscilloscope is programmed, and after the oscilloscope receives 2m paths of direct current, an m-dimensional complex vector y is output on the computer.
Has the advantages that: compared with the prior art, the invention has the following remarkable advantages: the parallel matrix vector point multiplication operation of any dimension in a complex number field is completed based on the in-memory computing hardware array, the matrix vector point multiplication operation is successfully popularized from a real number field to the complex number field, the application range of the method is expanded, and the method has universality.
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FIG. 1 is a schematic diagram of the process of the present invention;
FIG. 2 is a schematic diagram of the system of the present invention;
FIG. 3 is a schematic diagram of an embodiment of the present invention.
Detailed Description
The technical scheme of the invention is further explained by combining the attached drawings.
As shown in fig. 1, the method for complex dot product operation based on the non-volatile memory array according to the present invention is characterized in that: the method comprises the following steps:
converting an n-dimensional complex input vector X into a 2 n-dimensional real vector X; the method specifically comprises the following steps:
(11) let the a-th complex vector element x of the input vector xa＝xar+jxai，
Wherein x isarIs xaReal part of (x)aiIs xaJ is an imaginary unit, and a is traversed from 1 to n;
(12) x is to bear2a-1 vector element X as real number vector X2a-1X is to beai2 a-th vector element X as a real number vector X2a。
Converting the m x n dimensional complex input matrix H into a 2m x 2n dimensional real matrix H; the method specifically comprises the following steps:
(21) let each complex matrix element h of the m x n complex input matrix hbc＝hbcr+jhbci，
Wherein h isbcElements of the matrix h, representing the b, c, columns of the matrix hbcrIs hbcReal part of, hbciIs hbcJ is an imaginary unit; b is traversed from 1 to m, c is traversed from 1 to n;
(22) h is to bebcrElement H as column 2c-1 of row 2b-1 of matrix H2b-1，2c-1And element H of row 2b, column 2c2b，2cH is to bebciElement H as the 2b, 2c-1 column of matrix H2b，2c-1Will-hbciElement H as column 2c of row 2b-1 of matrix H2b-1，2c。
Designing an in-memory computing hardware array according to the matrix H; the method specifically comprises the following steps:
(31) the matrix H is transposed to obtain a matrix G which determines the array structure, i.e. G is HT；
(32) The 2 n-by-2 m memory cells form an array with 2n rows and 2m columns, wherein the conductance of the memory cell in the d row and e column is determined by the matrix element G of the matrix GdeDetermination of where GdeThe matrix element represents the d row and the e column of the matrix G; d is traversed from 1 to 2n and e is traversed from 1 to 2 m.
Step (4) realizing matrix vector dot product operation on the array; the method specifically comprises the following steps:
(41) let the array's row g input equal the g vector element X of the 2 n-dimensional real input vector XgMagnitude of voltage; traversing g from 1 to 2 n;
(42) obtaining the current magnitude of the kth column as the kth vector element Y of the real output vector Y with 2m dimensionskK is traversed from 1 to 2 m.
And (5) converting the 2 m-dimensional real output vector Y into an m-dimensional complex output vector Y.
Let the 2f-1 vector element of the 2 m-dimensional real output vector Y be YfrAnd the 2 f-th vector element is YfiUsing the 2f-1 th real number vector element Y of YfrAnd 2f real number vector element YfiCombined into a complex number yf＝Yfr+jYfiWherein Y isfrIs yfReal part of, YfiIs yfOf (1)Section, j is an imaginary unit; then y isfThe f-th vector element, which is the complex output vector y, traverses f from 1 to m.
As can be seen from fig. 2, the system for complex dot product operation based on the non-volatile memory array according to the present invention includes an input vector conversion unit, an input matrix conversion unit, a memory calculation array unit, a dot product operation unit, and an output vector conversion unit;
the input vector conversion unit converts an n-dimensional complex input vector X into a 2 n-dimensional real vector X; the input matrix conversion unit converts the m-by-n complex input matrix H into a 2 m-by-2 n real matrix H; the memory computing array unit is designed according to a matrix H; the dot multiplication operation unit realizes X and H matrix vector dot multiplication operation on the array to obtain a 2 m-dimensional real output vector Y; the output vector conversion unit converts a 2 m-dimensional real output vector Y into an m-dimensional complex output vector Y. The dot multiplication operation unit is a nonvolatile memory array, and an array structure matrix G is equal to the transposition of a matrix H, namely G is equal to HT。
In this embodiment, the input vector conversion unit is implemented by a programmable multi-channel signal source, which is programmed when the computer inputs a complex vector
Figure BDA0003366274550000051
When the voltage is equal to x, the signal source outputs 2n paths of direct current voltages in parallel, and the 2k-1 path of voltage is equal to xkrThe 2k path voltage is equal to xkiAnd k is traversed from 1 to n.
And the direct current voltage of the k path is used as the input voltage of the k row of the memory computing hardware array.
In this embodiment, the output vector conversion unit is implemented by a programmable multi-channel oscilloscope, the oscilloscope is programmed, and when the oscilloscope receives 2m paths of direct current, an m-dimensional complex vector y is output on the computer:
Figure BDA0003366274550000052
wherein y issrIs the 2 nd sMagnitude of 1 Current, ysiFor the magnitude of the 2s current, s is traversed from 1 to m.
And the direct current of the s path is the output current of the s column of the memory computing hardware array.
As shown in fig. 3, in this embodiment, a four-row and four-column memory computing hardware array is implemented, and the complex dot product operation process corresponding to the array is as follows:
and (1) inputting the deformation of the vector.
A two-dimensional complex input vector x is set to
Figure BDA0003366274550000053
The transformed four-dimensional real number vector X is
Figure BDA0003366274550000054
Step (2) inputting the deformation of the matrix:
setting a complex input matrix h in 2 x 2 dimensions as
Figure BDA0003366274550000061
The transformed 4 x 4 dimensional real number matrix H is
Figure BDA0003366274550000062
And (3) designing a memory computing hardware array:
transposing the matrix H to obtain a matrix G that determines the array structure, i.e.
Figure BDA0003366274550000063
And (4) performing matrix vector dot product operation on the array:
the dot product of the real vector X and the real matrix H is computed in parallel using an in-memory computing hardware array operating in the real domain.
And (5) outputting the deformation of the vector:
the four-dimensional real output vector Y is
Figure BDA0003366274550000064
The deformed two-dimensional complex output vector y is
Figure BDA0003366274550000065
The matrix vector dot product operation in the complex field is realized by adding parallel voltage to the memory computing hardware array to obtain parallel current.

Claims (10)

1. A method for complex dot product operation based on a non-volatile memory array, comprising: the method comprises the following steps:
(1) converting an n-dimensional complex input vector X into a 2 n-dimensional real vector X;
(2) converting the m x n dimensional complex input matrix H into a 2m x 2n dimensional real matrix H;
(3) designing a memory computing hardware array according to the matrix H;
(4) implementing a matrix vector dot product operation on the in-memory computing hardware array;
(5) the 2 m-dimensional real output vector Y is converted into an m-dimensional complex vector Y.
2. The method of claim 1, wherein the method comprises: the step (1) comprises the following steps:
(11) let the a-th complex vector element x of the input vector xa＝xar+jxai，
Wherein x isarIs xaReal part of (x)aiIs xaThe imaginary part of (a) is,j is an imaginary unit and traverses a from 1 to n;
(12) x is to bear2a-1 vector element X as real number vector X2a-1X is to beai2 a-th vector element X as a real number vector X2a。
3. The method of claim 1, wherein the method comprises: the step (2) comprises the following steps:
(21) let each complex matrix element h of the m x n complex input matrix hbc＝hbcr+jhbci，
Wherein h isbcElements of the matrix h, representing the b, c, columns of the matrix hbcrIs hbcReal part of, hbciIs hbcJ is an imaginary unit; b is traversed from 1 to m, c is traversed from 1 to n;
(22) h is to bebcrElement H as column 2c-1 of row 2b-1 of matrix H2b-1，2c-1And element H of row 2b, column 2c2b，2cH is to bebciElement H as the 2b, 2c-1 column of matrix H2b，2c-1Will-hbciElement H as column 2c of row 2b-1 of matrix H2b-1，2c。
4. The method of claim 1, wherein the method comprises: the step (3) comprises the following steps:
(31) the matrix H is transposed to obtain a matrix G which determines the array structure, i.e. G is HT；
(32) The 2 n-by-2 m memory cells form an array with 2n rows and 2m columns, wherein the conductance of the memory cell in the d row and e column is determined by the matrix element G of the matrix GdeDetermination of where GdeThe matrix element represents the d row and the e column of the matrix G; d is traversed from 1 to 2n and e is traversed from 1 to 2 m.
5. The method of claim 1, wherein the method comprises: the step (4) comprises the following steps:
(41) let the array's row g input equal the g vector element X of the 2 n-dimensional real input vector XgMagnitude of voltage; traversing g from 1 to 2 n;
(42) obtaining the current magnitude of the kth column as the kth vector element Y of the real output vector Y with 2m dimensionskK is traversed from 1 to 2 m.
6. The method of claim 1, wherein the method comprises: in the step (5), the 2f-1 vector element of the 2 m-dimensional real number output vector Y is marked as YfrAnd the 2 f-th vector element is YfiUsing the 2f-1 th real number vector element Y of YfrAnd 2f real number vector element YfiCombined into a complex number yf＝Yfr+jYfi，
Wherein, YfrIs yfReal part of, YfiIs yfJ is an imaginary unit; then y isfThe f-th vector element, which is the complex output vector y, traverses f from 1 to m.
7. A system for complex dot product operation based on a non-volatile memory array, comprising: the system comprises an input vector conversion unit, an input matrix conversion unit, an in-memory calculation array unit, a dot product operation unit and an output vector conversion unit;
the input vector conversion unit converts an n-dimensional complex input vector X into a 2 n-dimensional real vector X;
the input matrix conversion unit converts the m-by-n complex input matrix H into a 2 m-by-2 n real matrix H;
the memory computing array unit is designed according to a matrix H;
the dot multiplication operation unit realizes X and H matrix vector dot multiplication operation on the array to obtain a 2 m-dimensional real output vector Y;
the output vector conversion unit converts a 2 m-dimensional real output vector Y into an m-dimensional complex output vector Y.
8. The system of claim 7, wherein: the in-memory computing array unit is a nonvolatile memory array, and the array structure matrix G is equal to the transpose of a matrix H, namely G-HT.
9. The system of claim 7, wherein: the input vector conversion unit comprises a programmable multi-channel signal source, the signal source is programmed, when a computer inputs an n-dimensional complex vector x, the signal source outputs 2n paths of direct current voltage in parallel, and the magnitude of the 2k-1 path of voltage is equal to xkrThe 2k path voltage is equal to xkiTraversing k from 1 to n; and the direct current voltage of the k path is used as the input voltage of the k row of the memory computing hardware array.
10. The system of claim 7, wherein: the output vector conversion unit comprises a programmable multi-channel oscilloscope, the oscilloscope is programmed, and after the oscilloscope receives 2m paths of direct current, the m-dimensional complex vector y is output on the computer.
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