CN114237382A - Configuring a base clock frequency of a processor based on usage parameters - Google Patents

Abstract

A processor, comprising: a plurality of processor cores, a control register storing a per-core base clock frequency value for a respective processing core of the plurality of processor cores, power management circuitry to execute power control unit firmware to said control clock frequencies of the plurality of processing cores based at least in part on the base clock frequency value for each core, the power management circuitry to receive a target per-core base clock frequency value that is different from a respective default per-core base clock frequency value; storing the target per-core base clock frequency value in a respective control register to cause a respective processor core of the plurality of processor cores to operate in accordance with the target per-core base clock frequency value; the target base clock frequency value per core is exposed to software.

Description

Configuring a base clock frequency of a processor based on usage parameters

The application is a divisional application of an invention patent application with the application date of 2017, 24/2, and the stage date of entering China, 22/2/2019, and the application number of 201780084195.4, and the name of the invention patent application is 'basic clock frequency based on using parameters to configure a processor'.

Technical Field

The present disclosure relates to processors and, more particularly, to configuring a fundamental frequency of a processor based on usage parameters.

Background

A computing device may include one or more processing cores in one or more processors, such as Central Processing Units (CPUs), for executing instructions. The computing device may also include a memory device (such as Random Access Memory (RAM)) for storing instructions and data associated with performing tasks on one or more processing cores, including user applications and system applications such as the kernel of an operating system. A manufacturer may design a processor to operate at a base clock frequency value, where the base clock frequency value is a guaranteed clock speed at which the processor may run at full workload without violating a Thermal Design Power (TDP) requirement of the processor. TDP indicates the maximum amount of heat generated by the processor that may be adequately dissipated by the cooling system associated with the processor. The manufacturer may tag the processor with a base clock frequency value.

Drawings

The present disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure. The drawings, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only.

Fig. 1 illustrates a system according to an embodiment of the present disclosure.

Fig. 2A illustrates a process for setting a base clock frequency during system power-up according to an embodiment of the disclosure.

Fig. 2B illustrates a process for changing a base clock frequency based on usage scenarios during runtime according to an embodiment of the present disclosure.

FIG. 3 illustrates a process for adjusting a base clock frequency value on some or selective cores to meet a target service level according to an embodiment of the disclosure.

Fig. 4 is a block diagram of a method for setting a base clock frequency value based on a target service level according to an embodiment of the present disclosure.

FIG. 5A is a block diagram illustrating a microarchitecture for a processor including heterogeneous cores in which one embodiment of the present disclosure may be used.

Fig. 5B is a block diagram illustrating an in-order pipeline and a register renaming stage, out-of-order issue/execution pipeline, implemented according to at least one embodiment of the present disclosure.

FIG. 6 illustrates a block diagram of a microarchitecture for a processor including logic, according to one embodiment of the present disclosure.

Fig. 7 is a block diagram illustrating a system in which embodiments of the present disclosure may be used.

Fig. 8 is a block diagram of a system in which embodiments of the present disclosure may operate.

Fig. 9 is a block diagram of a system in which embodiments of the present disclosure may operate.

Fig. 10 is a block diagram of a system on chip (SoC) according to an embodiment of the present disclosure.

Fig. 11 is a block diagram of an embodiment of a SoC design according to the present disclosure.

FIG. 12 illustrates a block diagram of one embodiment of a computer system.

Detailed Description

The manufacturer determines the value of the base clock frequency for the processor through a design and test process, and may mark the value of the base clock frequency on the processor. The base clock frequency value assigned by the manufacturer is typically determined based on the particular usage scenario. Examples of specific usage scenarios may be specific combinations of worst case work load, TDP objectives, reliability objectives, and the like. Manufacturers often do not provide end users with any mechanism to change the processor's base clock frequency value (e.g., to a value higher than the assigned base clock frequency value). This disabling will prevent violations of the processor's TDP requirements. While processors may include hardware features (e.g., turbo acceleration techniques) that allow the processor to operate opportunistically above the base clock frequency value specified by the manufacturer, these hardware features do not guarantee that the processor will operate at a clock speed higher than the base clock frequency value of the determined workload. Because the turbo acceleration techniques cannot guarantee a continuous clock speed of the workload, cloud service providers cannot price cloud services provided using these opportunistic high clock frequencies when a Service Level Agreement (SLA) is reached with the customer.

Embodiments of the present disclosure address the above-mentioned and other deficiencies by providing an option to the end user to set the base clock frequency of the processor to a value that is higher or lower than the manufacturer-assigned base clock frequency value for different usage scenarios. The usage scenario may be specified by a set of parameters including, for example, a target number of processing cores in the processor to be used, a target amount of Thermal Design Power (TDP), a target workload (e.g., as a percentage of TDP), and a target reliability measure (e.g., a lifetime of the processor). Embodiments may include a user interface that may provide a user with an option to select a target usage scenario from a list of usage scenarios. For example, the user interface may include these options during the boot process. Alternatively, an application running on the processor may provide these options. The processor or controller circuitry associated with the processor may utilize the selected usage scenario to determine a target base clock frequency value for a set of processing cores in the processor. The set of processing cores may be less than all of the processing cores in the processor (e.g., 2 out of 6 processing cores). The processor or controller may also utilize the usage scenario to determine a target set of base clock frequency values for a plurality of disjoint sets of processing cores in the processor (e.g., 2 processing cores of the 6 processing cores at a first base clock frequency value (X) and the remaining 4 processing cores of the 6 processing cores at a second base clock frequency value (Y)). Additionally, the processor may update a base clock frequency value used by firmware (PCU firmware) running on power management circuitry associated with the processor to a target base clock frequency value. The PCU firmware may calculate power consumption and heat generation based on a target base clock frequency value for a set of processing cores. In response to setting the PCU calculation according to the target base clock frequency value, the processor may configure the set of processing cores to operate at the target base clock frequency value and enable the set of processing cores to operate at the target base clock frequency value. In this way, the cloud service provider can price the enhanced target base clock frequency value with the end user in a service level agreement.

Fig. 1 illustrates a system 100 according to an embodiment of the present disclosure. As shown in fig. 1, a processing system 100 (e.g., a system on a chip (SOC) or a motherboard of a computer system) may include a processor 102 and a memory device 104 communicatively coupled to the processor 102. The processor 102 may be a hardware processing device, such as, for example, a Central Processing Unit (CPU) or a Graphics Processing Unit (GPU) that includes one or more processing cores 108 to execute software applications. The system 100 may also include a Basic Input Output System (BIOS) chipset 106 to store system boot instructions during system boot (e.g., at power up). The BIOS chipset 106 may be a Read Only Memory (ROM) or a flash memory to store the instructions.

Processor 102 may also include processing core 108, power management circuitry 110 (such as, for example, a Power Control Unit (PCU) for an x86 processor), and control registers 112, 114, 126. The processing cores 108 in various embodiments may be provided by in-order cores or out-of-order cores. In an illustrative example, processing core 108 may have a microarchitecture that includes processor logic and circuitry to implement an Instruction Set Architecture (ISA). Processors 102 with different microarchitectures may share at least a portion of a common instruction set. For example, the same register architecture of an ISA may be implemented differently in different microarchitectures using various techniques, including dedicated physical registers, one or more dynamically allocated physical registers using a register renaming mechanism (e.g., using a Register Alias Table (RAT), a reorder buffer (ROB), and a retirement register file), as shown by fig. 6-7.

As discussed above, during preparation and testing of the processor, the manufacturer may determine the base clock frequency value for the processor 102. The base clock frequency value is the highest authenticated clock speed at which the processor 102 may run at a predetermined workload (e.g., the worst workload). The workload of a task running on the processor 102 may be measured in terms of the number of clock cycles used to carry out the task. The upper limit of the instructions executable at each clock cycle is determined based on a number of factors including the heat generated by executing these instructions. In one embodiment, the processor 102 may include a control register 112, referred to as a processor Base Clock Frequency (BCF) register, to store a base clock frequency value assigned to the processor 102. The predetermined basic clock frequency value is a default initial value stored in the control register 112. In one embodiment, each of the processing cores 108 may be associated with a respective control register 114 to store a corresponding base clock frequency value for the corresponding core 108. Each control register 114 obtained from the manufacturer may store a default base clock frequency value assigned to the processor 102. Additionally, the control register 126 may store an association mask to indicate which processing cores 108 are active. In one embodiment, the association mask 126 is a bitmap in which each bit stores an active state for a corresponding processing core. For example, when a bit is set to an active state (e.g., "1"), the corresponding processing core will operate according to the base clock frequency value associated with the processing core. When a bit is set to an inactive state (e.g., "0"), the corresponding processing core is unavailable to the software application or is idle. In one embodiment, the power management circuitry 110 may determine which processor cores 108 are active and set bits in the association mask corresponding to the active processing cores to an active state and set bits corresponding to the inactive processing cores to an inactive state. In another embodiment (as discussed in connection with fig. 3), system software 122 may set an association mask.

In another embodiment, processor BCF registers 112 may store a data structure including data items, where each data item may include a processing core identifier and a corresponding value for each core base clock frequency, as well as an association mask bit. In another embodiment, the BCF registers 112 may store references to data structures stored in memory, where the data structures include data items. Thus, the processing core 108 may operate according to each core base clock frequency value stored in the data structure. Each core base clock frequency value allows each processing core to operate at its own base clock frequency, which may be different from another processing core or from the base clock frequency value of processor 102.

The power management circuit 110 may be a microcontroller programmed with Power Control Unit (PCU) firmware 116. The PCU firmware 116 may include code encoding functionality associated with managing processor temperature based on a base clock frequency value for the processor 102 and/or each core base clock frequency value for the processing core 108. In one embodiment, during boot, the power management circuitry 110 executing the PCU firmware 116 reads the BIOS instructions 120 stored in the BIOS chipset 106 to perform initialization of the system 100. The PCU firmware 116 may also include code for managing base clock frequency values associated with the processor 102 and/or the processing cores 108 based on thermal sensor data and workload requests generated by the system software 122. For example, the PCU firmware 116 may turn off inactive processing cores and divert standby power to active processing cores. The PCU firmware 116 may also calculate the thermal energy generated by the processing device based on a heat generation model of the processing device. The thermal generation model may use the base clock frequency value of the active processing core as an input parameter.

The manufacturer may determine the base clock frequency value for the processor 102 based on a predetermined set of usage scenarios for processors that utilize all of the processing cores 108. In operation, the target usage scenario may be different from a predetermined set of usage conditions that have been tested by the manufacturer. In some cases, the target usage scenario may allow the processor 102 or some processing cores 108 of the processor 102 to run at a target base clock frequency value that is higher than the base clock frequency value assigned by the manufacturer. In one embodiment of the present disclosure, the processor 102 may provide a hardware interface to firmware (e.g., PCU firmware 116 during BIOS boot) to allow for changes to the base clock frequency value stored in the control registers 112 of the processor 102 and/or the value stored in the control registers 114 of the processing core 108 (including the associated mask stored in the control registers 126). Additionally, processor 102 may also expose an Application Programming Interface (API) to system software 122 (e.g., an operating system or a Virtual Machine Monitor (VMM)) to allow the system software to identify usage scenarios and send basic clock frequency requests to power management circuitry 110 using the API. The request may include a target base clock frequency value determined by system software 122 for the usage scenario. Power management unit 110 may set a target base clock frequency for one or more processing cores based on the request.

In one embodiment, the BIOS chipset 106 may generate a base clock frequency request during a boot process of the processing system 100. In another embodiment, system software (e.g., an operating system or VMM)122 may generate a base clock frequency request in response to a change in a usage scenario (e.g., addition/removal of a virtual machine). The base clock frequency request received by the power management circuit 110 may include a plurality of processing cores (a subset of the available processing cores or all of the available processing cores) determined based on the usage scenario and the target base frequency value associated with the processing cores. In response to receiving the base clock frequency request, PCU firmware 116 running on the power management circuitry 110 may set the target base frequency values associated with the processing cores and the corresponding bits in the association mask. In one embodiment, the PCU firmware 116 may change the base clock frequency value of the processor 102 by storing the target base clock frequency value in the control register 112 and change the base clock frequency of the processing core 108 by storing the target base clock frequency value in the corresponding control register 114.

In one embodiment, during a system boot process, processing system 100 may display an option to an end user to choose a usage scenario for generating a base clock frequency request to power management circuit 110 based on the end user selection. As shown in fig. 1, the BIOS chipset 106 may store instructions that, when executed during a boot process, present a BIOS user interface 118 on an input/output device (e.g., a display device and a keyboard or mouse), and the BIOS chipset 106 also stores BIOS instructions 120 for setting up the different devices of the processing system 100. The BIOS user interface 118 may present the state at different stages of the boot process on an interface device (e.g., a display device). In one embodiment, the BIOS user interface 118 may present a list of usage scenarios to the user. In response to receiving the selection of the usage scenario, the boot process may include execution of instructions (e.g., by the power management circuit 116) to generate a base clock frequency request to the power management circuit 110. The base clock frequency request may include a target base clock frequency value and, optionally, a number of processing cores operating at the target base clock frequency value. The power management circuit 110 may then set the processor 102 based on the received base clock frequency request.

Fig. 2A illustrates a process 200 of setting a base clock frequency during a system boot process according to an embodiment of the disclosure. As shown in FIG. 2A, at 202, the system 100 may initiate a boot process. A controller of the processor 102 (e.g., the power management circuit 110) may read sequences of instructions stored in the BIOS chipset to set up the various devices associated with the system 100. The boot process may also present the status of the boot process on a display device. In response to executing the instructions to configure the processor 102 of the system 100, at 204, the boot process may display a list of usage scenarios on a display device for user selection. Each usage scenario may specify a set of parameters including, for example, a target number of processing cores in the processor to be used, a target Thermal Design Power (TDP), a target workload (e.g., as a percentage of TDP), and a target reliability measure. The user may select a usage scenario from the list of usage scenarios that matches his or her needs. At 206, the system boot instructions may receive a selection and, at 208, also determine whether the selected usage scenario is a default usage scenario, where the default usage scenario is one of those scenarios tested by the manufacturer and assigned a base clock frequency value that is marked on the processor. In response to determining that the selected usage scenario is the default usage scenario, at 222, the boot process may continue with other instructions to set up devices other than the processor 102, while the processor 102 will run at the assigned base clock frequency, and after the boot process is completed, the system software is handed over.

In response to determining that the selected usage scenario is not the default usage scenario, the boot process may continue with executing instructions to determine a target base clock frequency based on the selected usage scenario, at 210. The list of usage scenarios may be constructed as additional usage scenarios during manufacture of the processor, and corresponding base clock frequencies may be determined. The controller (e.g., power management circuitry 110 executing PCU firmware 116) may determine a target base clock frequency value for the selected usage scenario. In one embodiment, this is implemented as a conversion table that includes a mapping from usage scenarios to target base clock frequency values. For example, the table may contain a list of activation core counts and corresponding base frequency values. Depending on the number of active core counts selected, the corresponding base frequency value will be used. The determined target base clock frequency value may be associated with the processor 102 (and, thus, all of the processing cores 108 in the processor 102). The determined target base clock frequency value may also be associated with less than all of the processing cores 108 in the processor 102. At 212, the boot process may continue executing instructions to transmit a base clock frequency request to the power management circuit 110. The base clock frequency request may include a target base clock frequency value, and optionally a number of processing cores associated with the target base clock frequency value.

At 214, the power management circuit 110 may receive a base clock frequency request from execution of instructions stored in the BIOS chipset 106. At 216, the power management circuit 110 may first update the base clock frequency value (which is the base clock frequency value assigned at the initial time) used in the various algorithms in the PCU firmware 116 to the target base clock frequency value in the received request. These algorithms in the PCU firmware may calculate thermal energy generated by various applications running on the processor 102 based on a heat generation model of the processing device, and may adjust the processor workload to ensure that the generated thermal energy does not violate the TDP associated with the processor 102. The workload may be adjusted by offloading the task to another processing device or reducing the base clock frequency value of the processing core. The power management circuit 110 may also set a base clock frequency value for the processor 102 and/or the one or more processing cores 108. In one embodiment, at 218, the power management circuit 110 may expose the target base frequency value on a hardware (or firmware) interface. An example of such a hardware interface may be a CPUID instruction that may expose a base clock frequency value of the processor or a Model Specific Register (MSR) within each processing core, which when read returns a new base clock frequency value. Exposure to the target base clock frequency may be achieved by making control registers 112 and/or control registers 114 (including association mask 126) visible to system software 122. This may allow the system software 122 to query the target base frequency value.

If the power management circuit 110 receives a base clock frequency request that includes a target base clock frequency value for the processor 102 (i.e., all of the processing cores 108), the power management circuit 110 may store the target base clock frequency value in the control register 112. The processor 102 (and all processing cores 108) may operate according to a target base clock frequency value, which may be higher than the plotted value. If the power management circuitry 110 receives a base clock frequency request that includes a set of processing cores 108 (e.g., less than all of the processing cores 108) and their corresponding target base clock frequency values, the power management circuitry 110 may store these target base clock frequency values in the corresponding control registers 114. The power management circuit 110 may also set an active state (e.g., a corresponding bit in the association mask) associated with the set of processing cores 108 to an active state, allowing the set of processing cores 108 to operate at the target base clock frequency value. These target base clock frequency values may be different from (e.g., higher than) the plotted values.

At 220, the power management circuit 110 may optionally set other hardware components that may operate based on the base clock frequency. For example, the power management circuit 110 may set a timestamp counter (TSC) to run at the target base clock frequency value. In response to setting all hardware components to run at the target base clock frequency, the boot process may continue with other instructions to set devices other than the processor 102 at 222.

In another embodiment, the system software 122 during operation may also present a selection of usage scenarios for the user to select. Based on the user selection, the system software 122 may transmit a base clock frequency request to the power management circuit 110 via the API to request a change in the base clock frequency value of the processor 102 and/or one or more processing cores 108. The power management circuit 110 may similarly set the processor 102 and/or one or more processing cores 108 to operate at the target base clock frequency.

In other embodiments, the system software 122 (or the BIOS chipset 106) may transmit the target usage scenario (rather than a basic clock frequency request) to the power management circuitry 110 of the processor 102. As shown in FIG. 1, system software 122 (e.g., an operating system or VMM) running on the processor 102 may support applications. For example, an operating system may manage the execution of multiple software applications running on processor 102. In a virtualized system, the VMM may support a Virtual Machine (VM) 124. Each VM 124 may run one or more software applications. The system software 122 may monitor software usage scenarios associated with the processor 102. The software usage scenario may include multiple processing cores in the processor to be used, thermal design power, operational load (e.g., as a percentage of TDP), and reliability measures. In response to determining a change in the usage scenario associated with the processor 102, the system software 122 may inform the PCU firmware 116 via an API of the change. For example, a change in usage scenario may be caused by the addition (or exit) of one or more VMs, thus increasing (or decreasing) the number of active VMs supported by the VMM. The change may also be caused by the installation (or removal) of the software application.

The PCU firmware 116 running on the power management circuitry 110 may use the usage scenario to determine a target base clock frequency value based on the usage scenario and update the base clock frequency of the processor 102 and/or the one or more processing cores 108 to the target base clock frequency value. Power management circuit 110 may declare the target base clock frequency value to system software 122. For example, the power management circuit 110 may dynamically update the base clock frequency to a target value and generate an interrupt to inform the system software 122 of the update.

Fig. 2B illustrates a process 230 for changing a base clock frequency based on a usage scenario according to an embodiment of the disclosure. As shown in FIG. 2B, at 232, the usage scenario of processor 102 may change due to a change in the software environment. At 234, in response to detecting a usage scenario change (e.g., a change from a first usage scenario to a second usage scenario), system software 122 may determine a new usage scenario for processor 102. The new usage scenario may specify a target number of processing cores in the processor to be used, a target thermal design power, a target workload (e.g., as a percentage of TDP), and a target reliability measure. At 236, the system software 122 running on the processor 102 may transmit the new usage scenario to the power management circuit 110 via the API, requesting an update of the base clock frequency value of the processor 102 and/or the one or more processing cores 108.

At 238, the power management circuit 110 may receive the new usage scenario and calculate a target base clock frequency value, and optionally a number of processing cores operating at the target base clock frequency value. Similar to the boot process, at 240, the power management circuitry 110 may update parameters associated with the PCU firmware 116 to reflect the target base clock frequency value. Accordingly, the PCU firmware 116 can monitor the thermal energy generated by the processor 102 based on the target base clock frequency value. At 242, the power management circuitry 110 may store the power management circuitry 110 in the control registers 112 and/or the control registers 114 (including the association mask 126) associated with those target processing cores 118, thus preparing the processor 102 and/or one or more processing cores 118 to operate at the target base clock frequency value under the new usage scenario. In response to preparing the processor 102 to run at the target base clock frequency value, the power management circuit 110 may notify the system software 122 via a hardware (or firmware) interface of the base clock frequency value update. In one embodiment, the power management circuit 110 may send a notification by triggering an interrupt event that may be captured by the system software 122.

At 244, the system software 122 running on the processor 102 may receive (e.g., by detecting an interrupt event) a notification of an update to the base clock frequency value. The notification may include a target base clock frequency value at which the processor 102 (or the set of processing cores 108) is to run. In this manner, the system 100 may dynamically change its base clock frequency value based on the usage scenario.

The flexibility to reconfigure the base clock frequency of the processor and/or one or more processing cores therein allows a computing service provider (i.e., a cloud service provider or an enterprise-class service provider) to provide variable levels of service to customers and then charge for service. The computing service provider and the customer may agree on a Service Level Agreement (SLA), which is a contract that specifies the quality of service guarantees made by the computing service provider to the customer. The services provided may include providing one or more types of software objects, such as, for example, virtualized instances of virtual machines and operating systems (referred to as containers). Each of the software objects may operate at a target service level, which may be provided by a processing core operating at a different base clock frequency value. The target service level may also include other parameters such as, for example, the allowable power to be consumed by the software (as a ratio to TDP), allowable software object instruction mix, allowable reliability/wear rate, and exclusivity of using the processing core. System software 122 may query processor 102 via the API to determine whether processor 102 can ensure the target service level, and store parameters for the target service level in a service level data structure associated with system software 122. In some implementations, the higher the target service level (e.g., the higher the target number of processing cores and/or the higher the basic clock frequency), the higher the cost associated with providing the target service level.

Embodiments of the present disclosure allow a computing service provider to increase the base clock frequency value associated with one or more processing cores to meet a target service level specified by a customer. In one embodiment, the system software 122 may determine whether the current service level stored in the service level data structure satisfies the customer's request and, if not, determine that the conditions of the customer's request are satisfied. Additionally, in response to determining that a higher base clock frequency value is needed to satisfy the client's request, the system software 122 may determine whether the base clock frequency value of the processor and/or the one or more processing cores may be increased to satisfy the request. In this manner, system software 122 may adjust the base clock frequency value associated with processor 102 to meet the target service level requested by the customer.

Fig. 3 illustrates a process 300 for adjusting a base clock frequency value to meet a target service level according to an embodiment of the disclosure. As shown in fig. 3, at 302, a customer (bound by an SLA with a cloud service provider) may request a set of software objects (e.g., VMs, containers, and/or processes) via a user interface and specify a target service level at which the set of software objects runs. The target service level may include the time required to accomplish a particular task. Thus, a target service level may be satisfied by utilizing different combinations of processing cores operating at different base clock frequency values. At 304, system software 122 executing on processor 102 may generate a set of software objects (e.g., VMs or containers) and store the target service level in a service level data structure. At 306, the system software 122 executing on the processor 102 may determine, via the API, which available processing cores 108 may support the target service level stored in the service level data structure at their current base clock frequency value.

At 306, the system software 122 executing on the processor 102 may also determine whether there are enough available processing cores to support the target service level. In response to determining that there are enough processing cores 108 to support the target service level requested by the customer, at 310, the system software 122 executing on the processor 102 may notify the power management circuitry 110 via the API, and cause the power management circuitry 110 to set these supported processing cores to run at their current base clock frequency value. At 312, system software 122 executing on processor 102 may also execute instructions to set an association mask to limit services provided to customers from being provided from these available and capable processing cores identified at 306 and 308. At 314, system software 122 executing on the processor 102 may deploy a software object on the processor 102, which may run on the identified processing core according to the association mask.

In response to determining that there are not enough processing cores to support the target service level requested by the customer, at 316, system software 122 executing on processor 102 may direct power management circuitry 110 to increase the base clock frequency of the available processing cores to the target base clock frequency value, thus satisfying the target service level requested by the customer. At 318, the power management circuit 110 may determine whether it has exhausted the hardware change option to meet the target service level. In one embodiment, the determination may be based on the number of times the base clock frequency value has been increased beyond a threshold value. In another embodiment, the determination may be capped based on the increased base clock frequency value. If the power management circuitry 110 determines that the hardware change option has not been exhausted, the power management circuitry 110 may notify the system software 122 (e.g., by sending an interrupt event) to determine whether the processor 102 has enough software objects to perform a task at the target service level. If power management unit 110 determines that the hardware change option is exhausted, power management circuitry 110 may notify system software 122 (e.g., by sending an interrupt event), deny deployment of the software object requested by the customer, or alternatively take the software object offline to other systems at 320.

Fig. 4 is a block diagram of a method 400 for setting a base clock frequency value based on a target service level according to an embodiment of the present disclosure. The method 400 may be performed by processing logic that may comprise hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, etc.), software (such as instructions run on a processing device, a general purpose computer system, or a dedicated machine), firmware, or a combination thereof. In one embodiment, the method 400 may be carried out in part by the processor 102 and the power management circuit 110 as shown in FIG. 1.

For simplicity of explanation, the methodology 400 is depicted and described as a series of acts. However, acts in accordance with the present disclosure may occur in various orders and/or concurrently, and with other acts not presented and described herein. Also, not all illustrated acts may be performed to implement the methodology 400 in accordance with the disclosed subject matter. Further, those skilled in the art will understand and appreciate that the methodology 400 can alternatively be represented as a series of interrelated states via a state diagram or events.

Referring to FIG. 4, at 402, the processor 102 may receive a specification including a target service level associated with a software object, wherein the target service level includes a first base clock frequency value associated with a plurality of processing cores of a processing device.

At 404, the processor 102 may determine whether there are sufficient processing cores available in the processor to support the target service level.

At 406, in response to determining that the processing device does not have enough processing cores, the processor 102 may transmit a request to a power management unit of the processing device to cause the available processing cores to operate at a second base clock frequency value that is higher than the first base clock frequency value.

Fig. 5A is a block diagram illustrating a microarchitecture for a processor 500, the processor 500 implementing a processing device including heterogeneous cores, according to one embodiment of the present disclosure. In particular, processor 500 depicts an in-order architecture core and register renaming logic, out-of-order issue/execution logic to be included in a processor in accordance with at least one embodiment of the present disclosure.

The processor 500 includes a front end unit 530 coupled to an execution engine unit 550, and both coupled to a memory unit 570. The processor 500 may include a Reduced Instruction Set Computing (RISC) core, a Complex Instruction Set Computing (CISC) core, a Very Long Instruction Word (VLIW) core, or a hybrid or alternative core type. As yet another option, the processor 500 may include special purpose cores such as, for example, a network or communication core, compression engine, graphics core, and the like. In one embodiment, processor 500 may be a multi-core processor or may be part of a multi-processor system.

Front end unit 530 includes a branch prediction unit 532 coupled to an instruction cache unit 534, instruction cache unit 534 coupled to an instruction Translation Lookaside Buffer (TLB)536, instruction Translation Lookaside Buffer (TLB)536 coupled to an instruction fetch unit 538, and instruction fetch unit 538 coupled to a decode unit 540. Decode unit 540 (also referred to as a decoder) may decode instructions and generate as output one or more micro-operations, microcode entry points, microinstructions, or other instruction or other control signals that are decoded from, or otherwise reflect, or are derived from, the original instructions. Decoder 540 may be implemented using a variety of different mechanisms. Examples of suitable mechanisms include, but are not limited to, look-up tables, hardware implementations, Programmable Logic Arrays (PLAs), microcode read-only memories (ROMs), and the like. Instruction cache unit 534 is also coupled to memory unit 570. The decode unit 540 is coupled to a rename/allocator unit 552 in the execution engine unit 550.

The execution engine unit 550 includes a rename/allocator unit 552 coupled to a retirement unit 554 and a set of one or more scheduler units 556. The one or more scheduler units 556 represent any number of different schedulers, including Reservation Stations (RSs), central instruction windows, and so forth. The one or more scheduler units 556 are coupled to the one or more physical register file units 558. Each of the one or more physical register file units 558 represents one or more physical register files, different ones of which store one or more different data types (such as scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point, etc.), states (e.g., an instruction pointer to an address of a next instruction to be executed), and so forth. One or more physical register file units 558 overlap retirement unit 554 to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using one or more reorder buffers and one or more retirement register files, using one or more future files, one or more history buffers and one or more retirement register files; using register mappings and register pools, etc.).

In one embodiment, the processor 500 may be the same as the processor 102 described with respect to FIG. 1. In particular, the processor 500 may include the power management circuit 110, and the power management circuit 110 will set a base clock frequency value for the processing core 108, as shown in FIG. 1.

Typically, architectural registers are visible from outside the processor or from a programmer's perspective. The registers are not limited to any known particular type of circuitry. Various different types of registers are suitable so long as the various different types of registers are capable of storing and providing data as described herein. Examples of suitable registers include, but are not limited to, dedicated physical registers, dynamically allocated physical registers using register renaming, a combination of dedicated and dynamically allocated physical registers, and the like. Retirement unit 554 and one or more physical register file units 558 are coupled to one or more execution clusters 560. One or more execution clusters 560 include one or more sets of execution units 562 and one or more sets of memory access units 564. Execution units 562 may perform various operations (e.g., shifts, additions, subtractions, multiplications) and operate on various types of data (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point).

While some embodiments may include multiple execution units dedicated to a particular function or set of functions, other embodiments may include only one execution unit or multiple execution units that all perform all functions. The one or more scheduler units 556, the one or more physical register file units 558, and the one or more execution clusters 560 are shown as possibly plural because certain embodiments create separate pipelines for certain types of data/operations (e.g., a scalar integer pipeline, a scalar floating point/packed integer/packed floating point/vector integer/vector floating point pipeline, and/or a memory access pipeline (each memory access pipeline having its own scheduler unit, one or more physical register file units, and/or execution cluster) -and in the case of a separate memory access pipeline, implement certain embodiments in which only the execution cluster of that pipeline has one or more memory access units 564). It should also be understood that where separate pipelines are used, one or more of these pipelines may be issued/executed out-of-order, and the remainder in-order.

The set of memory access units 564 is coupled to a memory unit 570, which memory unit 570 may include a data prefetcher 580, a data TLB unit 572, a Data Cache Unit (DCU) 574, and a level two (L2) cache unit 576, to name a few examples. In some embodiments, DCU 574 is also referred to as a level one data cache (L1) cache. The DCU 574 may handle multiple outstanding cache misses and continue to service incoming stores and loads. DCU 574 also supports maintaining cache coherency. The data TLB unit 572 is a cache used to improve virtual address translation speed by mapping virtual and physical address spaces. In one exemplary embodiment, the memory access units 564 may include a load unit, a store address unit, and a store data unit, each of which is coupled to the data TLB unit 572 in the memory unit 570. The L2 cache element 576 may be coupled to one or more other levels of cache and ultimately to main memory.

In one embodiment, the data prefetcher 580 speculatively loads/prefetches data to the DCU 574 by automatically predicting which data will be consumed by a program. Prefetching may refer to transferring data stored in one memory location of a memory hierarchy (e.g., a lower level cache or memory) to a higher level memory location that is closer to the processor (e.g., giving a lower access latency) before the data is actually demanded by the processor. More specifically, prefetching may refer to early data retrieval from one of the lower level caches/memory to the data cache and/or prefetch buffer before the processor issues a demand for the particular data returned.

The processor 500 may support one or more instruction sets (e.g., the x86 instruction set (with some extensions that have been added with newer versions); the MIPS instruction set for MIPS technology of Sunnyvale, CA, the ARM instruction set (with optional additional extensions such as nen)) for ARM Holdings of Sunnyvale, CA).

It should be appreciated that a core may support multithreading (performing two or more parallel operations or sets of threads), and may do so in a variety of ways, including time-sliced multithreading, simultaneous multithreading (where a single physical core provides a logical core for each of the threads, and the physical cores are simultaneously multithreaded), or a combination thereof (e.g., time-sliced fetch and decode, and simultaneous multithreading thereafter, such as in parallel multithreading

In hyper-threading technology).

Although register renaming is described in the context of out-of-order execution, it should be understood that register renaming may be used in an in-order architecture. While the illustrated embodiment of the processor also includes separate instruction and data cache units and a shared L2 cache unit, alternative embodiments may have a single internal cache for both instructions and quantities, such as, for example, a level one (L1) internal cache, or multiple levels of internal cache. In some embodiments, a system may include a combination of an internal cache and an external cache, the external cache being external to the core and/or the processor. Alternatively, all caches may be external to the core and/or processor.

FIG. 5B is a block diagram illustrating an in-order pipeline and a register renaming stage, out-of-order issue/execution pipeline implemented by the processor 500 of FIG. 5A, according to some embodiments of the present disclosure. The solid line boxes in FIG. 5B show an in-order pipeline, while the dashed line boxes show a register renaming, out-of-order issue/execution pipeline. In FIG. 5B, processor 500 as a pipeline includes a fetch stage 502, a length decode stage 504, a decode stage 506, an allocation stage 508, a rename stage 510, a schedule (also called dispatch or issue) stage 512, a register read/memory read stage 514, an execute stage 516, a write back/memory write stage 518, an exception handling stage 522, and a commit stage 524. In some embodiments, the ordering of stages 502-524 may be different than shown and is not limited to the specific ordering shown in FIG. 5B.

Fig. 6 illustrates a block diagram of a microarchitecture for a processor 600 including a hybrid core, according to one embodiment of the present disclosure. In some embodiments, an instruction according to one embodiment may be implemented to operate on data elements having sizes of bytes, words, doublewords, quadwords, and the like, as well as data types, such as single and double precision integer and floating point data types. In one embodiment, the in-order front end 601 is part of the processor 600, and part of the processor 600 fetches an instruction to be executed and prepares the instruction for later use in the processor pipeline.

The front end 601 may include several units. In one embodiment, the instruction prefetcher 626 fetches instructions from memory and feeds the instructions to an instruction decoder 628, the instruction decoder 628 in turn decoding or interpreting the instructions. For example, in one embodiment, the decoder decodes a received instruction into one or more operations called "microinstructions" or "micro-operations" (also called micro ops or uops) that the machine can execute. In other embodiments, the decoder parses the instruction into an opcode and corresponding data and control fields, which are used by the microarchitecture to perform the operation according to one embodiment. In one embodiment, the trace cache 630 takes decoded uops and assembles them into an ordered sequence of programs or traces in the uop queue 634 for execution. When the trace cache 630 encounters a complex instruction, the microcode ROM 632 provides the uops needed to complete the operation.

Some instructions are converted into a single micro-operation, while others require several micro-operations to complete the entire operation. In one embodiment, if more than four micro-ops are needed to complete an instruction, decoder 628 accesses microcode ROM 632 to execute the instruction. For one embodiment, instructions may be decoded into a small number of micro-operations for processing at the instruction decoder 628. In another embodiment, instructions may be stored in microcode ROM 632 if multiple micro-ops are needed to implement an operation. The trace cache 630 refers to an entry point Programmable Logic Array (PLA) to determine the correct micro-instruction pointer for reading a micro-code sequence to complete one or more instructions from the micro-code ROM 632 in accordance with one embodiment. After the microcode ROM 632 finishes sequencing micro-operations for the instruction, the front end 601 of the machine resumes fetching micro-operations from the trace cache 630.

The out-of-order execution engine 603 is where instructions are prepared for execution. The out-of-order execution logic has multiple buffers to smooth out the instruction stream as it passes down the pipeline and is scheduled for execution, and to reorder the instruction stream to optimize performance. The allocator logic allocates the machine buffers and resources required by each uop for execution. The register renaming logic renames the logical registers to entries in a register file. The allocator also allocates entries (one for memory operations and one for non-memory operations) for each uop in one of the two uop queues in front of the following instruction scheduler: a memory scheduler, a fast scheduler 602, a slow/general floating point scheduler 604, and a simple floating point scheduler 606. The uop schedulers 602, 604, 606 determine when a uop is ready to execute based on the readiness of their associated input register operand sources and the availability of execution resources that the uop needs to complete its operation. The fast scheduler 602 of one embodiment may schedule on each half of the main clock cycle, while the other schedulers may schedule only once per main processor clock cycle. The scheduler decides to dispatch the port to schedule the uop for execution.

Register file 608, register file 610 is located between scheduler 602, scheduler 604, scheduler 606, and execution units 612, 614, 616, 618, 620, 622, 624 in execution block 611. There are separate register files 608, 610 for integer and floating point operations, respectively. Each register file 608, 610 of one embodiment also includes a bypass network that may bypass or forward only completed results that have not yet been written to the register file to new dependent uops. The integer register file 608 and floating point register file 610 are also capable of communicating data with each other. For one embodiment, integer register file 608 is split into two separate register files, one register file for the lower order 32-bit data and a second register file for the higher order 32-bit data. The floating point register file 610 of one embodiment has 128-bit wide entries because floating point instructions typically have operands from 64-bits to 128-bits in width.

Execution block 611 contains execution unit 612, execution unit 614, execution unit 616, execution unit 618, execution unit 620, execution unit 622, execution unit 624, where the instructions are actually executed. This portion includes register file 608, register file 610, register file 608, register file 610 stores the integer and floating point data operand values that the microinstructions need to execute. Processor 600 for one embodiment includes multiple execution units: address Generation Unit (AGU)612, AGU 614, fast ALU 616, fast ALU 618, slow ALU 620, floating point ALU 622, floating point move unit 624. For one embodiment, the floating point execution block 622, floating point execution block 624 perform floating point, MMX, SIMD, and SSE or other operations. The floating-point ALU 622 of one embodiment includes a 64-bit by 64-bit floating-point divider to perform divide, square root, and remainder micro-operations. For embodiments of the present disclosure, instructions involving floating point values may be handled with floating point hardware.

In one embodiment, the ALU operation goes to a high-speed ALU execution unit 616, a high-speed ALU execution unit 618. Fast ALUs 616, 618 for one embodiment may perform fast operations with an effective delay of half a clock cycle. For one embodiment, because slow ALU 620 includes integer execution hardware for long latency type operations (such as multiply, shift, flag logic, and branch processing), most complex integer operations go to slow ALU 620. Memory load/store operations are performed by AGU 612, AGU 614. For one embodiment, integer ALU 616, integer ALU 618, integer ALU 620 are described in the context of performing integer operations on 64-bit data operands. In alternative embodiments, ALUs 616, 618, 620 may be implemented to support a variety of data bits including 16, 32, 128, 256, and so on. Similarly, floating- point units 622, 624 may be implemented to support a range of operands having bits of various widths. For one embodiment, floating point units 622, 624 may operate on 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions.

In one embodiment, uop schedulers 602, 604, 606 dispatch dependent operations before the parent load has finished executing. When the uops are speculatively scheduled and executed in the processor 600, the processor 600 also includes logic to handle memory misses. If a data load misses in the data cache, there may be an outstanding dependent operation in the pipeline that leaves the scheduler temporarily with incorrect data. The playback mechanism tracks and re-executes instructions that use incorrect data. Only the relevant operations need to be played back and the independent operations are allowed to complete. The scheduler and replay mechanism of one embodiment of the processor are also designed to capture the instruction sequences for the text string comparison operation.

According to an embodiment of the disclosure, processor 600 also includes logic to implement memory address prediction for memory disambiguation. In one embodiment, execution block 611 of processor 600 may include a memory address predictor (not shown) for performing memory address prediction for memory disambiguation.

The term "register" may refer to an on-board processor storage location that is used as part of an instruction to identify operands. In other words, the registers may be those that are accessible from outside the processor (from the programmer's perspective). However, the registers of an embodiment should not be limited in meaning to a particular type of circuit. Rather, the registers of an embodiment are capable of storing and providing data, and performing the functions described herein. The registers described herein may be implemented by circuitry within a processor using any number of different techniques, such as dedicated physical registers, dynamically allocated physical registers using register renaming, a combination of dedicated and dynamically allocated physical registers, and so forth. In one embodiment, the integer register stores 32 bits of integer data. The register file of one embodiment also contains 8 multimedia SIMD registers for packed data.

For the following discussion, registers are understood to be data registers designed to hold packed data, such as a 64-bit wide MMXTM register (also referred to as a 'mm' register in some instances) in a microprocessor capable of MMX technology from Intel Corporation of Santa Clara, California. These MMX registers, available in both integer and floating point form, may operate with packed data elements accompanied by SIMD and SSE instructions. Similarly, 128-bit wide XMM registers related to SSE2, SSE3, SSE4, or beyond (commonly referred to as "SSEx") technology may also be used to hold such packed data operands. In one embodiment, in storing packed data and integer data, the registers need not distinguish between the two data types. In one embodiment, the integer and floating point are contained in the same register file or different register files. Also, in one embodiment, the floating point and integer data may be stored in different registers or in the same register.

Referring now to fig. 7, shown is a block diagram illustrating a system 700 in which embodiments of the present disclosure may be used. As shown in fig. 7, multiprocessor system 700 is a point-to-point interconnect system, and includes a first processor 770 and a second processor 780 coupled via a point-to-point interconnect 750. Although shown with only two processors 770, 780, it is to be understood that the scope of embodiments of the present disclosure is not so limited. In other embodiments, there may be one or more additional processors in a given processor. In other embodiments, multiprocessor system 700 may implement a hybrid core as described herein.

Processor 770 and processor 780 are shown including an integrated memory controller unit 772 and an integrated memory controller unit 782, respectively. Processor 770 also includes a point-to-point (P-P) interface 776 and a point-to-point (P-P) interface 778 as part of its bus controller unit; similarly, second processor 780 includes a P-P interface 786 and a P-P interface 788. Processors 770, 780 may exchange information via a point-to-point (P-P) interface 750 using P-P interface circuits 778, 788. As shown in fig. 7, IMCs 772 and 782 couple the processors to respective memories (i.e., memory 732 and memory 734), which may be portions of main memory locally attached to the respective processors.

Processor 770, processor 780 may each exchange information with a chipset 790 via individual P-P interfaces 752, 754 using a point-to-point interface circuit 776, a point-to-point interface circuit 794, 786, 798. Chipset 790 may also exchange information with a high-performance graphics circuit 738 via a high-performance graphics interface 739.

A shared cache (not shown) may be included in the processor or outside of both processors, but connected with the processors via a P-P interconnect, such that if the processors are placed in a low power mode, local cache information for either or both processors may be stored in the shared cache.

Chipset 790 may be coupled to a first bus 716 via an interface 796. In one embodiment, first bus 716 may be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or another third generation I/O interconnect bus, although the scope of the present disclosure is not so limited.

As shown in fig. 7, various I/O devices 714 may be coupled to first bus 716, along with a bus bridge 718, which couples first bus 716 to a second bus 720. In one embodiment, second bus 720 may be a Low Pin Count (LPC) bus. In one embodiment, various devices may be coupled to second bus 720 including, for example, a keyboard and/or mouse 722, communication devices 727, and a storage unit 728 (such as a disk drive or other mass storage device which may include/code and data 730). Additionally, an audio I/O724 may be coupled to second bus 720. Note that other architectures are possible. For example, instead of the point-to-point architecture of fig. 7, a system may implement a multi-drop bus or other such architecture.

Referring now to FIG. 8, shown is a block diagram of a system 800 in which one embodiment of the present disclosure may operate. The system 800 may include one or more processors 810, 815, the one or more processors 810, 815 being coupled to a Graphics Memory Controller Hub (GMCH) 820. Optional nature of the additional processor 815 is indicated generally by the dashed lines in fig. 8. In one embodiment, processors 810, 815 implement a hybrid core according to embodiments of the disclosure.

Each processor 810, 815 may be a circuit, an integrated circuit, some version of a processor, and/or a silicon integrated circuit as described above. It should be noted, however, that integrated graphics logic and integrated memory control units are unlikely to be present in processor 810, 815. Fig. 8 illustrates that the GMCH 820 may be coupled to a memory 840, which may be, for example, a Dynamic Random Access Memory (DRAM). For at least one embodiment, the DRAM may be associated with a non-volatile cache.

The GMCH 820 may be a chipset, or a portion of a chipset. The GMCH 820 may communicate with one or more processors 810, 815 and control interaction between the one or more processors 810, 815 and the memory 840. The GMCH 820 may also serve as an accelerated bus interface between one or more of the processor 810, the processor 815, and other elements of the system 800. For at least one embodiment, the GMCH 820 communicates with one or more of the processors 810, 815 via a multi-drop bus, such as a Front Side Bus (FSB) 895.

Also, the GMCH 820 is coupled to a display 845 (such as a flat panel display or touch screen display). The GMCH 820 may include an integrated graphics accelerator. GMCH 820 is also coupled to an input/output (I/O) controller hub (ICH)850, which ICH 850 may be used to couple various peripheral devices to system 800. For example, shown in the embodiment of fig. 8 is an external graphics device 860 coupled to the ICH 850, along with another peripheral device 870, the external graphics device 860 may be a discrete graphics device.

Alternatively, additional or different processors may also be present in system 800. For example, the one or more additional processors 815 may include one or more additional processors that are the same as processor 810, one or more additional processors that are heterogeneous or asymmetric to processor 810, accelerators (such as, for example, graphics accelerators or Digital Signal Processing (DSP) units), field programmable gate arrays, or any other processor. Depending on the metric spectrum of metrics including architectural, microarchitectural, thermal, power consumption characteristics, etc., there may be a variety of differences between one or more of processors 810, 815. These differences may effectively manifest themselves as asymmetries and heterogeneity amongst the processors 810, 815. For at least one embodiment, the various processors 810, 815 may reside in the same die package.

Referring now to FIG. 9, shown is a block diagram of a system 900 in which embodiments of the present disclosure may operate. Fig. 9 illustrates processor 970, processor 980. In one embodiment, processors 970, 980 may implement a hybrid core as described above. Processors 970, 980 may include integrated memory and I/O control logic ("CL") 972 and I/O control logic ("CL") 982, respectively, and communicate with each other via a point-to-point interconnect 950 between a point-to-point (P-P) interface 978 and a point-to-point (P-P) interface 988, respectively. Processor 970, and processor 980 each communicate with a chipset 990 via a point-to-point interconnect 952 and a point-to-point interconnect 954 through a respective P-P interface 976 to P-P interface 994 and a respective P-P interface 986 to P-P interface 998, as shown. For at least one embodiment, the CL 972, CL 982 may include integrated memory controller units. The CL 972, CL 982 may include I/O control logic. As depicted, memory 932, 934, which is coupled to CL 972, CL 982, and I/O devices 914, is also coupled to control logic 972, control logic 982. Legacy I/O devices 915 are coupled to the chipset 990 via an interface 996.

Embodiments may be implemented in many different system types. Fig. 10 is a block diagram of a SoC 1000 according to an embodiment of the present disclosure. The dashed box is an optional feature on more advanced socs. In some implementations, the SoC 1000 as shown in fig. 10 includes features of the SoC 100 as shown in fig. 1. In fig. 10, one or more interconnect units 1012 are coupled to: an application processor 1020, the application processor 1020 including one or more core sets 1002-N and one or more shared cache units 1006; a system agent unit 1010; one or more bus controller units 1016; one or more integrated memory controller units 1014; a set or one or more media processors 1018, which set or one or more media processors 1018 may include integrated graphics logic 1008, an image processor 1024 to provide still and/or video camera functionality, an audio processor 1026 to provide hardware audio acceleration, and a video processor 1028 to provide video encoding/decoding acceleration; a Static Random Access Memory (SRAM) unit 1030; a direct memory access (DAM) unit 1032; and a display unit 1040 for coupling to one or more external displays. In one embodiment, the memory modules may be included in one or more integrated memory controller units 1014. In another embodiment, the memory module may be included in one or more other components of SoC 1000 that may be used to access and/or control memory. Application processor 1020 may include a memory address predictor for implementing a hybrid core as described in embodiments herein.

The memory hierarchy includes one or more levels of cache within the core, a set of shared cache units 1006, or one or more shared cache units 1006, and an external memory (not shown) coupled to the set of integrated memory controller units 1014. The set of shared cache units 1006 may include one or more mid-level caches, such as a second level (L2), third level (L3), fourth level (L4), or other levels of cache, Last Level Cache (LLC), and/or combinations thereof.

In some embodiments, one or more of the cores 1002A-N are capable of multithreading. The system agent 1010 includes those components that coordinate and operate the cores 1002A-N. The system agent unit 1010 may include, for example, a Power Control Unit (PCU) and a display unit. The PCU may be or include the logic and components necessary to regulate the power states of cores 1002A-N and integrated graphics logic 1008. The display unit is used to drive one or more externally connected displays.

Depending on the architecture and/or instruction set, the cores 1002A-N may be homogeneous or heterogeneous. For example, some of cores 1002A-N may be ordered while others are unordered. As another example, two or more of the cores 1002A-N may be capable of executing the same instruction set, while others may be capable of executing only a subset of that instruction set or a different instruction set.

The application processor 1020 may be a general purpose processor, such as Intel (R) available from Intel corporation of Santa Clara, Calif^TMCore available from Corporation, of Santa Clara, Calif.)^TMi3, i5, i7, 2Duo and Quad, Xeon^TM、Itanium^TM、Atom^TMOr Quark^TMA processor. Alternatively, the application processor 1020 may be from another company, such as ARM Holdings, Inc. (ARM Holdings)^TM)、MIPS^TMAnd the like. The application processor 1020 may be a special purpose processor such as, for example, a network or communication processor, compression engine, graphics processor, co-processor, embedded processor, or the like. The application processor 1020 may be implemented on one or more chips. The application processor 1020 may be part of and/or implemented on one or more substrates using any of a variety of process technologies, such as, for example, BiCMOS, CMOS, or NMOS.

Fig. 11 is a block diagram of an embodiment of a system-on-chip (SoC) design according to the present disclosure. As a specific illustrative example, SoC 1100 is included in a User Equipment (UE). In one embodiment, a UE refers to any device to be used by an end user to communicate (such as a handheld phone, a smart phone, a tablet computer, an ultra-thin notebook, a notebook with a broadband adapter, or any other similar communication device). Often, the UE is connected to a base station or node, which potentially corresponds in nature to a Mobile Station (MS) in a GSM network.

Here, SOC 1100 includes 2 cores-1106 and 1107. Core 1106 and core 1107 may conform to an instruction set architecture, such as based on

Architectural core^TMA high-level micro device corporation (AMD) processor, a MIPS-based processor, an ARM-based processor design, or a customer thereof, and a license holder or adopter thereof. Core 1106 and core 1107 are coupled to cache control 1108, cache control 1108 being associated with bus interface unit 1109 and L2 cache 1110 to communicate with other portions of system 1100. Interconnect 1110 includes an on-chip interconnect, such as an IOSF, AMBA, or other interconnect discussed above, that potentially implements one or more aspects of the described disclosure.

The interconnect 1110 provides a communication channel to other components, such as a Subscriber Identity Module (SIM)1130 for interfacing with a SIM card, a boot ROM 1135 for holding boot code for execution by the core 1106 and the core 1107 to initialize and boot the SoC 1100, an SDRAM controller 1140 for interfacing with external memory (e.g., DRAM 1160), a flash controller 1145 for interfacing with non-volatile memory (e.g., flash memory 5), a peripheral control device 1150 (e.g., a serial peripheral interface) for interfacing with a peripheral device, a video codec 1120 and a video interface 116116116for displaying and receiving inputs (e.g., touch-enabled inputs), a GPU 1115 for performing graphics-related computations, and so forth. Any of these interfaces may incorporate aspects of the disclosure described herein. Further, system 1100 illustrates peripheral devices for communication, such as bluetooth module 1170, 3G modem 1175, GPS 1180, and Wi-Fi 1185.

Fig. 12 shows a diagrammatic representation of machine in the example form of a computer system 1200 within which a set of instructions, for causing the machine to perform any one or more of the methodologies discussed herein, may be executed. In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, or the internet. The machine may operate in the capacity of a server or a client device in a client-server network environment, or as a peer machine in a peer-to-peer (or distributed) network environment. The machine may be a Personal Computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web service tool, a server, a network router, switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Additionally, while only a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

Computer system 1200 includes a processing device 1202, a main memory 1204 (e.g., Read Only Memory (ROM), flash memory, Dynamic Random Access Memory (DRAM) such as synchronous DRAM (sdram) or DRAM (rdram), etc.), a static memory 1206 (e.g., flash memory, Static Random Access Memory (SRAM), etc.), and a data storage device 1218, which communicate with each other via a bus 1230.

Processing device 1202 represents one or more general-purpose processing devices such as a microprocessor, central processing unit, or the like. More particularly, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, Reduced Instruction Set Computer (RISC) microprocessor, Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or processors implementing a combination of instruction sets. The processing device 1202 may also be one or more special purpose processing devices such as an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), a Digital Signal Processor (DSP), network processor, or the like. In one embodiment, the processing device 1202 may include one or more processing cores. The processing device 1202 is configured to execute the processing logic 1226 for performing the operations and steps discussed herein. In one embodiment, the processing device 1202 is the same as the processor architecture 100 described with respect to fig. 1 described herein with embodiments of the present disclosure.

The computer system 1200 may also include a network interface device 1208 communicatively coupled to the network 1220. Computer system 1200 may also include a video display unit 1210 (e.g., a Liquid Crystal Display (LCD) or a Cathode Ray Tube (CRT)), an alphanumeric input device 1212 (e.g., a keyboard), a cursor control device 1214 (e.g., a mouse), and a signal generation device 1216 (e.g., a speaker). Also, computer system 1200 may include a graphics processing unit 1222, a video processing unit 1228, and an audio processing unit 1232.

The data storage device 1218 may include a machine-accessible storage medium 1224 having stored thereon software 1226 embodying any one or more of the methodologies of performing the functionality described herein (such as implementing storage address prediction for memory disambiguation as described above). Software 1226 may also reside, completely or at least partially, within the main memory 1204 as instructions 1226 and/or within the processing device 1202 as processing logic 1226 during execution thereof by the computer system 1200; the main memory 1204 and the processing device 1202 also constitute machine-accessible storage media.

Machine-readable storage medium 1224 may also be used to store instructions 1226, instructions 1226 implementing memory address prediction for hybrid cores, such as described in accordance with embodiments of the present disclosure. While the machine-accessible storage medium 1128 is shown in an example embodiment to be a single medium, the term "machine-accessible storage medium" should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) that store the one or more sets of instructions. The term "machine-accessible storage medium" shall also be taken to include any medium that is capable of storing, encoding or carrying a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present disclosure. The term "machine accessible storage medium" shall accordingly be taken to include, but not be limited to, solid-state memories and optical and magnetic media.

The following examples relate to further embodiments. Example 1 is a processor, comprising: a plurality of processing cores; a control register associated with a first processing core of the plurality of processing cores to store a first base clock frequency value, the first processing core operating at the first base clock frequency value; and a power management circuit to: receiving a base clock frequency request comprising a second base clock frequency value; storing the second base clock frequency value in the control register to cause the first processing core to operate at the second base clock frequency value; and exposing the second base clock frequency value on a hardware interface associated with the power management circuit.

In example 2, the subject matter of example 1 can further provide that the first base clock frequency value and the second base clock frequency value are clock speeds at which the processing device is to be carried out at a predetermined workload level within a Thermal Design Power (TDP) limit of the processing device.

In example 3, the subject matter of example 1 can also provide that the second base clock frequency value is different from the first base clock frequency value.

In example 4, the subject matter of example 1 can also specify that the power management circuit is to receive a base clock frequency request from at least one of a controller executing basic input/output system (BIOS) instructions or a system software application executing on the processing device.

In example 5, the subject matter of any of examples 1 and 4 may further specify that the processor executing the BIOS instructions is to: displaying a plurality of usage scenarios on an output device, wherein a usage scenario specifies at least one of a number of processing cores to be used, a target base clock frequency value at which a processing core is to operate, a target workload, or a target reliability metric; in response to receiving a selection of one of a plurality of usage scenarios, determining a second base clock frequency value based on the selected usage scenario; and transmitting a base clock frequency request including the second base clock frequency value to the power management circuit.

In example 6, the subject matter of any of examples 1 and 4 can further provide that the controller executing the BIOS instructions is to transmit, to the power management circuit, a base clock frequency request including the second base clock frequency value and an identifier associated with the first processing core.

In example 7, the subject matter of any of examples 1 and 4 may further provide that the system software application is one of an operating system or a Virtual Machine Monitor (VMM), and wherein the processing device is to execute the system software to: detecting a second usage scenario associated with the processing device; determining a second base clock frequency value based on a second usage scenario; and transmitting a base clock frequency request including the second base clock frequency value to the power management circuit.

In example 8, the subject matter of any of examples 1 and 4 can further specify that the processing device is to execute a system software application to retrieve the second base clock frequency value via the hardware interface.

In example 9, the subject matter of example 1 can also include a second control register to store an associative mask including a bit flag representing an active state of the first processing core, and wherein the power management circuit is to set the bit flag to an active state in response to storing the second base clock frequency value in the control register.

In example 10, the subject matter of example 1 can further provide that, in response to receiving the base clock frequency request, the power management circuit is to run the power control firmware according to a second base clock value.

In example 11, the subject matter of example 1 can further provide that the control register is associated with the processing device to store a first base clock frequency value at which the plurality of processing cores are to operate.

In example 12, the subject matter of example 1 can also include a second control register to store a reference to a data structure stored in the memory, wherein the data structure is to store a first base clock frequency value at which the plurality of processing cores are to operate.

Example 13 is a system, comprising: a basic input/output system (BIOS) chipset to store BIOS instructions; a processing apparatus, the processing apparatus comprising: a plurality of processing cores; a control register associated with a first processing core of the plurality of processing cores to store a first base clock frequency value at which the first processing core is to operate; and a power management circuit to calculate to: receiving a use scene of a processing device; determining a second base clock frequency value based on the usage scenario; storing the second base clock frequency value in the control register to cause the first processing core to operate at the second base clock frequency value; and exposing the second base clock frequency value on a hardware interface associated with the power management circuit.

In example 14, the subject matter of example 13 can also specify that the second base clock frequency value is different from the first base clock frequency value.

In example 15, the subject matter of example 13 can further specify that the power management circuit is to receive a base clock frequency request from at least one of a controller executing basic input/output system (BIOS) instructions or a system software application executing on the processing device.

In example 16, the subject matter of any of examples 13 and 15 may further specify that the system software application is one of an operating system or a Virtual Machine Monitor (VMM), and wherein the processing device is to execute the system software application to retrieve the second base clock frequency value via the hardware interface.

In example 17, the subject matter of example 13 can also provide that the control register is associated with the processing device to store a first base clock frequency value at which the plurality of processing cores are to operate.

In example 18, the subject matter of example 13 can also provide that the processing device further comprises: a second control register to store a reference to a data structure stored in the memory, wherein the data structure is to store a first base clock frequency value at which the plurality of processing cores are to operate.

Example 19 is a method, comprising: receiving, by a processing device, a specification comprising a target service level associated with a software object, wherein the target service level comprises a first base clock frequency value associated with a plurality of processing cores of the processing device; determining whether the processing device includes sufficient processing cores available to support the target service level; and in response to determining that the processing device does not have sufficient processing cores available to support the target service level, transmitting a request to power management circuitry of the processing device to cause the available processing cores to operate at a second base clock frequency value, the second base clock frequency value being higher than the first base clock frequency value.

In example 20, the subject matter of example 19 can further specify that the software object is one of a virtual machine or a container object.

Example 21 is an apparatus, comprising: apparatus for carrying out the method according to any one of examples 19 and 20.

Example 22 is a machine-readable non-transitory medium having program code stored thereon, the program code, when executed, performing operations comprising: receiving, by a processing device, a specification comprising a target service level associated with a software object, wherein the target service level comprises first base clock frequency values associated with a plurality of processing cores of the processing device; determining whether the processing device includes sufficient processing cores available to support the target service level; and in response to determining that the processing device does not have sufficient processing cores available to support the target service level, transmitting a request to power management circuitry of the processing device to cause the available processing cores to operate at a second base clock frequency value, the second base clock frequency value being higher than the first base clock frequency value.

In example 23, the subject matter of example 22 may further specify that the software object is one of a virtual machine or a container object.

The design may go through various stages, from creation to simulation to fabrication. The data representing the design may represent the design in a variety of ways. First, as is useful in simulations, the hardware may be represented using a hardware description language or another functional description language. Additionally, a circuit level model with logic and/or transistor gates may be generated at some stages of the design process. Also, at some stage, most designs reach a level of data representing the physical layout of various devices in the hardware model. In the case where conventional semiconductor fabrication techniques are used, the data representing the hardware model may be the data specifying the presence or absence of various features on different mask layers for masks used to produce the integrated circuit. In any representation of the design, the data may be stored in any form of a machine-readable medium. A memory or magnetic or optical storage device, such as a disk, may be a machine-readable medium to store information which is transmitted via modulated or otherwise generated optical or electrical waves to transmit such information. When an electrical carrier wave indicating or carrying the code or design is transmitted, to the extent that copying, buffering, or re-transmission of the electrical signal is performed, a new copy is made. Thus, a communication provider or a network provider may store, at least temporarily, an article of manufacture, such as information encoded into a carrier wave embodying techniques of embodiments of the present disclosure, on a tangible machine-readable medium.

A module as used herein refers to any combination of hardware, software, and/or firmware. As an example, a module includes hardware associated with a non-transitory medium to store code suitable for execution by a microcontroller, such as a microcontroller. Thus, in one embodiment, reference to a module refers to hardware specifically configured to recognize and/or execute code to be stored on non-transitory media. Also, in another embodiment, use of a module refers to a non-transitory medium including code specifically adapted to be executed by a microcontroller to perform predetermined operations. And as may be inferred, in yet another embodiment, the term module (in this example) may refer to a combination of a microcontroller and a non-transitory medium. The boundaries of modules, which are often shown as separate, often vary and potentially overlap. For example, the first module and the second module may share hardware, software, firmware, or a combination thereof, while potentially retaining some independent hardware, software, or firmware. In one embodiment, use of the term logic includes hardware, such as transistors, registers, or other hardware, such as programmable logic devices.

In one embodiment, use of the phrase 'configured to' refers to arranging, assembling, manufacturing, offering for sale, introducing, and/or designing an instrument, hardware, logic, or element to perform an assigned or determined task. In this example, if the instrument or elements thereof that are not operational are designed, coupled, and/or interconnected to perform the assigned task, the instrument or elements thereof that are not operational are still 'configured to' perform the assigned task. As a purely illustrative example, a logic gate may provide a 0 or a 1 during operation. But logic gates 'configured to' provide an enable signal to the clock do not include every potential logic gate that can provide a 1 or a 0. Instead, the logic gate is a logic gate coupled in some way that the 1 or 0 output will enable the clock during operation. It is again noted that use of the term 'configured to' does not require operation, but instead focuses on the intrinsic state of the instrument, hardware, and/or elements in which the instrument, hardware, and/or elements are designed to perform a particular task when the instrument, hardware, and/or elements are operating.

Also, in one embodiment, use of the phrases 'with', 'capable/capable', and/or 'operable' refer to some instruments, logic, hardware, and/or elements that are designed such that the instruments, logic, hardware, and/or elements can be used in a specified manner. Note that, as above, in one embodiment, use of 'with', 'capable/capable', and/or 'operable' refers to the intrinsic state of an instrument, logic, hardware, and/or element, where the instrument, logic, hardware, and/or element does not operate, but is designed such that the instrument can be used in a specified manner.

A value, as used herein, includes any known representation of a number, state, logic state, or binary logic state. Often, the use of logic levels, logic values (logical values), or logic values (logical values) is also referred to as simply representing 1's and 0's of binary logic states. For example, 1 refers to a high logic level and 0 refers to a low logic level. In one embodiment, a memory cell, such as a transistor or a flash memory cell, may be capable of holding a single logical value or multiple logical values. However, other values in the computer system have been used for representation. For example, a decimal number of tens may also be represented as a binary value 910 and a hexadecimal letter A. Thus, a value includes any representation of information that can be stored in a computer system.

Also, a state may be represented by a value or a portion of a value. As an example, a first value (such as a logic 1) may represent a default or initial state, while a second value (such as a logic 0) may represent a non-default state. Further, in one embodiment, the terms reset and set refer to default and updated values or states, respectively. For example, the default value potentially comprises a high logic value, i.e., reset, while the updated value potentially comprises a low logic value, i.e., set. Note that any combination of values may be used to represent any number of states.

The embodiments of methods, hardware, software, firmware, or code set forth above may be implemented via instructions or code stored on a machine-accessible, machine-readable, computer-accessible, or computer-readable medium that are executable by a processing element. A non-transitory machine-accessible/readable medium includes any mechanism that provides (i.e., stores and/or transmits) information in a form readable by a machine (e.g., a computer or electronic system). For example, non-transitory machine-accessible media include Random Access Memory (RAM), such as static RAM (sram) or dynamic RAM (dram); a ROM; a magnetic or optical storage medium; a flash memory device; an electrical storage device; an optical storage device; an acoustic storage device; other forms of storage devices that store information received from transitory (propagated) signals (e.g., carrier waves, infrared signals, digital signals); etc., which will be distinguished from non-transitory media from which information may be received.

Instructions for programming logic to carry out embodiments of the present disclosure may be stored in memory in a system, such as DRAM, cache, flash memory, or other storage. Also, the instructions may be distributed via a network or in other computer readable media. Thus, a machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer), but is not limited to, floppy diskettes, optical disks, read-only memories (CD-ROMs), and magneto-optical disks, read-only memories (ROMs), Random Access Memories (RAMs), erasable programmable read-only memories (EPROMs), electrically erasable programmable read-only memories (EEPROMs), magnetic or optical cards, flash memory, or a tangible machine-readable storage device for transmitting information over the internet via an electrical, optical, acoustical or other form of propagated signal (e.g., carrier waves, infrared signals, digital signals, etc.). Thus, a computer-readable medium includes any type of tangible machine-readable medium suitable for storing or transmitting electronic instructions or information in a form readable by a machine (e.g., a computer).

Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

In the foregoing specification, a detailed description has been given with reference to specific exemplary embodiments. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the disclosure as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense. Also, the foregoing use of embodiment and other exemplarily language does not necessarily refer to the same embodiment or the same example, but may refer to different and distinct embodiments, as well as potentially the same embodiment.

Claims (15)

1. A processor (102), comprising:

a plurality of processor cores (108);

each of the processor cores (108) being associated with a respective control register (114) storing a per-core base clock frequency value for a respective processing core (108) of the plurality of processor cores (108),

the per-core base clock frequency value initially comprises a default per-core base clock frequency value determined by a manufacturer of the processor (102);

a power management circuit (110) to execute Power Control Unit (PCU) firmware (116) to said control clock frequencies of the plurality of processing cores (108) based at least in part on a base clock frequency value for each core,

the power management circuit (110) is configured to:

receiving a target per-core base clock frequency value that is different from the corresponding default per-core base clock frequency value;

storing a target per-core base clock frequency value in a respective control register (114) to cause a respective processor core (108) of the plurality of processor cores (108) to operate in accordance with the target per-core base clock frequency value;

the target base clock frequency per core value is exposed to software (122).

2. The processor (102) of claim 1, wherein the default per-core base clock frequency value and the target per-core base clock frequency value are processor clock speeds at which the processor (102) is to be carried out at a predetermined workload level within a Thermal Design Power (TDP) limit of the processor (102).

3. The processor (102) of claim 1, wherein the target per-core base clock frequency value is different from a default per-core base clock frequency value.

4. The processor (102) of claim 1, wherein the power management circuit (110) exposes the target base clock frequency value per core on a hardware interface.

5. The processor (102) of claim 4, wherein the power management circuitry is to receive the target per-core base clock frequency value from at least one controller in a system executing basic input/output system (BIOS) instructions or from a system software application executing on the sub-processor (102).

6. The processor (102) of claim 1, wherein the respective control register (114) includes a Model Specific Register (MSR) and an MSR associated with each core (108) of a plurality of processor cores (108).

7. The processor (102) of claim 6, wherein the processor (102) executes a system software application to retrieve the target per-core base clock frequency value through a hardware interface.

8. The processor (102) of claim 1, wherein the power management circuit (110) is to adjust one or more workloads on the processor (102) to ensure that the thermal energy generated does not violate a Thermal Design Power (TDP) associated with the processor (102).

9. The processor (102) of claim 8, wherein the power management circuit (110) adjusts the one or more workloads by offloading tasks to another processor (102) or reducing the target base clock-per-core frequency value.

10. The processor (102) of claim 1, wherein at least one of the plurality of processing cores (108) operates at a first per-core base clock frequency and at least another one of the plurality of processing cores (108) operates at a second per-core base clock frequency.

11. The processor (102) of claim 1, further comprising a register for storing a bit map, wherein each bit of the bit map stores an active state of a corresponding processing core.

12. The processor (102) of claim 1, wherein the power management circuit (110) is to turn off one or more inactive ones of the plurality of processing cores (108) and to transfer the standby power to active ones of the plurality of processing cores (108).

13. The processor (102) of claim 1, wherein said receiving a target per-core base clock frequency value and exposing the target per-core base clock frequency value to software comprises:

executing commands of an Application Programming Interface (API) exposed by the processor (102).

14. A data prefetcher coupled to a processor and a data cache, wherein,

a prediction unit for predicting data to be consumed by the auto-prediction program and speculatively loading or prefetching the data into the data cache, an

A data retrieval unit to early retrieve data prefetched into the data cache for processing by a processor.

15. The data prefetcher of claim 14 wherein said data prefetcher is configured to:

the data to be consumed is transferred from a lower level cache or memory to a higher level cache or memory closer to the processor before the processor actually demands the data.

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