CN114236343B - Test structure and forming method, working method and circuit thereof - Google Patents
Test structure and forming method, working method and circuit thereof Download PDFInfo
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- CN114236343B CN114236343B CN202210183669.3A CN202210183669A CN114236343B CN 114236343 B CN114236343 B CN 114236343B CN 202210183669 A CN202210183669 A CN 202210183669A CN 114236343 B CN114236343 B CN 114236343B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2601—Apparatus or methods therefor
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2607—Circuits therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/0014—Measuring characteristics or properties thereof
Abstract
A test structure and a forming method, a working method and a circuit thereof relate to the technical field of semiconductors, and the test structure comprises: the device comprises a substrate, a plurality of first-level transistors and a plurality of second-level transistors, wherein the substrate comprises a plurality of device areas distributed in an array along a first direction and a second direction, and the first direction and the second direction are different; the device comprises a plurality of device structures, a plurality of first electrode layers and a plurality of second electrode layers, wherein each device structure is respectively positioned on the surface of each device area; a plurality of drain layers, each drain layer being electrically connected to a device structure; a plurality of source layers parallel to the second direction, each source layer corresponding to a row of device structures arranged along the second direction; each semiconductor layer is respectively positioned between any drain electrode layer and the corresponding source electrode layer and is respectively connected with any drain electrode layer and the corresponding source electrode layer; and the grid structures are parallel to the first direction and are respectively positioned on the surfaces of a row of semiconductor layers arranged along the first direction. The test efficiency of the test structure is improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a test structure and a forming method, a working method and a circuit thereof.
Background
A Vertical-Cavity Surface-Emitting Laser (VCSEL) is a semiconductor Laser Emitting Laser light perpendicular to a substrate Surface, and generally includes an upper bragg reflector (DBR), a lower DBR, and a middle active layer. The bragg reflector is generally formed by alternately growing two materials with different refractive indexes and the thickness of one fourth of the wavelength of light, in order to reduce optical loss, the reflectivity of the N-type bragg reflector is close to 100 percent and can be used as a total reflector of the resonant cavity, and the reflectivity of the P-type bragg reflector is relatively low and can be used as an exit mirror of the resonant cavity.
The vertical cavity surface emitting laser product needs to be tested by 100% before being cut off from a wafer, and the existing testing method has low efficiency and needs to be improved.
Disclosure of Invention
The invention provides a test structure, a forming method, a working method and a circuit thereof, which are used for improving a test method of a vertical cavity surface emitting laser.
In order to solve the above technical problem, a technical solution of the present invention provides a test structure, including: the device comprises a substrate, a plurality of first-level transistors and a plurality of second-level transistors, wherein the substrate comprises a plurality of device areas distributed in an array along a first direction and a second direction, and the first direction is different from the second direction; the device comprises a plurality of device structures, a plurality of first connecting lines and a plurality of second connecting lines, wherein each device structure is respectively positioned on the surface of each device area; a plurality of drain layers, each of the drain layers being electrically connected to one of the device structures; a plurality of source layers parallel to the second direction, each of the source layers corresponding to a row of the device structures arranged along the second direction; the semiconductor layers are respectively positioned between any drain electrode layer and the corresponding source electrode layer and are respectively connected with any drain electrode layer and the corresponding source electrode layer; and the grid structures are parallel to the first direction and are respectively positioned on the surface of a row of the semiconductor layers arranged along the first direction.
Optionally, the material of the semiconductor layer includes a semiconductor material, and the semiconductor material includes: silicon, silicon carbide, silicon germanium, a multicomponent semiconductor material of group iii-v elements including InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP, silicon-on-insulator (SOI), or germanium-on-insulator (GOI).
Optionally, the semiconductor layer has doped ions therein, and the conductivity type of the doped ions includes N type or P type.
Optionally, the doping ions with the N-type conductivity include phosphorus ions, arsenic ions, or antimony ions; the doped ions with the conductive type of P type comprise boron ions, boron-fluorine ions or indium ions.
Optionally, the substrate further includes: a scribe line region between adjacent device regions, the scribe line region including a first scribe line parallel to the first direction and a second scribe line parallel to the second direction; the semiconductor layer is located on the second cutting path, and the source electrode layer is located on the second cutting path.
Optionally, the gate structure includes a first subsection and a second subsection connected to each other, the first subsection is located on the first scribe line, an extending direction of the first subsection is parallel to the first direction, and the second subsection is located on the semiconductor layer on the second scribe line.
Optionally, the method further includes: an insulating layer between the semiconductor layer and the second section.
Optionally, the material of the insulating layer includes: silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon oxycarbonitride in combination with one or more of these.
Optionally, the material of the source layer includes a metal or a metal nitride; the metal includes: combinations of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.
Optionally, the material of the gate structure includes a metal or a metal nitride; the metal includes: a combination of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.
Optionally, the material of the drain layer comprises a metal or a metal nitride; the metal includes: combinations of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.
Optionally, the substrate includes opposite first and second sides, and the device structure is located on the device region first side surface.
Optionally, the device structure includes: a first mirror structure located on a first surface of the device region; an active layer on the first mirror structure; at least two overlapping second mirror structures on the active layer, the second mirror structures having a conductivity type opposite to the conductivity type of the first mirror structures; the light blocking layers and the light emitting layers are positioned between two adjacent second reflecting mirror structures, the light emitting layers are mutually separated, and the light blocking layers are positioned between the light emitting layers; the drain layer is located on the second mirror structure.
Optionally, the test structure further includes: and the electrode layer is positioned on the second surface of the device area.
Optionally, the material of the electrode layer comprises a metal or a metal nitride; the metal includes: combinations of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.
Optionally, the first mirror structure includes a plurality of first stacked structures, each of the first stacked structures includes a first reflective layer and a second reflective layer on the first reflective layer, and the first reflective layer and the second reflective layer have different refractive indexes.
Optionally, the material of the first reflective layer includes aluminum gallium arsenide, and the material of the second reflective layer includes gallium arsenide.
Optionally, the second mirror structure includes a plurality of second stacked structures, each of the second stacked structures includes a third reflective layer and a fourth reflective layer on the third reflective layer, and refractive indices of the third reflective layer and the fourth reflective layer are different.
Optionally, the material of the third reflective layer includes aluminum gallium arsenide, and the material of the fourth reflective layer includes gallium arsenide.
Optionally, the method further includes: the first shift register is electrically connected with the plurality of grid structures; and a second shift register electrically connected to the source layers.
Correspondingly, the technical scheme of the invention also provides a method for forming the test structure, which comprises the following steps: providing a substrate, wherein the substrate comprises a plurality of device areas distributed in an array along a first direction and a second direction, and the first direction is different from the second direction; forming a plurality of device structures on the surface of each device area; forming a plurality of drain layers on the device structures, wherein each drain layer is electrically connected with one device structure; forming a plurality of source layers on the substrate parallel to the second direction, each source layer corresponding to a row of the device structures arranged along the second direction; forming a plurality of semiconductor layers on the substrate, wherein each semiconductor layer is respectively positioned between any drain layer and the corresponding source layer; and forming a plurality of grid structures parallel to the first direction on the substrate, wherein each grid structure is respectively positioned on the surface of a row of the semiconductor layers arranged along the first direction.
Optionally, the material of the semiconductor layer includes a semiconductor material, and the semiconductor material includes: silicon, silicon carbide, silicon germanium, a multicomponent semiconductor material of group iii-v elements including InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP, silicon-on-insulator (SOI), or germanium-on-insulator (GOI).
Optionally, the process for forming the semiconductor layer includes: an epitaxial growth process or a deposition process.
Optionally, the semiconductor layer has doped ions therein, and the conductivity type of the doped ions includes N type or P type; the doped ions with the N-type conductivity comprise phosphorus ions, arsenic ions or antimony ions; the doped ions with the conductive type of P type comprise boron ions, boron-fluorine ions or indium ions.
Optionally, the substrate further includes: a scribe line region between adjacent device regions, the scribe line region including a first scribe line parallel to the first direction and a second scribe line parallel to the second direction; the semiconductor layer is located on the second cutting path, and the source electrode layer is located on the second cutting path.
Optionally, the gate structure includes a first subsection and a second subsection connected to each other, the first subsection is located on the first scribe line, an extending direction of the first subsection is parallel to the first direction, and the second subsection is located on the semiconductor layer on the second scribe line.
Optionally, before forming a plurality of gate structures on the scribe line region, the method further includes: an insulating layer is formed between the semiconductor layer and the second section.
Optionally, the material of the insulating layer includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon oxycarbonitride.
Optionally, the material of the source layer includes a metal or a metal nitride; the metal includes: combinations of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.
Optionally, the material of the gate structure includes a metal or a metal nitride; the metal includes: combinations of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.
Optionally, the material of the drain layer comprises a metal or a metal nitride; the metal includes: combinations of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.
Optionally, the substrate includes opposite first and second sides, and the device structure is located on the device region first side surface.
Optionally, the device structure includes: a first mirror structure located on a first surface of the device region; an active layer on the first mirror structure; at least two overlapping second mirror structures on the active layer, the second mirror structures having a conductivity type opposite to the conductivity type of the first mirror structures; the light blocking layers and the light emitting layers are positioned between two adjacent second reflecting mirror structures, the light emitting layers are mutually separated, and the light blocking layers are positioned between the light emitting layers; the drain layer is located on the second mirror structure.
Optionally, the method further includes: and forming an electrode layer on the second surface of the substrate device area.
Optionally, the material of the electrode layer comprises a metal or a metal nitride; the metal includes: combinations of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.
Optionally, the first mirror structure includes a plurality of first stacked structures, each of the first stacked structures includes a first reflective layer and a second reflective layer on the first reflective layer, and the first reflective layer and the second reflective layer have different refractive indexes.
Optionally, the material of the first reflective layer includes aluminum gallium arsenide, and the material of the second reflective layer includes gallium arsenide.
Optionally, the second mirror structure includes a plurality of second stacked structures, each of the second stacked structures includes a third reflective layer and a fourth reflective layer on the third reflective layer, and refractive indices of the third reflective layer and the fourth reflective layer are different.
Optionally, the material of the third reflective layer includes aluminum gallium arsenide, and the material of the fourth reflective layer includes gallium arsenide.
Optionally, the method further includes: the first shift register is electrically connected with the plurality of grid structures; and a second shift register electrically connected to the source layers.
Correspondingly, the technical scheme of the invention also provides a working method of the test structure, which comprises the following steps: providing the test structure; sequentially loading first voltages to the plurality of grid structures through the first shift register; sequentially loading a second voltage on the source electrode layers on the second cutting path through the second shift register; applying a third voltage to the electrode layer; collecting an optical signal of the device structure.
Optionally, the method further includes: and judging whether the device structure passes the performance according to the optical signal.
Optionally, the method for determining whether the device structure passes the performance according to the optical signal includes: acquiring a current signal or a voltage signal according to the optical signal; and judging whether the current signal or the voltage signal reaches a preset value, and if the current signal or the voltage signal reaches the preset value, judging that the structural performance of the device passes.
Optionally, the first voltage is a positive voltage, the second voltage is a positive voltage, and the third voltage is a negative voltage.
Correspondingly, the technical scheme of the invention also provides a circuit of a test structure, which comprises: a plurality of device structures distributed in an array; a plurality of drains, each of the drains being coupled to one of the device structures; a plurality of rows of source electrodes, each of the source electrodes corresponding to a row of the device structures; a plurality of semiconductor switches, each of the semiconductor switches being coupled to any one of the drains and the corresponding source, respectively; and the grid structures are respectively coupled with a row of the semiconductor switches.
Optionally, the method further includes: a first shift register coupled to a number of the gate structures; a second shift register coupled to a number of the sources.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
according to the technical scheme, the semiconductor layer is formed on the second cutting channel and is positioned on any source electrode layer and the adjacent drain electrode layer, and then the plurality of grid structures are formed on the cutting channel area and are positioned on the semiconductor layer. By adding a semiconductor switch on each device structure, the gate structures and the source electrode layers corresponding to a plurality of device areas are controlled to be electrified, so that the device structures on any device area can be electrified independently, the loading voltage of each device structure can be controlled in a time-sharing manner, a plurality of device structures can be automatically tested at one time, and the testing efficiency can be improved.
Drawings
FIGS. 1 to 7 are schematic structural views illustrating a test structure forming process according to an embodiment of the present invention;
FIG. 8 is a flow chart of a method of operation of a test structure in an embodiment of the present invention;
FIG. 9 is a circuit diagram of a test structure in an embodiment of the invention.
Detailed Description
As described in the background, the existing methods for testing vertical cavity surface emitting laser products still need to be improved.
Specifically, the vertical cavity surface emitting laser includes: a substrate comprising opposing first and second faces; a first mirror structure located on a first side surface of the substrate; an active layer on the first mirror structure; at least two overlapped second mirror structures located on the surface of the active layer, wherein the conductivity type of the second mirror structure is opposite to that of the first mirror structure; the light-blocking layers and the light-emitting layers are positioned between two adjacent second mirror structures, the light-emitting layers are mutually separated, the light-blocking layers are positioned between the light-emitting layers, and the projection of the light-emitting layers on the surface of the substrate is circular; a first electrode layer on top of the second mirror structure; and the second electrode layer is positioned on the second surface of the substrate.
The current testing method is as follows: the probe is pricked on the first electrode layer, positive voltage is loaded to the vertical cavity surface emitting laser through the first electrode layer, negative voltage is loaded to the vertical cavity surface emitting laser through the second electrode layer, a detector is arranged above the vertical cavity surface emitting laser and used for collecting corresponding optical signals, the optical signals are converted into current signals or voltage signals, whether the current signals or the voltage signals reach preset values or not is judged, and if the current signals or the voltage signals reach the preset values, the performance of the vertical cavity surface emitting laser is judged to pass.
Since there are many vertical cavity surface emitting lasers on one wafer, there are typically thousands of vertical cavity surface emitting lasers, after the probe has tested one vertical cavity surface emitting laser, the probe moves to the second vertical cavity surface emitting laser to continue testing, and the testing efficiency of one vertical cavity surface emitting laser is very low.
In order to solve the above problems, the present invention provides a test structure, a method for forming the same, a method for operating the same, and a circuit, wherein a semiconductor layer is formed on a second scribe line, the semiconductor layer is located on any one of source layers and adjacent drain layers, and a plurality of gate structures are formed on the scribe line region, the gate structures being located on the semiconductor layer. By adding a semiconductor switch on each device structure, the gate structures and the source electrode layers corresponding to a plurality of device areas are controlled to be electrified, so that the device structures on any device area can be electrified independently, the loading voltage of each device structure can be controlled in a time-sharing manner, a plurality of device structures can be automatically tested at one time, and the testing efficiency can be improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1 to 7 are schematic structural diagrams illustrating a test structure forming process according to an embodiment of the present invention.
Referring to fig. 1, a substrate 100 is provided, where the substrate 100 includes a first side and a second side opposite to each other, and the substrate 100 includes a plurality of device regions I distributed in an array along a first direction X and a second direction Y, where the first direction X is different from the second direction Y.
In this embodiment, the substrate 100 further includes: and the cutting path region is positioned between the adjacent device regions I and comprises a first cutting path II parallel to the first direction X and a second cutting path III parallel to the second direction Y.
In this embodiment, the first direction X and the second direction Y are perpendicular to each other.
The material of the substrate 100 comprises a semiconductor material, and in the present embodiment, the material of the substrate 100 comprises gallium arsenide.
Referring to fig. 2 and fig. 3, fig. 2 is a top view of fig. 3 with a portion of the structure omitted, and fig. 3 is a schematic cross-sectional view of the device structure of fig. 2 along a section line AA1, wherein a plurality of device structures are formed on the first surface of each device region I.
The device structure includes: the first reflector structure is positioned on the surface of the first surface of the device region I; an active layer 103 on the first mirror structure; at least two overlapped second mirror structures on the active layer 103, the second mirror structures having a conductivity type opposite to that of the first mirror structures; and a plurality of light blocking layers 108 and light emitting layers 109 positioned between two adjacent layers of the second mirror structures, wherein a plurality of the light emitting layers 109 are separated from each other, and the light blocking layers 108 are positioned between the light emitting layers 109.
The first mirror structure includes a plurality of first stacked structures including a first reflective layer and a second reflective layer 102 on the first reflective layer 101, and the first reflective layer 101 and the second reflective layer 102 have different refractive indices.
In this embodiment, the material of the first reflective layer 101 includes aluminum gallium arsenide, and the material of the second reflective layer 102 includes gallium arsenide.
The second mirror structure includes a plurality of second stacked structures including a third reflective layer 104 and a fourth reflective layer 105 on the third reflective layer 104, and refractive indices of the third reflective layer 104 and the fourth reflective layer 105 are different.
In this embodiment, the material of the third reflective layer 104 includes aluminum gallium arsenide, and the material of the fourth reflective layer 105 includes gallium arsenide.
The active layer 103 includes a plurality of first barrier layers (not shown), second barrier layers (not shown), and well layers (not shown) between the first barrier layers and the second barrier layers, which are alternately stacked in a direction perpendicular to the surface of the substrate 100.
The material of the first barrier layer comprises P-type gallium arsenide, and carbon ions are doped in the P-type gallium arsenide; the material of the second barrier layer comprises N-type gallium arsenide, and silicon ions are doped in the N-type gallium arsenide; the material of the well layer comprises gallium indium arsenide (In) 0.2 Ga 0.8 As）。
The first barrier layer, the second barrier layer and the well layer between the first barrier layer and the second barrier layer form a strain quantum well.
In this embodiment, the number of the strained quantum wells is 3, and in other embodiments, the number of the strained quantum wells is 5 or 7.
In the present embodiment, the material of the light blocking layer 108 includes aluminum oxide, and the material of the light emitting layer 109 includes aluminum gallium arsenide.
With continued reference to fig. 2 and 3, a plurality of drain layers 112 are formed on the device structures, and each drain layer 112 is electrically connected to one of the device structures.
In this embodiment, the method further includes: forming a first passivation layer 110 on top of the second reflective structure; a second passivation layer 111 is formed on the surface of the first passivation layer 110, the sidewall surface of the second reflective structure, the sidewall surface of the light blocking layer 108, the sidewall surface of the active layer 103, and a portion of the sidewall surface of the first reflective structure.
In the present embodiment, the drain layer 112 is located on the second mirror structure, and the drain layer 112 is located in the first passivation layer 110 and the second passivation layer 111.
In this embodiment, the material of the first passivation layer 110 and the second passivation layer 111 includes silicon nitride.
The material of the drain layer 112 includes a metal or a metal nitride; the metal includes: a combination of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.
Referring to fig. 4, a plurality of source layers 113 parallel to the second direction Y are formed on the second scribe line III, and each source layer 113 corresponds to a row of the device structures arranged along the second direction Y.
The material of the source layer 113 includes metal or metal nitride; the metal includes: combinations of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.
Referring to fig. 5, a plurality of semiconductor layers 114 are formed on the second scribe line III, each semiconductor layer 114 is respectively located between any one of the drain layers 112 and the corresponding source layer 113, and the semiconductor layers 114 are respectively in contact with any one of the drain layers 112 and the corresponding source layer 113.
The material of the semiconductor layer 114 includes a semiconductor material including: silicon, silicon carbide, silicon germanium, a multicomponent semiconductor material of group iii-v elements including InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP, silicon-on-insulator (SOI), or germanium-on-insulator (GOI).
In the present embodiment, the material of the semiconductor layer 114 includes silicon.
The process of forming the semiconductor layer 114 includes: an epitaxial growth process or a deposition process.
In the present embodiment, the semiconductor layer 114 has doped ions therein, and the conductivity type of the doped ions includes N type or P type; the doped ions with the N-type conductivity comprise phosphorus ions, arsenic ions or antimony ions; the doped ions with the conductive type of P type comprise boron ions, boron-fluorine ions or indium ions.
Referring to fig. 6 and 7, fig. 6 is a top view of fig. 7, fig. 7 is a schematic cross-sectional view taken along a section line BB1 in fig. 6, and fig. 7 omits a device structure, and an insulating layer 115 is formed on the semiconductor layer 114.
The material of the insulating layer 115 includes: silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and combinations of one or more of silicon oxycarbonitride.
In the present embodiment, the material of the insulating layer 115 includes silicon nitride.
The material of the semiconductor layer 114 includes silicon, and the material of the insulating layer 115 includes silicon nitride. The silicon nitride has stable performance, and prevents the material of the semiconductor layer 114 from being affected by oxidation or other influences during the process of forming the insulating layer 115.
With reference to fig. 6 and fig. 7, a plurality of gate structures parallel to the first direction X are formed on the scribe line region, and each gate structure is located on a surface of a row of the semiconductor layers 114 arranged along the first direction X.
The gate structure includes a first subsection 116 and a second subsection 117 connected to each other, the first subsection 116 is located on the first scribe line II, the extending direction of the first subsection 116 is parallel to the first direction X, and the second subsection 117 is located on the semiconductor layer 114 on the second scribe line III.
The material of the gate structure comprises metal or metal nitride; the metal includes: a combination of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.
In this embodiment, the method further includes: and forming an electrode layer (not shown) on the second surface of the device region I.
The material of the electrode layer comprises a metal or a metal nitride; the metal includes: combinations of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.
In this embodiment, the method further includes: forming a first shift register electrically connected with a plurality of grid structures; a second shift register electrically connected to the source layers 113 is formed.
The first shift register controls the energization of any one of the gate structures, and the second shift register controls the energization of any one of the source layers 113.
By adding the semiconductor layer 114, the gate structures and the source layer 113 corresponding to the device regions I are controlled to be electrified, and thus the device structures in any device region I can be electrified independently, so that the loading voltage of each device structure can be controlled in a time-sharing manner, a plurality of device structures can be automatically tested at one time, and the testing efficiency can be improved.
Accordingly, an embodiment of the present invention further provides a test structure, please continue to refer to fig. 6 and fig. 7, including:
the device comprises a substrate 100, wherein the substrate 100 comprises a plurality of device regions I distributed in an array along a first direction X and a second direction Y, and the first direction X is different from the second direction Y;
the device structure is respectively positioned on the surface of each device area I;
a plurality of drain layers 112, each of the drain layers 112 being electrically connected to one of the device structures;
a plurality of source layers 113 parallel to the second direction, each source layer 113 corresponding to a row of the device structures arranged along the second direction Y;
a plurality of semiconductor layers 114, each of the semiconductor layers 114 being located between any one of the drain layers 112 and the corresponding source layer 113, and each of the semiconductor layers 114 being connected to any one of the drain layers 112 and the corresponding source layer 113;
and a plurality of gate structures parallel to the first direction X, wherein each gate structure is located on a surface of a row of the semiconductor layers 114 arranged along the first direction X.
In this embodiment, the material of the semiconductor layer 114 includes a semiconductor material, and the material of the semiconductor layer includes a semiconductor material including: silicon, silicon carbide, silicon germanium, a multicomponent semiconductor material of group iii-v elements including InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP, silicon-on-insulator (SOI), or germanium-on-insulator (GOI).
In the present embodiment, the semiconductor layer 114 has doped ions therein, and the conductivity type of the doped ions includes N type or P type.
In this embodiment, the doping ions with the N-type conductivity include phosphorus ions, arsenic ions, or antimony ions; the doped ions with the conductive type of P type comprise boron ions, boron-fluorine ions or indium ions.
In this embodiment, the substrate 100 further includes: a scribe line region located between adjacent device regions I, the scribe line region including a first scribe line II parallel to the first direction X and a second scribe line III parallel to the second direction Y; the semiconductor layer 114 is located on the second scribe line III, and the source layer 113 is located on the second scribe line III.
In this embodiment, the gate structure includes a first subsection 116 and a second subsection 117 connected to each other, the first subsection 116 is located on the first scribe line II, the extending direction of the first subsection 116 is parallel to the first direction X, and the second subsection 117 is located on the semiconductor layer 114 on the second scribe line III.
In this embodiment, the method further includes: an insulating layer 115 between the semiconductor layer 114 and the second section 117.
In this embodiment, the material of the insulating layer 115 includes: silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and combinations of one or more of silicon oxycarbonitride.
In this embodiment, the material of the source layer 113 includes metal or metal nitride; the metal includes: combinations of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.
In this embodiment, the material of the gate structure includes a metal or a metal nitride; the metal includes: combinations of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.
In the present embodiment, the material of the drain layer 112 includes metal or metal nitride; the metal includes: combinations of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.
In this embodiment, the substrate 100 includes a first side and a second side opposite to each other, and the device structure is located on the first side surface of the device region I.
In this embodiment, the device structure includes: the first reflector structure is positioned on the surface of the first surface of the device area I; an active layer 103 on the first mirror structure; at least two overlapped second mirror structures on the active layer 103, the second mirror structures having a conductivity type opposite to that of the first mirror structures; a plurality of light blocking layers 108 and light emitting layers 109 positioned between two adjacent layers of the second mirror structures, wherein the plurality of light emitting layers 109 are separated from each other, and the light blocking layers 108 are positioned between the light emitting layers 109; the drain layer 112 is located on the second mirror structure.
In this embodiment, the test structure further includes: and the electrode layer is positioned on the second surface of the device area I.
In this embodiment, the material of the electrode layer includes a metal or a metal nitride; the metal includes: combinations of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.
In this embodiment, the first mirror structure includes a plurality of first stacked structures, the first stacked structures include a first reflective layer 101 and a second reflective layer 102 on the first reflective layer 101, and refractive indices of the first reflective layer 101 and the second reflective layer 102 are different.
In this embodiment, the material of the first reflective layer 101 includes aluminum gallium arsenide, and the material of the second reflective layer 102 includes gallium arsenide.
In this embodiment, the second mirror structure includes several second stacked structures, the second stacked structures include a third reflective layer 104 and a fourth reflective layer 105 on the third reflective layer 104, and refractive indices of the third reflective layer 104 and the fourth reflective layer 105 are different.
In this embodiment, the material of the third reflective layer 104 includes aluminum gallium arsenide, and the material of the fourth reflective layer 105 includes gallium arsenide.
In this embodiment, the method further includes: the first shift register is electrically connected with the plurality of grid structures; and a second shift register electrically connected to the plurality of source layers 113.
FIG. 8 is a flow chart of a method of operation of a test structure in an embodiment of the invention.
The working method of the test structure comprises the following steps:
step S10: providing the test structure formed as shown in fig. 1 to 7;
step S20: sequentially loading first voltages to the plurality of grid structures through the first shift register;
step S30: sequentially loading a second voltage on a plurality of source electrode layers on a second cutting path through the second shift register;
step S40: applying a third voltage to the electrode layer;
step S50: collecting an optical signal of the device structure.
Next, each step will be described.
With continued reference to fig. 8, step S10 is executed: a test structure as described in fig. 1 to 7 is provided.
The formation process of the test structure is as described in fig. 1 to 7, and is not described herein again.
With continued reference to fig. 8, step S20 is executed: and sequentially loading a first voltage to the plurality of grid structures through the first shift register.
The first shift register controls energization of any of the gate structures.
With continued reference to fig. 8, step S30 is executed: and sequentially loading a second voltage to the source layers 113 on the second scribe line III through a second shift register.
With continued reference to fig. 8, step S40 is executed: applying a third voltage to the electrode layer.
The first voltage is a positive voltage, the second voltage is a positive voltage, and the third voltage is a negative voltage.
When a first voltage is applied to any of the gate structures, the semiconductor layer 114 becomes a conductor under the action of the first voltage, so that charges generated by a second voltage applied to the source layer 113 can be transferred to the drain layer 112 through the semiconductor layer 114, i.e., the anode of the device structure is energized. And loading a third voltage on the electrode layer, wherein the electrode layer is a cathode of the device structure, thereby completing the process of electrifying any device structure.
Continuing to refer to fig. 8, step S50 is executed: collecting an optical signal of the device structure.
And collecting the optical signal of the device structure by using a detector.
With continued reference to fig. 8, step S60 is executed: and judging whether the device structure passes the performance according to the optical signal.
The method for judging whether the device structure passes the performance according to the optical signal comprises the following steps: acquiring a current signal or a voltage signal according to the optical signal; judging whether the current signal or the voltage signal reaches a preset value, and if the current signal or the voltage signal reaches the preset value, judging that the structural performance of the device passes; and if the current signal or the voltage signal does not reach a preset value, judging that the structural performance of the device does not pass through.
And loading a first voltage to any one of the gate structures, sequentially loading a second voltage to the source electrode layers 113 on the second cutting channel III, and then loading a third voltage to the electrode layers, so that the electrifying process of the device structure can be sequentially completed. By adding the semiconductor layer 114, the gate structures and the source layer 113 corresponding to the device regions I are controlled to be electrified, and thus the device structures in any device region I can be electrified independently, so that the loading voltage of each device structure can be controlled in a time-sharing manner, a plurality of device structures can be automatically tested at one time, and the testing efficiency can be improved.
FIG. 9 is a circuit diagram of a test structure in an embodiment of the invention.
Referring to fig. 9, the circuit of the test structure includes:
a plurality of device structures distributed in an array;
a plurality of drains D, each of the drains D coupled to one of the device structures;
a plurality of rows of source electrodes SL, each of the source electrodes SL corresponding to one of the rows of device structures;
a plurality of semiconductor switches T, each of which is coupled to any one of the drains D and the corresponding source SL;
and the grid structures WL in a plurality of rows are respectively coupled with the semiconductor switch T in one row.
In this embodiment, the method further includes: a first shift register P1 coupled to a number of the gate structures WL; a second shift register P2 coupled to a number of the sources SL.
The circuit of the test structure is powered on the first row gate structure WL1 at time T1 through the first shift register P1, all the semiconductor switches T1 in the first row are turned off, the semiconductor switches T in other rows are kept in an on state, then voltage signals are provided to the first column source SL1, the second column source SL2 and the nth column through the second shift register P2 in a time sharing mode, and light signals are collected through a detector above the device structure.
The device structures form an M x N array arrangement, a 4 x 3 array being schematically shown in this embodiment.
The array has a total of N columns, the testing time of each device structure is preset to be T seconds, then the power-on time of the first row gate structure WL1 is N x T seconds, the power-on time of the first column source SL1 is 0-T seconds, the power-on time of the second column source SL2 is T-2T seconds … …, and the power-on time of the Nth column is (N-1) T-NT seconds. And finishing the testing of the device structure in the first row.
After the testing of the device structures in the first row is completed, the second row of gate structures WL2 is powered on at time T2 under the control of the first shift register P1, the second row of semiconductor switches T2 is turned off, and all the other rows are turned on. Then, voltage signals are provided to the first column source electrode SL1, the second column source electrode SL2 and the Nth column through the second shift register P2, and corresponding light signals are collected through a detector above the device structure.
And the rest can be done until the test of all the products is finished.
By adding the semiconductor switch T, the grid electrode structures and the source electrodes corresponding to the device structures are controlled to be electrified, so that any device structure can be independently electrified, the loading voltage of each device structure can be controlled in a time-sharing mode, a plurality of device structures can be automatically tested at one time, and the testing efficiency can be improved.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected by one skilled in the art without departing from the spirit and scope of the invention, as defined in the appended claims.
Claims (46)
1. A test structure, comprising:
the device comprises a substrate, a plurality of first-level transistors and a plurality of second-level transistors, wherein the substrate comprises a plurality of device areas distributed in an array along a first direction and a second direction, and the first direction is different from the second direction;
the device structure is respectively positioned on the surface of each device area;
a plurality of drain layers, each of the drain layers being electrically connected to one of the device structures;
a plurality of source layers parallel to the second direction, each of the source layers corresponding to a row of the device structures arranged along the second direction;
the semiconductor layers are respectively positioned between any drain electrode layer and the corresponding source electrode layer and are respectively connected with any drain electrode layer and the corresponding source electrode layer;
a plurality of grid structures parallel to the first direction, wherein each grid structure is respectively positioned on the surface of a row of the semiconductor layers arranged along the first direction,
the semiconductor layer is conducted and electrically connected with the drain layer and the corresponding source layer under the action of voltage loaded on the grid structure.
2. The test structure of claim 1, wherein the material of the semiconductor layer comprises a semiconductor material comprising: silicon, silicon carbide, silicon germanium, a multicomponent semiconductor material of group iii-v elements including InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP, silicon-on-insulator (SOI), or germanium-on-insulator (GOI).
3. The test structure of claim 2, wherein the semiconductor layer has dopant ions therein, the dopant ions having a conductivity type comprising N-type or P-type.
4. The test structure of claim 3, wherein the dopant ions of conductivity type N comprise phosphorus ions, arsenic ions, or antimony ions; the doped ions with the conductive type of P type comprise boron ions, boron-fluorine ions or indium ions.
5. The test structure of claim 1, wherein the substrate further comprises: a scribe line region between adjacent device regions, the scribe line region including a first scribe line parallel to the first direction and a second scribe line parallel to the second direction; the semiconductor layer is located on the second cutting path, and the source electrode layer is located on the second cutting path.
6. The test structure of claim 5, wherein the gate structure comprises a first subsection and a second subsection connected, the first subsection being located on the first scribe line, an extending direction of the first subsection being parallel to the first direction, the second subsection being located on the semiconductor layer on the second scribe line.
7. The test structure of claim 6, further comprising: an insulating layer between the semiconductor layer and the second section.
8. The test structure of claim 7, wherein a material of the insulating layer comprises: silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and combinations of one or more of silicon oxycarbonitride.
9. The test structure of claim 1, wherein a material of the source layer comprises a metal or a metal nitride; the metal includes: combinations of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.
10. The test structure of claim 1, wherein a material of the gate structure comprises a metal or a metal nitride; the metal includes: combinations of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.
11. The test structure of claim 1, wherein a material of the drain layer comprises a metal or a metal nitride; the metal includes: combinations of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.
12. The test structure of claim 1, wherein the substrate includes opposing first and second sides, the device structure being located at the device region first side surface.
13. The test structure of claim 12, wherein the device structure comprises: a first mirror structure located on a first surface of the device region; an active layer on the first mirror structure; at least two overlapping second mirror structures on the active layer, the second mirror structures having a conductivity type opposite to the conductivity type of the first mirror structures; the light blocking layers and the light emitting layers are positioned between two adjacent second reflecting mirror structures, the light emitting layers are mutually separated, and the light blocking layers are positioned between the light emitting layers; the drain layer is located on the second mirror structure.
14. The test structure of claim 13, wherein the test structure further comprises: and the electrode layer is positioned on the second surface of the device area.
15. The test structure of claim 14, wherein a material of the electrode layer comprises a metal or a metal nitride; the metal includes: combinations of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.
16. The test structure of claim 13, wherein the first mirror structure comprises a number of first stacked structures, the first stacked structures comprising a first reflective layer and a second reflective layer on the first reflective layer, the first reflective layer having a different index of refraction than the second reflective layer.
17. The test structure of claim 16, wherein the material of the first reflective layer comprises aluminum gallium arsenide and the material of the second reflective layer comprises gallium arsenide.
18. The test structure of claim 13, wherein the second mirror structure comprises a plurality of second stacked structures, the second stacked structures comprising a third reflective layer and a fourth reflective layer on the third reflective layer, the third reflective layer and the fourth reflective layer having different refractive indices.
19. The test structure of claim 18, wherein the material of the third reflective layer comprises aluminum gallium arsenide and the material of the fourth reflective layer comprises gallium arsenide.
20. The test structure of claim 1, further comprising: the first shift register is electrically connected with the plurality of grid structures; and a second shift register electrically connected to the source layers.
21. A method of forming a test structure, comprising:
providing a substrate, wherein the substrate comprises a plurality of device areas distributed in an array along a first direction and a second direction, and the first direction is different from the second direction;
forming a plurality of device structures on the surface of each device area;
forming a plurality of drain layers on the device structures, wherein each drain layer is electrically connected with one device structure;
forming a plurality of source layers on the substrate parallel to the second direction, each source layer corresponding to a row of the device structures arranged along the second direction;
forming a plurality of semiconductor layers on the substrate, wherein each semiconductor layer is respectively positioned between any drain layer and the corresponding source layer;
forming a plurality of grid structures parallel to the first direction on the substrate, wherein each grid structure is respectively positioned on the surface of a row of the semiconductor layers arranged along the first direction,
the semiconductor layer is conducted and electrically connected with the drain layer and the corresponding source layer under the action of voltage loaded on the grid structure.
22. The method of forming a test structure of claim 21, wherein the material of the semiconductor layer comprises a semiconductor material comprising: silicon, silicon carbide, silicon germanium, a multicomponent semiconductor material of group iii-v elements including InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP, silicon-on-insulator (SOI), or germanium-on-insulator (GOI).
23. The method of forming a test structure of claim 22, wherein the process of forming the semiconductor layer comprises: an epitaxial growth process or a deposition process.
24. The method of claim 22, wherein the semiconductor layer has dopant ions therein, the conductivity type of the dopant ions including N-type or P-type; the doped ions with the N-type conductivity comprise phosphorus ions, arsenic ions or antimony ions; the doped ions with the conductive type of P type comprise boron ions, boron-fluorine ions or indium ions.
25. The method of forming a test structure of claim 21, wherein the substrate further comprises: a scribe line region between adjacent device regions, the scribe line region including a first scribe line parallel to the first direction and a second scribe line parallel to the second direction; the semiconductor layer is located on the second cutting path, and the source electrode layer is located on the second cutting path.
26. The method of claim 25, wherein the gate structure comprises a first subsection and a second subsection connected to each other, the first subsection is located on the first scribe line, the first subsection extends in a direction parallel to the first direction, and the second subsection is located on the semiconductor layer on the second scribe line.
27. The method of forming a test structure of claim 26, wherein prior to forming a plurality of gate structures on the scribe line region, further comprising: an insulating layer is formed between the semiconductor layer and the second section.
28. The method of forming a test structure of claim 27, wherein the material of the insulating layer comprises one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon oxycarbonitride.
29. The method of forming a test structure of claim 21, wherein the material of the source layer comprises a metal or a metal nitride; the metal includes: combinations of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.
30. The method of forming a test structure of claim 21, wherein the material of the gate structure comprises a metal or a metal nitride; the metal includes: a combination of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.
31. The method of forming a test structure of claim 21, wherein the material of the drain layer comprises a metal or a metal nitride; the metal includes: combinations of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.
32. The method of forming a test structure of claim 21, wherein the substrate includes opposing first and second sides, the device structure being located at the device region first side surface.
33. The method of forming a test structure of claim 32, wherein the device structure comprises: a first mirror structure located on a first surface of the device region; an active layer on the first mirror structure; at least two overlapping second mirror structures on the active layer, the second mirror structures having a conductivity type opposite to that of the first mirror structures; the light blocking layers and the light emitting layers are positioned between two adjacent second reflecting mirror structures, the light emitting layers are mutually separated, and the light blocking layers are positioned between the light emitting layers; the drain layer is located on the second mirror structure.
34. The method of forming a test structure of claim 33, further comprising: and forming an electrode layer on the second surface of the substrate device area.
35. The method of forming a test structure of claim 34, wherein the material of the electrode layer comprises a metal or a metal nitride; the metal includes: combinations of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.
36. The method of forming a test structure of claim 33, wherein the first mirror structure comprises a plurality of first stacked structures, the first stacked structures comprising a first reflective layer and a second reflective layer on the first reflective layer, the first reflective layer having a different index of refraction than the second reflective layer.
37. The method of forming a test structure of claim 36, wherein the material of the first reflective layer comprises aluminum gallium arsenide and the material of the second reflective layer comprises gallium arsenide.
38. The method of claim 33, wherein the second mirror structure comprises a plurality of second stacked structures, the second stacked structures comprising a third reflective layer and a fourth reflective layer on the third reflective layer, the third reflective layer and the fourth reflective layer having different refractive indices.
39. The method of forming a test structure of claim 38, wherein the material of the third reflective layer comprises aluminum gallium arsenide and the material of the fourth reflective layer comprises gallium arsenide.
40. The method of forming a test structure of claim 21, further comprising: the first shift register is electrically connected with the plurality of grid structures; and the second shift register is electrically connected with a plurality of source electrode layers.
41. A method of operating a test structure, comprising:
providing a test structure according to any one of claims 1 to 20;
a first voltage is sequentially loaded on the plurality of grid electrode structures through the first shift register, and the semiconductor layer is conducted under the action of the first voltage and is electrically connected with the source electrode layer and the corresponding drain electrode layer;
sequentially loading a second voltage on the source electrode layers on the second cutting channel through a second shift register;
applying a third voltage to the electrode layer;
collecting an optical signal of the device structure.
42. The method of operating a test structure of claim 41, further comprising: and judging whether the device structure passes the performance according to the optical signal.
43. The method of claim 42, wherein determining whether the device structure is performing based on the optical signal comprises: acquiring a current signal or a voltage signal according to the optical signal; and judging whether the current signal or the voltage signal reaches a preset value, and if the current signal or the voltage signal reaches the preset value, judging that the structural performance of the device passes.
44. The method of claim 43, wherein the first voltage is a positive voltage, the second voltage is a positive voltage, and the third voltage is a negative voltage.
45. A circuit for testing a structure, comprising:
a plurality of device structures distributed in an array;
a plurality of drains, each of the drains being coupled to one of the device structures;
a plurality of rows of source electrodes, each of the source electrodes corresponding to a row of the device structures;
a plurality of semiconductor switches, each of the semiconductor switches being coupled to any one of the drains and the corresponding source, respectively;
a plurality of rows of gate structures, each of the gate structures being coupled to a respective one of the rows of semiconductor switches,
the semiconductor switch is conducted under the action of voltage loaded on the grid structure and is electrically connected with the drain electrode and the corresponding source electrode.
46. The circuit of test structure of claim 45, further comprising: a first shift register coupled to a number of the gate structures; a second shift register coupled to a number of the sources.
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