CN114222079A - Pixel charge transfer efficiency test structure and time sequence - Google Patents
Pixel charge transfer efficiency test structure and time sequence Download PDFInfo
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- CN114222079A CN114222079A CN202111534022.2A CN202111534022A CN114222079A CN 114222079 A CN114222079 A CN 114222079A CN 202111534022 A CN202111534022 A CN 202111534022A CN 114222079 A CN114222079 A CN 114222079A
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- 238000012546 transfer Methods 0.000 title claims abstract description 72
- 238000012360 testing method Methods 0.000 title claims abstract description 22
- 230000005540 biological transmission Effects 0.000 claims abstract description 40
- 238000003860 storage Methods 0.000 claims abstract description 9
- 238000009792 diffusion process Methods 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 101100041125 Arabidopsis thaliana RST1 gene Proteins 0.000 claims description 7
- 101100443250 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) DIG1 gene Proteins 0.000 claims description 7
- 101100422768 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) SUL2 gene Proteins 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 101100191136 Arabidopsis thaliana PCMP-A2 gene Proteins 0.000 claims description 3
- 101100443251 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) DIG2 gene Proteins 0.000 claims description 3
- 101100048260 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) UBX2 gene Proteins 0.000 claims description 3
- 101100041128 Schizosaccharomyces pombe (strain 972 / ATCC 24843) rst2 gene Proteins 0.000 claims description 3
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- 238000005468 ion implantation Methods 0.000 claims description 2
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/50—Control of the SSIS exposure
- H04N25/57—Control of the dynamic range
- H04N25/59—Control of the dynamic range by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
- H01L27/1461—Pixel-elements with integrated switching, control, storage or amplification elements characterised by the photosensitive area
Abstract
The invention discloses a pixel charge transfer efficiency test structure.A pixel is formed by injecting N-type ions into a PPD101 photosensitive area on the basis of a p-type substrate 100, and p + doping 104 for reducing dark current noise is positioned on the surface of PPD; the N-type doped floating diffusion node FD105 and the storage node SD103 are respectively located in one P well 102. The grid of the first transmission grid 107 is connected with a TG1 signal, the source is PPD, and the drain is an FD node; the grid electrode of the second transmission grid 108 is connected with a TG2 signal, and the source electrode is PPD; the second transfer gate 108 is stacked over the third transfer gate 109. The second transfer gate 108 overlaps the PPD101 more than the first transfer gate 107 overlaps the PPD101, and the third transfer gate 109 overlaps the SD node 103 more than the first transfer gate 107 overlaps the FD node 105. By additionally introducing a structure more conducive to transmission in the test pixel, the design of the added stacked gate and storage node structure does not need to be too limited by the conversion gain for transferring trailing electrons, so as to more objectively and accurately evaluate the charge transfer efficiency of the pixel.
Description
Technical Field
The present invention relates to image sensors, and more particularly to a pixel charge transfer efficiency test structure and timing sequence.
Background
The charge transfer efficiency is an important index for reflecting the performance of the image sensor, and when the charge transfer efficiency is low, the image trailing phenomenon can be generated by the sensor, and the imaging quality is seriously influenced. The reasons for the low charge transfer efficiency of the image sensor generally include the existence of a potential barrier on the charge transfer path (as shown in fig. 1(a)), and the backflow of the charge under the channel to the clamped photodiode (PPD) when the Transfer Gate (TG) is turned off (as shown in fig. 1 (b)).
Evaluating the charge transfer efficiency of a pixel is of great importance to guide image sensor design. Common methods for testing the charge transfer efficiency are "multiple readout method" and "equivalent exposure method". The "multiple readout method" refers to repeating the process of resetting a floating diffusion node (FD) and turning on a transfer gate multiple times after a normal readout timing, and sampling signals each time and accumulating the signals to obtain an electronic tailing amount. However, in this method, if a relatively serious potential barrier exists under the channel of the pixel due to design, trailing electrons still exist even if PPD is read out for many times, and the transfer efficiency cannot be accurately evaluated; the "equal exposure method" means that the pixel is read out with a normal timing for the first exposure, then the PPD is not reset, the second exposure is performed with an exposure amount equal to the first exposure, and the number of trailing electrons is obtained by subtracting the signal read out for the second time from the signal read out for the first time. In this test method, if the sensor has trailing electrons, the charge in the PPD after the second exposure is high, and the charge transfer efficiency is related to the number of electrons accumulated in the PPD, which results in the second readout transfer efficiency being lower than the first readout transfer efficiency, thereby causing the calculated number of trailing electrons to be low. Furthermore, both methods do not allow for efficient evaluation of charge backflow.
In view of the above, the present invention is particularly proposed.
Disclosure of Invention
The invention aims to provide a pixel charge transfer efficiency test structure and a time sequence, which aim to solve the technical problems in the prior art, and objectively and accurately evaluate the pixel charge transfer efficiency by introducing an additional storage node (SD) and a transistor and matching with a designed read-out sampling time sequence.
The purpose of the invention is realized by the following technical scheme:
according to the pixel charge transfer efficiency test structure, on the basis of a p-type substrate 100, a PPD101 photosensitive area is formed by injecting N-type ions, and p + doping 104 for reducing dark current noise is located on the surface of PPD;
the N-type doped floating diffusion node FD105 and the storage node SD103 are respectively located in one P well 102, and the two P wells 102 are disposed at both sides of the PPD 101.
The driving sequence of the pixel charge transfer efficiency testing structure comprises three stages of resetting, exposing and reading:
in the reset stage, the TG1 is raised to 2.8V, the RST1 is placed at 2.8V, the TG2 and the TG3 are turned off at-1.5V, and the rest of tubes are turned off at 0V, so that the FD node and the PPD region are reset;
after the exposure phase begins, the first gate tube is opened, and a reset signal Vrst1 is sampled after the first reset tube is turned off;
and (3) a reading stage:
the first transmission grid is conducted, a PPD internal signal is transferred into an FD node, and a photoelectron signal Vsig1 is sampled;
after the first transmission gate is turned off, the second gate tube is turned on, the second reset tube is turned on to reset the FD and SD nodes, and after the second reset tube is turned off, a reset signal Vrst2 is sampled;
in the next stage, the second transmission gate is started at 2.5V, then the third transmission gate is started at 2.8V, residual charges in PPD are transferred to a node formed by SD and FD, and the second transmission gate is turned off before the third transmission gate;
the photo-electronic signal Vsig2 is sampled after both transfer gates are turned off.
Compared with the prior art, the pixel charge transfer efficiency test structure and the time sequence provided by the invention can be used for objectively and accurately evaluating the pixel charge transfer efficiency by matching the improved pixel structure with the driving time sequence.
Drawings
FIG. 1 is a schematic diagram of a transfer channel barrier and charge return;
FIG. 2 is a schematic diagram of a pixel device structure according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a driving timing sequence according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of charge transfer at different times in accordance with an embodiment of the present invention;
in the figure:
100: p-type substrate
101：PPD
102: p well
103: SD node
104: p + doping
105: FD node
106: oxide layer
107: a first transfer gate
108: second transfer gate
109: third transfer gate
110: first reset transistor
111: second reset transistor
112: first gate tube
113: source follower
114: second gate tube
Detailed Description
The technical scheme in the embodiment of the invention is clearly and completely described below by combining the attached drawings in the embodiment of the invention; it is to be understood that the described embodiments are merely exemplary of the invention, and are not intended to limit the invention to the particular forms disclosed. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
The terms that may be used herein are first described as follows:
the term "and/or" means that either or both can be achieved, for example, X and/or Y means that both cases include "X" or "Y" as well as three cases including "X and Y".
The terms "comprising," "including," "containing," "having," or other similar terms of meaning should be construed as non-exclusive inclusions. For example: including a feature (e.g., material, component, ingredient, carrier, formulation, material, dimension, part, component, mechanism, device, process, procedure, method, reaction condition, processing condition, parameter, algorithm, signal, data, product, or article of manufacture), is to be construed as including not only the particular feature explicitly listed but also other features not explicitly listed as such which are known in the art.
The term "consisting of … …" is meant to exclude any technical feature elements not explicitly listed. If used in a claim, the term shall render the claim closed except for the inclusion of the technical features that are expressly listed except for the conventional impurities associated therewith. If the term occurs in only one clause of the claims, it is defined only to the elements explicitly recited in that clause, and elements recited in other clauses are not excluded from the overall claims.
Unless expressly stated or limited otherwise, the terms "mounted," "connected," and "secured," etc., are to be construed broadly, as for example: can be fixedly connected, can also be detachably connected or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms herein can be understood by those of ordinary skill in the art as appropriate.
The terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in an orientation or positional relationship that is indicated based on the orientation or positional relationship shown in the drawings for ease of description and simplicity of description only, and are not intended to imply or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting herein.
Details which are not described in detail in the embodiments of the invention belong to the prior art which is known to the person skilled in the art. Those not specifically mentioned in the examples of the present invention were carried out according to the conventional conditions in the art or conditions suggested by the manufacturer. The reagents or instruments used in the examples of the present invention are not specified by manufacturers, and are all conventional products available by commercial purchase.
According to the pixel charge transfer efficiency test structure, on the basis of a p-type substrate 100, a PPD101 photosensitive area is formed by injecting N-type ions, and p + doping 104 for reducing dark current noise is located on the surface of PPD;
the N-type doped floating diffusion node FD105 and the storage node SD103 are respectively located in one P well 102, and the two P wells 102 are disposed at both sides of the PPD 101.
The grid of the first transmission grid 107 is connected with a TG1 signal, the source is PPD, and the drain is an FD node;
the grid electrode of the second transmission grid 108 is connected with a TG2 signal, and the source electrode is PPD;
the second transfer gate 108 is stacked over the third transfer gate 109, with the polysilicon structures of the two gates separated by the oxide layer 106.
The gate of the first reset transistor 110 is connected with the RST1 signal, the source is connected with the FD node, the gate of the source follower 113 and the drain of the second gate tube 114, and the drain is connected with the VDD signal;
the second reset transistor 111 has a gate connected to the RST2 signal, a source connected to the SD node and the source of the second gate transistor 114, and a drain connected to the VDD signal.
The gate of the second gate tube 114 is connected with SEL2 signal;
the source of the source follower 113 is connected with the source of the first gate tube 112, and the drain is connected with the VDD signal;
the first gate line 112 has its gate connected to the SEL1 signal and its drain connected to the column sense bus.
The second transfer gate 108 overlaps the PPD101 more than the first transfer gate 107 overlaps the PPD101, and the third transfer gate 109 overlaps the SD node 103 more than the first transfer gate 107 overlaps the FD node 105.
The driving sequence of the pixel charge transfer efficiency testing structure comprises three stages of resetting, exposing and reading:
in the reset stage, the TG1 is raised to 2.8V, the RST1 is placed at 2.8V, the TG2 and the TG3 are turned off at-1.5V, and the rest of tubes are turned off at 0V, so that the FD node and the PPD region are reset;
after the exposure phase begins, the first gate tube is opened, and a reset signal Vrst1 is sampled after the first reset tube is turned off;
and (3) a reading stage:
the first transmission grid is conducted, a PPD internal signal is transferred into an FD node, and a photoelectron signal Vsig1 is sampled;
after the first transmission gate is turned off, the second gate tube is turned on, the second reset tube is turned on to reset the FD and SD nodes, and after the second reset tube is turned off, a reset signal Vrst2 is sampled;
in the next stage, the second transmission gate is started at 2.5V, then the third transmission gate is started at 2.8V, residual charges in PPD are transferred to a node formed by SD and FD, and the second transmission gate is turned off before the third transmission gate;
the photo-electronic signal Vsig2 is sampled after both transfer gates are turned off.
In summary, the pixel charge transfer efficiency test structure and timing sequence of the embodiments of the invention, by additionally introducing a structure beneficial to transmission into the test pixel, the design of the added stacked gate and storage node structure does not need to be too limited by the conversion gain for transferring the trailing electrons, so as to more objectively and accurately evaluate the charge transfer efficiency of the pixel. In the additionally introduced structure, on one hand, the overlapping length of the stacked polysilicon gate and the N-type region is increased, so that the potential barrier of the overlapping region is eliminated, the equivalent channel length is reduced, and the electron transmission is facilitated; in a second aspect, stacked transfer gates TG2, TG3 optimize electron transfer channels by applying different voltages, different pulse times.
In order to more clearly show the technical solutions and the technical effects provided by the present invention, the following detailed description is provided for the embodiments of the present invention with specific embodiments.
Example 1
The structure of the pixel device of the invention is shown in figure 2:
the pixel is on the basis of a p-type substrate 100, and a PPD101 photosensitive area is formed by N-type ion implantation; p + doping 104 for reducing dark current noise is located on the PPPD surface; the N-type doped floating diffusion node FD105 and the storage node SD103 are located in the P-well 102; the grid of the first transmission grid 107 is connected with a TG1 signal, the source is PPD, and the drain is an FD node; the grid electrode of the second transmission grid 108 is connected with a TG2 signal, and the source electrode is PPD; the second transfer gate is stacked above the third transfer gate 109, and the polysilicon structures of the two gates are separated by the oxide layer 106; the gate of the first reset transistor 110 is connected to the RST1 signal, the source is connected to the FD node, the gate of the source follower SF113 and the drain of the second gate tube 114, and the drain is connected to the VDD signal; the grid of the second reset transistor 111 is connected with a RST2 signal, the source is connected with the SD node and the source of the second gate tube, and the drain is connected with a VDD signal; the grid of the second gating tube is connected with a SEL2 signal; the source electrode of the source follower is connected with the source electrode of the first gate tube 112, and the drain electrode is connected with a VDD signal; the first gate is connected to the SEL1 signal at its gate and to the column readout bus at its drain. Compared with the relative position relationship between the PPD and the FD node, in the manufacturing process, the overlapping degree of the second transmission gate and the PPD is required to be larger than that of the first transmission gate and the PPD, and the overlapping degree of the third transmission gate and the SD node is larger than that of the first transmission gate and the FD node.
The pixel driving timing of the present invention is shown in fig. 3, and is divided into three stages of reset, exposure and readout: in the reset stage, the TG1 is raised to 2.8V, the RST1 is placed at 2.8V, the TG2 and the TG3 are turned off at-1.5V, and the rest of tubes are turned off at 0V, so that the FD node and the PPD region are reset; after the exposure phase begins, the first gate tube is opened, and a reset signal Vrst1 is sampled after the first reset tube is turned off; in the readout phase, the first transfer gate is turned on, transferring the PPD internal signal to the FD node, and sampling the photo electronic signal Vsig 1. After the first transmission gate is turned off, the second gate tube is turned on, the second reset tube is turned on to reset the FD and SD nodes, and after the second reset tube is turned off, the reset signal Vrst2 is sampled. In the next stage, the second transmission gate is started at 2.5V, then the third transmission gate is started at 2.8V, residual charges in PPD are transferred to a node formed by SD and FD, and the second transmission gate is turned off before the third transmission gate; the photo-electronic signal Vsig2 is sampled after both transfer gates are turned off.
In the pixel design, the balance between the transfer characteristic and the Conversion Gain (CG) and the full-well capacity performance needs to be considered, so that the optimization design of the transfer gate and the FD node for the transfer efficiency is limited, and the accuracy of the conventional trailing electron test method is limited by the device structure and the exposure condition.
The invention additionally introduces a structure beneficial to transmission in the test pixel, and the design of the added stacked gate and storage node structure is not required to be excessively restricted by the limitation of conversion gain for transferring trailing electrons, so that the charge transfer efficiency of the pixel can be objectively and accurately evaluated. In the additionally introduced structure, on one hand, the overlapping length of the stacked polysilicon gate and the N-type region is increased, so that the potential barrier of the overlapping region is eliminated, the equivalent channel length is reduced, and the electron transmission is facilitated; in a second aspect, stacked transfer gates TG2, TG3 optimize electron transfer channels by applying different voltages, different pulse times.
As shown in fig. 4, it can be seen from the combination of the gate timing, that at time (r), the different turn-on voltages of TG2 and TG3 form a step-like potential in the channel, which is beneficial to electron transfer. At the moment (iii), the TG2 and the TG3 are successively turned off, so that a channel close to the PPD region can be turned off firstly, and the backflow effect of electrons in the channel to the PPD region in the gate turn-off process is inhibited; in the third aspect, during the process that the trailing electrons in PPD are read by TG2 and TG3, SEL2 is in an on state, and the electrons are transferred to a node where SD and FD are connected in parallel, and the node has larger capacitance, so that the trailing electrons have larger driving capability and are beneficial to charge transfer.
Finally, the sampled signal is processed as follows to obtain the final charge transfer efficiency:
the CG1 is conversion gain under the SEL2 off state, the CG2 is conversion gain under the SEL2 on state, and the value can be obtained through a photon transfer curve test.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims. The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.
Claims (6)
1. A pixel charge transfer efficiency test structure is characterized in that a pixel forms a PPD (101) photosensitive area by N-type ion implantation on the basis of a p-type substrate (100), and p + doping (104) for reducing dark current noise is positioned on the surface of the PPD;
the N-type doped floating diffusion node FD (105) and the storage node SD (103) are respectively positioned in one P well (102), and the two P wells (102) are respectively arranged on two sides of the PPD (101).
2. The pixel charge transfer efficiency test structure of claim 1, wherein:
the grid of the first transmission grid (107) is connected with a TG1 signal, the source electrode is PPD, and the drain electrode is an FD node;
the grid of the second transmission grid (108) is connected with a TG2 signal, and the source is PPD;
the second transfer gate (108) is stacked over the third transfer gate (109), with the polysilicon structures of the two gates separated by an oxide layer (106).
3. The pixel charge transfer efficiency test structure of claim 2, wherein:
the grid of the first reset transistor (110) is connected with a RST1 signal, the source is connected with an FD node, the grid of the source follower (113) and the drain of the second gate tube (114), and the drain is connected with a VDD signal;
the gate of the second reset transistor (111) is connected with the RST2 signal, the source is connected with the SD node and the source of the second gate tube (114), and the drain is connected with the VDD signal.
4. The pixel charge transfer efficiency test structure of claim 3, wherein:
the grid of the second gate tube (114) is connected with a SEL2 signal;
the source electrode of the source electrode follower (113) is connected with the source electrode of the first gate tube (112), and the drain electrode is connected with a VDD signal;
the first gate line (112) has its gate connected to the SEL1 signal and its drain connected to the column sense bus.
5. The pixel charge transfer efficiency test structure according to claim 4, wherein the overlap of the second transfer gate (108) with the PPD (101) is greater than the overlap of the first transfer gate (107) with the PPD (101), and the overlap of the third transfer gate (109) with the SD node (103) is greater than the overlap of the first transfer gate (107) with the FD node (105).
6. A driving timing sequence of the pixel charge transfer efficiency test structure according to any one of claims 1 to 5, comprising three phases of reset, exposure and readout:
in the reset stage, the TG1 is raised to 2.8V, the RST1 is placed at 2.8V, the TG2 and the TG3 are turned off at-1.5V, and the rest of tubes are turned off at 0V, so that the FD node and the PPD region are reset;
after the exposure phase begins, the first gate tube is opened, and a reset signal Vrst1 is sampled after the first reset tube is turned off;
and (3) a reading stage:
the first transmission grid is conducted, a PPD internal signal is transferred into an FD node, and a photoelectron signal Vsig1 is sampled;
after the first transmission gate is turned off, the second gate tube is turned on, the second reset tube is turned on to reset the FD and SD nodes, and after the second reset tube is turned off, a reset signal Vrst2 is sampled;
in the next stage, the second transmission gate is started at 2.5V, then the third transmission gate is started at 2.8V, residual charges in PPD are transferred to a node formed by SD and FD, and the second transmission gate is turned off before the third transmission gate;
the photo-electronic signal Vsig2 is sampled after both transfer gates are turned off.
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