CN114221658A

CN114221658A - Broadband high-speed tracking and holding circuit

Info

Publication number: CN114221658A
Application number: CN202111544031.XA
Authority: CN
Inventors: 孙伟; 王永禄; 张磊; 徐鸣远; 朱璨; 刘佳
Original assignee: Chongqing Jixin Technology Co ltd; CETC 24 Research Institute
Current assignee: Chongqing Jixin Technology Co ltd; CETC 24 Research Institute
Priority date: 2021-12-16
Filing date: 2021-12-16
Publication date: 2022-03-22
Anticipated expiration: 2041-12-16
Also published as: CN114221658B

Abstract

The invention provides a broadband high-speed tracking and holding circuit, which comprises an input buffer, a tracking and holding switch module, an output buffer and a clock module, wherein the input buffer is designed based on an additional cascade amplification unit and a feedforward auxiliary amplification unit, so that the nonlinearity of the third harmonic distortion of a common-emitter circuit which increases exponentially along with the frequency increase is reduced, and the linearity is improved; the tracking and holding switch module is designed based on the following sampling unit, the clock switch unit and the clamping unit, when the tracking and holding switch module is in a holding state, the base electrode potential is effectively reduced through the base electrode resistance of the sampling switch tube, and the base electrode voltage is fixed to a fixed value through the clamping unit, so that the base error of the sampling switch tube is reduced, the signal establishing time is prolonged, and the signal bandwidth is ensured; through the sampling delay adjustable technology, the clock module is designed based on the plurality of clock delay units and the clock selection unit, so that the clock signal with flexibly adjustable delay is obtained, and the improvement of the post-stage quantization and comparison precision is facilitated.

Description

Broadband high-speed tracking and holding circuit

Technical Field

The invention relates to the technical field of analog integrated circuits, in particular to a broadband high-speed tracking and holding circuit.

Background

The application of digital circuits in the modern communication field is more and more extensive, which makes the requirement of a digital signal processing system for signal acquisition continuously increase, and an analog-to-digital converter is a very important key module as a bridge of digital discrete signals and analog continuous signals, and develops towards the direction of high speed, high precision and low power consumption. The tracking and holding circuit is widely applied to the front end of an analog-digital converter, the sampling speed and the sampling precision of the tracking and holding circuit directly influence the performance of the analog-digital converter, and the tracking and holding circuit is a difficult point for researching the analog-digital converter and restricts the development of the analog-digital converter in the ultra-high speed field.

In the prior art, based on the characteristic that the cut-off frequency of the bipolar transistor can reach hundreds of GHz and even higher, the bipolar transistor is generally used as a sampling switch to achieve the high-speed design goal. However, the actual transistors all have parasitic capacitance, and when the switching tube is in an off state, signals are coupled to the output end through the parasitic capacitance, so that signal feed-through is generated, and sampling precision is seriously influenced. When the circuit is in a holding state, although the base voltage of the switch tube is pulled down, the base potential cannot be fixed due to the existence of parasitic capacitance, and a base error exists. And the base potential of the switch tube is pulled low, so that the preceding stage can be in a saturated state, and the signal establishment time and the signal bandwidth during state switching are influenced.

Therefore, a high-precision broadband high-speed track-and-hold circuit is needed.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, the present invention provides a high-precision broadband high-speed track-and-hold circuit, which is used to solve the above-mentioned technical problems.

To achieve the above and other related objects, the present invention provides the following technical solutions.

A wideband high speed track and hold circuit comprising:

the input buffer is used for receiving differential input signals, buffering and amplifying the differential input signals and outputting the signals;

the tracking and holding switch module is connected with the output end of the input buffer at the input end, samples and holds the buffered and amplified differential input signal, and comprises a clamping unit, and the clamping unit clamps the base electrode potential of the sampling switch tube in a holding state;

the input end of the output buffer is connected with the output end of the track-hold switch module, and the output end of the output buffer outputs a sampling signal or a holding signal;

and the output end of the clock module is connected with the track-hold switch module and is used for controlling the switching of a sampling switch tube in the track-hold switch module.

Optionally, the input buffer includes a tandem amplification unit and a feed-forward auxiliary amplification unit, an input end of the tandem amplification unit is connected to the differential input signal, a small signal gain of the differential input signal is increased through the tandem amplification unit, one end of the feed-forward auxiliary amplification unit is connected to an input end of the tandem amplification unit, the other end of the feed-forward auxiliary amplification unit is connected to an output end of the tandem amplification unit, and a collector of an input pair transistor of the tandem amplification unit is nonlinearly transmitted to a collector of an output pair transistor of the tandem amplification unit through the feed-forward auxiliary amplification unit, so that output currents of the output pair transistors are compensated, and nonlinearity of the output currents is suppressed.

Optionally, the tandem amplification unit includes a first NPN triode, a second NPN triode, a third NPN triode, a fourth NPN triode, a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a second capacitor, a first current source, and a second current source, a collector of the first NPN triode is connected to a working voltage through the first resistor in series, a base of the first NPN triode is connected to a first bias voltage, an emitter of the first NPN triode is connected to a collector of the second NPN triode, an emitter of the second NPN triode is grounded through the second resistor and the first current source connected in series in sequence, a base of the second NPN triode is connected to a negative terminal of the differential input signal, a collector of the third NPN triode is connected to the working voltage through the third resistor in series, and a base of the third NPN triode is connected to the first bias voltage, an emitter of the third NPN triode is connected to a collector of the fourth NPN triode, the emitter of the fourth NPN triode is grounded through the fourth resistor and the second current source which are sequentially connected in series, a base of the fourth NPN triode is connected to a positive end of the differential input signal, one end of the first capacitor is connected to a collector of the first NPN triode, the other end of the first capacitor is connected to a collector of the third NPN triode, one end of the second capacitor is connected to an emitter of the second NPN triode, the other end of the second capacitor is connected to an emitter of the fourth NPN triode, wherein the second NPN triode and the fourth NPN triode are used as input pair transistors of the tandem amplification unit, the first NPN triode and the third NPN triode are used as output pair transistors of the tandem amplification unit, and a collector of the first NPN triode is used as an output positive terminal of the tandem amplification unit, and the collector of the third NPN triode is used as the output negative terminal of the cascade amplification unit.

Optionally, the feed-forward auxiliary amplifying unit comprises a fifth NPN transistor, a sixth NPN transistor, a fifth resistor, a sixth resistor, a third capacitor, and a third current source, the collector of the fifth NPN triode is connected with the collector of the third NPN triode, the base of the fifth NPN triode is connected with the collector of the second NPN triode, an emitter of the fifth NPN triode is grounded after being sequentially connected with the fifth resistor and the third current source in series, the collector of the sixth NPN triode is connected with the collector of the first NPN triode, the base of the sixth NPN triode is connected with the collector of the fourth NPN triode, an emitter of the sixth NPN triode is connected with a common end of the fifth resistor and the third current source after passing through the sixth resistor, one end of the third capacitor is connected with the emitter of the fifth NPN triode, and the other end of the third capacitor is connected with the emitter of the sixth NPN triode.

Optionally, the track-and-hold switch module includes a following sampling unit, a clock switch unit, and the clamping unit, where an input end of the following sampling unit is used as an input end of the track-and-hold switch module, an input end of the following sampling unit is connected to an output end of the input buffer, an output end of the following sampling unit is used as an output end of the track-and-hold switch module, the clock switch unit is connected to the following sampling unit, the clock switch unit switches an operating state of the following sampling unit under control of a clock signal, the clock switch unit is connected to a sampling switch tube of the following sampling unit, and in a holding state of the following sampling unit, a base potential of the sampling switch tube of the following sampling unit is clamped by the clamping unit.

Optionally, the following sampling unit includes a seventh NPN transistor, an eighth NPN transistor, a ninth NPN transistor, a tenth NPN transistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a fourth capacitor, a fifth capacitor, a sixth capacitor, and a seventh capacitor, a collector of the seventh NPN transistor is connected to the operating voltage, a base of the seventh NPN transistor serves as an input negative terminal of the tracking and holding switch module, an emitter of the seventh NPN transistor is connected to a base of the eighth NPN transistor through the seventh resistor, a collector of the eighth NPN transistor is connected to the operating voltage through the eighth resistor, an emitter of the eighth NPN transistor serves as an output negative terminal of the tracking and holding switch module, a collector of the ninth NPN transistor is connected to the operating voltage, and a base of the ninth NPN transistor serves as an input positive terminal of the tracking and holding switch module, an emitter of the ninth NPN triode is connected to a base of the tenth NPN triode after passing through the ninth resistor in series, a collector of the tenth NPN triode is connected to the working voltage after passing through the tenth resistor in series, an emitter of the tenth NPN triode serves as an output positive terminal of the tracking and holding switch module, one end of the fourth capacitor is connected to an emitter of the eighth NPN triode, the other end of the fourth capacitor is grounded, one end of the fifth capacitor is connected to an emitter of the tenth NPN triode, the other end of the fifth capacitor is grounded, one end of the sixth capacitor is connected to a base of the eighth NPN triode, the other end of the sixth capacitor is connected to an emitter of the tenth NPN triode, one end of the seventh capacitor is connected to an emitter of the eighth NPN triode, and the other end of the seventh capacitor is connected to a base of the tenth NPN triode, the eighth NPN triode and the tenth NPN triode are the sampling switching tubes.

Optionally, the clamping unit includes a unit gain buffer, an eleventh NPN transistor, and a twelfth NPN transistor, a first input of the unit gain buffer is connected to an emitter of the eighth NPN transistor, a first output of the unit gain buffer is connected to a base of the eleventh NPN transistor, a collector of the eleventh NPN transistor is connected to the operating voltage, an emitter of the eleventh NPN transistor is connected to a base of the eighth NPN transistor, a second input of the unit gain buffer is connected to an emitter of the tenth NPN transistor, a second output of the unit gain buffer is connected to a base of the twelfth NPN transistor, a collector of the twelfth NPN transistor is connected to the operating voltage, and an emitter of the twelfth NPN transistor is connected to a base of the tenth NPN transistor.

Optionally, the clock switching unit includes a thirteenth NPN transistor, a fourteenth NPN transistor, a fifteenth NPN transistor, a sixteenth NPN transistor, a seventeenth NPN transistor, an eighteenth NPN transistor, a nineteenth NPN transistor, a twentieth NPN transistor, a fourth current source, a fifth current source, a sixth current source, and a seventh current source, a collector of the thirteenth NPN transistor is connected to an emitter of the seventh NPN transistor, a base of the thirteenth NPN transistor is connected to the first clock signal, an emitter of the thirteenth NPN transistor is grounded through the series connection of the fourth current source, a collector of the fourteenth NPN transistor is connected to a base of the eighth NPN transistor, a base of the fourteenth NPN transistor is connected to the second clock signal, an emitter of the fourteenth NPN transistor is connected to an emitter of the thirteenth NPN transistor, and a collector of the fifteenth NPN transistor is connected to a collector of the fourteenth NPN transistor, a base electrode of the fifteenth NPN triode is connected to the base electrode of the fourteenth NPN triode, an emitter electrode of the fifteenth NPN triode is grounded through the fifth current source connected in series, a collector electrode of the sixteenth NPN triode is connected to the emitter electrode of the eighth NPN triode, a base electrode of the sixteenth NPN triode is connected to the base electrode of the thirteenth NPN triode, an emitter electrode of the sixteenth NPN triode is connected to the emitter electrode of the fifteenth NPN triode, a collector electrode of the seventeenth NPN triode is connected to the emitter electrode of the tenth NPN triode, a base electrode of the seventeenth NPN triode is connected to the first clock signal, an emitter electrode of the seventeenth NPN triode is grounded through the sixth current source connected in series, a collector electrode of the eighteenth NPN triode is connected to the base electrode of the tenth NPN triode, and a base electrode of the eighteenth NPN triode is connected to the second clock signal, an emitting electrode of the eighteenth NPN triode is connected with an emitting electrode of the seventeenth NPN triode, a collecting electrode of the nineteenth NPN triode is connected with a collecting electrode of the eighteenth NPN triode, a base electrode of the nineteenth NPN triode is connected with a base electrode of the eighteenth NPN triode, an emitting electrode of the nineteenth NPN triode is grounded after passing through the seventh current source which is connected in series, a collecting electrode of the twentieth NPN triode is connected with an emitting electrode of the ninth NPN triode, a base electrode of the twentieth NPN triode is connected with a base electrode of the seventeenth NPN triode, and an emitting electrode of the twentieth NPN triode is connected with an emitting electrode of the nineteenth NPN triode.

Optionally, the output buffer includes a high-gain operational amplifier unit and a buffer amplifier unit, an input terminal of the high-gain operational amplifier unit is connected to an output terminal of the track-hold switch module, an output terminal of the high-gain operational amplifier unit is connected to an input terminal of the buffer amplifier unit, an output terminal of the buffer amplifier unit outputs the sampling signal or the holding signal, in the output buffer, the high-gain operational amplifier unit performs accurate duplication of the input signal and performs front-and-back stage isolation, and the buffer amplifier unit amplifies the input signal to optimize linearity of the input signal.

Optionally, the high-gain operational amplifier unit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a twenty-first NPN triode, a twenty-second NPN triode, a twenty-third NPN triode, a twenty-fourth NPN triode, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, an eighth current source, a ninth current source, and a tenth current source, where a source of the first PMOS transistor is connected to the working voltage, a gate of the first PMOS transistor is connected to a drain of the first PMOS transistor, a drain of the first PMOS transistor is grounded via the eighth current source connected in series, a source of the second PMOS transistor is connected to the working voltage, a gate of the second PMOS transistor is connected to a gate of the first PMOS transistor, a source of the third PMOS transistor is connected to the working voltage, a gate of the third PMOS transistor is connected to the gate of the first PMOS transistor, and a collector of the twenty-first NPN triode is connected to the working voltage in series via the eleventh resistor, a base electrode of the twenty-first NPN triode is connected to the negative output terminal of the tracking and maintaining switch module, an emitter electrode of the twenty-first NPN triode is grounded through the ninth current source connected in series, a collector electrode of the twenty-second NPN triode is connected to the drain electrode of the second PMOS transistor through the twelfth resistor connected in series, an emitter electrode of the second twelve NPN triode is connected to the emitter electrode of the twenty-first NPN triode, a collector electrode of the twenty-third NPN triode is connected to the working voltage through the thirteenth resistor connected in series, a base electrode of the twenty-third NPN triode is connected to the positive output terminal of the tracking and maintaining switch module, an emitter electrode of the twenty-third NPN triode is grounded through the tenth current source connected in series, a collector electrode of the twenty-fourth NPN triode is connected to the drain electrode of the third PMOS transistor through the fourteenth resistor connected in series, and an emitter electrode of the twenty-fourth NPN triode is connected to the emitter electrode of the thirteenth NPN triode, the base electrode of the twenty-first NPN triode is used as the input negative terminal of the high-gain operational amplifier unit, the base electrode of the twenty-second NPN triode is used as the output negative terminal of the high-gain operational amplifier unit, the base electrode of the twenty-third NPN triode is used as the input positive terminal of the high-gain operational amplifier unit, and the base electrode of the twenty-fourth NPN triode is used as the output positive terminal of the high-gain operational amplifier unit.

Optionally, the buffer amplifying unit includes a twenty-fifth NPN triode, a twenty-sixth NPN triode, a twenty-seventh NPN triode, a twenty-eighth NPN triode, a twenty-ninth NPN triode, a thirty-third NPN triode, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, a twentieth resistor, an eleventh current source, a twelfth current source, a thirteenth current source, and a fourteenth current source, a collector of the twenty-fifth NPN triode is connected to the operating voltage through the fifteenth resistor in series, a base of the twenty-fifth NPN triode is connected to the drain of the second PMOS transistor, an emitter of the twenty-fifth NPN triode is connected to the ground through the sixteenth resistor and the eleventh current source in series in sequence, and an emitter of the twenty-fifth NPN triode is further connected to the base of the twenty-twelfth NPN triode, a collector of the twenty-sixth NPN triode is connected with the working voltage through the seventeenth resistor in series, a base of the twenty-sixth NPN triode is connected with a collector of the twenty-fifth NPN triode, an emitter of the twenty-sixth NPN triode is connected with a collector of the twenty-seventh NPN triode, a collector of the twenty-seventh NPN triode is connected with a base of the twenty-seventh NPN triode, an emitter of the twenty-seventh NPN triode is connected with the ground through the twelfth current source in series, a collector of the twenty-eighth NPN triode is connected with the working voltage through the eighteenth resistor in series, a base of the twenty-eighteenth NPN triode is connected with a drain of the third NPN transistor, an emitter of the twenty-eighth NPN triode is connected with the nineteenth resistor and the thirteenth current source in series in sequence and then connected with the ground, and an emitter of the twenty-eighth NPN triode is further connected with a base of the twenty-fourteenth NPN triode, the collector of the twenty-ninth NPN triode is connected with the working voltage through the twentieth resistor in series, the base of the twenty-ninth NPN triode is connected with the collector of the twenty-eighteenth NPN triode, the emitter of the twenty-ninth NPN triode is connected with the collector of the thirty-ninth NPN triode, the collector of the thirty-ninth NPN triode is connected with the base of the thirty-fifth NPN triode, and the emitter of the thirty-fifth NPN triode is connected with the ground through the fourteenth current source in series, wherein the emitter of the twenty-seventh NPN triode serves as the negative output terminal of the buffer amplification unit, and the emitter of the thirty-fifth NPN triode serves as the positive output terminal of the buffer amplification unit.

Optionally, the clock module outputs a delay-adjustable clock signal to the track-and-hold switch module under the selective control of a control signal.

Optionally, the clock module includes a first clock delay unit, a second clock delay unit, a third clock delay unit, a fourth clock delay unit, a first clock selection unit, a second clock selection unit, and a third clock selection unit, wherein a clock input signal is respectively connected to an input terminal of the first clock delay unit and a first input terminal of the third clock selection unit, an output terminal of the first clock delay unit is respectively connected to an input terminal of the second clock delay unit and a first input terminal of the second clock selection unit, an output terminal of the second clock delay unit is respectively connected to an input terminal of the third clock delay unit and a second input terminal of the first clock selection unit, an output terminal of the third clock delay unit is connected to an input terminal of the fourth clock delay unit, and an output terminal of the fourth clock delay unit is connected to a first input terminal of the first clock selection unit, the third input end of the first clock selection unit is connected with a first control signal, the output end of the first clock selection unit is connected with the second input end of the second clock selection unit, the third input end of the second clock selection unit is connected with a second control signal, the output end of the second clock selection unit is connected with the second input end of the third clock selection unit, the third input end of the third clock selection unit is connected with a third control signal, and the output end of the third clock selection unit outputs the clock signal.

As described above, the broadband high-speed track-and-hold circuit of the present invention has at least the following advantages:

the whole broadband high-speed track-hold circuit comprises four parts, namely an input buffer, a track-hold switch module, an output buffer and a clock module, and the input buffer and the output buffer effectively buffer and isolate input signals and output signals, so that the structural stability and the sampling precision of the whole broadband high-speed track-hold circuit are ensured; the tracking and holding switch module comprises a clamping unit, and the base electrode potential of the sampling switch tube is clamped by the clamping unit in a holding state, so that the substrate error caused by parasitic capacitance can be effectively avoided, the signal establishing time is prolonged, and the signal bandwidth is ensured.

Drawings

Fig. 1 shows a circuit diagram of a track and hold circuit in the prior art.

Fig. 2 is a block diagram of a wideband high-speed track-and-hold circuit according to an embodiment of the invention.

Fig. 3 is a circuit diagram of the input buffer of fig. 2.

Fig. 4 is a circuit diagram of the clock module of fig. 2.

Fig. 5 is a circuit diagram of the track and hold switch module of fig. 2.

Fig. 6 is a circuit diagram of the output buffer of fig. 2.

Fig. 7 is a time domain waveform diagram obtained by simulation test of the broadband high-speed track-and-hold circuit according to an embodiment of the present invention.

Fig. 8 shows a graph of the frequency domain dynamic performance parameters derived from fig. 7.

FIG. 9 is a waveform diagram illustrating simulation of AC bandwidth of the broadband high-speed track-and-hold circuit according to an embodiment of the present invention.

Detailed Description

As described in the foregoing background, the inventors have studied and found that, for the track-and-hold circuit shown in fig. 1, which includes NPN transistors Q01, Q02, Q03, Q04, Q05, resistors R01, R02, a holding capacitor Ch, and three current sources, a base of the NPN transistor Q01 receives an input signal Vin, the NPN transistor Q01 and a resistor R01 form an input buffer, the input signal Vin is buffered, a base of the NPN transistor Q05 receives a sampling signal/holding signal, the NPN transistor Q05 and the resistor R02 form an output buffer, specifically: when T is greater than H, the NPN type triodes Q02 and Q04 are conducted, signals flow to the output buffer through the NPN type triode Q02, and the circuit works in a sampling mode; when H > T, the NPN type triode Q01 is conducted, the base electrode potential of the NPN type triode Q02 is pulled low, the NPN type triodes Q02 and Q04 are in a cut-off state, the base electrode potential of the NPN type triode Q02 is lowered, the circuit is in a holding mode, and in the holding mode, the charges on the holding capacitor Ch serve as the circuit to be output to the output buffer.

However, the actual transistors all have parasitic capacitance, and when the sampling switch tube (NPN transistor Q02) is in an off state, the signal is coupled to the output end through the parasitic capacitance, so that signal feed-through is generated, and the sampling precision is seriously affected. When the circuit is in a holding state, although the base voltage of the switch tube is pulled down, the base potential cannot be fixed due to the existence of parasitic capacitance, and a base error exists. And the base potential of the switch tube is pulled low, so that the NPN transistor Q01 at the front stage may be in a saturation state, thereby affecting the signal setup time and the signal bandwidth during state switching.

Therefore, a high-speed high-bandwidth track-and-hold circuit is proposed in chinese patent CN204376880U, and the circuit design employs an auxiliary switch emitter follower. In a sampling mode, the output of the emitter of the auxiliary switching tube directly carries out feedforward on the output of the current source of the main switching follower through the Cff feedforward capacitor, so that the linearity error is reduced, and in a holding mode, the auxiliary switching tube and the main switching tube are simultaneously turned off, so that the output of the holding mode of the circuit is not influenced. However, the circuit has disadvantages in that: 1) although the quasi-differential input stage driving circuit is adopted, the influence of the switching tube on the input tube is isolated, and the signal bandwidth is optimized, the linearity of the high frequency of the circuit is not improved, and the signal at the output end is not isolated, so that the signal accuracy is kept; 2) the clamping tube Qclp1 can prevent the output node of the quasi-differential output stage from being pulled down too low, so that the cut-off of the switch tube during holding is ensured, but the breakdown voltage value of the high-frequency fT bipolar tube Vce is small, so that the breakdown risk exists in the circuit design, the high-frequency fT bipolar tube is only suitable for low-voltage design, and the bandwidth is influenced by increasing the resistance.

In addition, chinese patent CN107196637A discloses a GaAs HBT track-and-hold circuit in the patent "high sampling rate broadband track-and-hold circuit", which uses input and output buffers with emitter degeneration resistors, reduces third harmonic distortion, and increases the sampling rate by adding a schottky diode between the sampling switch and the holding capacitor. However, the method also has the disadvantages that the base electrode potential of the switch device in the hold mode is not fixed, so that a certain time is required for the switch device of the circuit to be in a saturation state to be in a forward amplification state, the setup time of a signal is prolonged, and the bandwidth of the signal is affected. And the GaAs HBT process has higher manufacturing cost and limited application.

Based on the SiGe BiCMOS process, the invention provides a tracking and holding circuit with a brand-new structure, which comprises the following steps:

1) the whole broadband high-speed track-hold circuit is divided into four parts, namely an input buffer, a track-hold switch module, an output buffer and a clock module, and the input buffer and the output buffer and isolate input signals and output signals so as to ensure the structural stability and the sampling precision of the whole broadband high-speed track-hold circuit;

2) the input buffer is designed on the basis of adding the cascade amplification unit and the feedforward auxiliary amplification unit, the high-frequency performance of the circuit is improved through the cascade amplification unit, the nonlinearity of exponential increase of the third harmonic distortion of the common-emitter circuit along with the frequency increase is reduced, the nonlinearity of the collector electrode of the input geminate transistor of the cascade amplification unit is transmitted to the collector electrode of the output geminate transistor of the cascade amplification unit through the feedforward auxiliary amplification unit, the output current of the output geminate transistor is compensated, and the nonlinearity of the output current is restrained;

3) the tracking and holding switch module is designed based on the following sampling unit, the clock switch unit and the clamping unit, the working state of the following sampling unit is switched through the clock switch unit, and the base electrode potential of a sampling switch tube of the following sampling unit is clamped through the clamping unit under the holding state of the following sampling unit, so that the substrate error caused by parasitic capacitance is avoided, the signal establishing time is prolonged, and the signal bandwidth is ensured;

4) the output buffer is designed based on the high-gain operational amplification unit and the buffer amplification unit, the isolation of the input signal and the output signal of the current stage is realized through the high-gain operational amplification unit, and the accurate voltage-to-current conversion is realized through the high-gain operational amplification unit, so that the larger bandwidth and the higher gain of the low-frequency loop are ensured, and the harmonic distortion is reduced;

5) and through a sampling delay adjustable technology, designing a clock module based on a plurality of clock delay units and clock selection units to obtain a delay adjustable clock signal, thereby changing the delay time of a rear-end quantization and comparison signal and improving the precision of the analog-to-digital converter.

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

Please refer to fig. 2 to fig. 9. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated. The structures, proportions, sizes, and other dimensions shown in the drawings and described in the specification are for understanding and reading the present disclosure, and are not intended to limit the scope of the present disclosure, which is defined in the claims, and are not essential to the art, and any structural modifications, changes in proportions, or adjustments in size, which do not affect the efficacy and attainment of the same are intended to fall within the scope of the present disclosure.

As shown in fig. 2, the present invention provides a broadband high-speed track-and-hold circuit, which adopts a fully differential structure, and includes:

an input buffer for receiving the differential input signal, buffering the differential input signal and outputting the buffered differential input signal;

the input end of the tracking and holding switch module is connected with the output end of the input buffer, and the tracking and holding switch module samples/holds the differential input signal;

the input end of the output buffer is connected with the output end of the track-hold switch module, and the output end of the output buffer outputs a sampling signal/holding signal;

the output end of the clock module is connected with the track-hold switch module and is used for controlling the switching of a sampling switch tube in the track-hold switch module;

where Vinn is the negative terminal of the differential input signal, Vinp is the positive terminal of the differential input signal, Voutn is the negative terminal of the sample/hold signal, and Voutp is the positive terminal of the sample/hold signal.

In detail, as shown in fig. 3, the input buffer includes a tandem amplification unit and a feedforward auxiliary amplification unit, an input end of the tandem amplification unit is connected to the differential input signal, a small signal gain of the differential input signal is increased by the tandem amplification unit, one end of the feedforward auxiliary amplification unit is connected to an input end of the tandem amplification unit, the other end of the feedforward auxiliary amplification unit is connected to an output end of the tandem amplification unit, and a collector of an input pair transistor of the tandem amplification unit is nonlinearly transmitted to a collector of an output pair transistor of the tandem amplification unit by the feedforward auxiliary amplification unit, so as to compensate an output current of the output pair transistor and suppress nonlinearity of the output current.

In more detail, as shown in fig. 3, the tandem amplifying unit includes a first NPN transistor Q1, a second NPN transistor Q2, a third NPN transistor Q3, a fourth NPN transistor Q4, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first capacitor C1, a second capacitor C2, a first current source I1, and a second current source I2, wherein a collector of the first NPN transistor Q1 is connected to the operating voltage VDD via a first resistor R1 in series, a base of the first NPN transistor Q1 is connected to the first bias voltage Vb1, an emitter of the first NPN transistor Q1 is connected to a collector of the second NPN transistor Q2, an emitter of the second NPN transistor Q2 is grounded via a second resistor R7 and a first current source I1 connected in series in turn, a base of the second NPN transistor Q2 is connected to the negative terminal Vinn of the input signal, a collector of the third NPN transistor Q2 is connected to the differential voltage 2 via a collector of the third NPN transistor 2 and a collector 2, an emitter of the third NPN triode Q3 is connected to a collector of the fourth NPN triode Q4, an emitter of the fourth NPN triode Q4 is grounded through a fourth resistor R4 and a second current source I2 which are sequentially connected in series, a base of the fourth NPN triode Q4 is connected to the positive terminal Vinp of the differential input signal, one end of a first capacitor C1 is connected to the collector of the first NPN triode Q1, the other end of the first capacitor C1 is connected to the collector of the third NPN triode Q3, one end of a second capacitor C2 is connected to the emitter of the second NPN triode Q2, the other end of the second capacitor C2 is connected to the emitter of the fourth NPN triode Q4, the second NPN triode Q2 and the fourth NPN triode Q4 are used as input pair transistors of the tandem amplification unit, the first NPN triode Q1 and the third NPN triode Q3 are used as output pair transistors of the tandem amplification unit, a collector of the first NPN triode Q1 is used as an output positive terminal Voutp1 of the tandem amplification unit, and a collector of the third NPN triode Q3 is used as an output negative terminal Voutn1 of the tandem amplification unit.

In more detail, as shown in fig. 3, the feed forward auxiliary amplifying unit includes a fifth NPN transistor Q5, a sixth NPN transistor Q6, a fifth resistor R5, a sixth resistor R6, a third capacitor C3 and a third current source I3, wherein a collector of a fifth NPN triode Q5 is connected to a collector of a third NPN triode Q3, a base of the fifth NPN triode Q5 is connected to a collector of a second NPN triode Q2, an emitter of the fifth NPN triode Q5 is grounded through a fifth resistor R5 and a third current source I3 which are sequentially connected in series, a collector of a sixth NPN triode Q6 is connected to a collector of a first NPN triode Q1, a base of a sixth NPN triode Q6 is connected to a collector of a fourth NPN triode Q4, an emitter of a sixth NPN triode Q6 is connected to a common terminal of the fifth resistor R5 and the third current source I3 through a sixth resistor R6 which is connected in series, one end of a third capacitor C3 is connected to an emitter of the fifth NPN Q5, and the other end of the third capacitor C3 is connected to an emitter of the sixth NPN Q6.

In more detail, as shown in fig. 3, the input buffer provided by the present invention includes a cascade amplification unit with an emitter degeneration resistor and a feed-forward auxiliary amplification unit, and is used for buffering an input differential signal and isolating a signal source from a back-end track-hold switch module, so as to obtain good linearity.

For a tandem amplification unit, the small signal gain formula is generally given by:

in the formula: gm is It/2Vt is the small signal transconductance of the HBT device, R_LIs a load resistor (a first resistor R1 and a third resistor R3 shown in FIG. 3), R_EAre emitter degeneration resistors (second resistor R2 and fourth resistor R4 shown in FIG. 3), R'_EIs the emitter parasitic resistance (unit: omega/mum) of the amplifying tube (the second resistor R2 and the fourth resistor R4 shown in FIG. 3)²)，l_EIs the emitter length, W_EIs the emitter width. When g is_mWhen the gain is more than or equal to 1, the gain of the low-frequency small signal is about

As the frequency increases, the gain decreases due to parasitic influence, and in order to improve the gain flatness, a first capacitor C1 is added at the load resistor end, which increases the load capacitance of the output tube (the first NPN transistor Q1 and the third NPN transistor Q3 in fig. 3), and the main pole changes to fp-1/2 tr_L(2C1//C_jc2) Thereby reducing bandwidth.

To balance the high frequency gain and bandwidth, compensation is performed across the second capacitor C2 at the emitter degeneration resistor end. The design can be used for compensating the influence of the collector parasitic capacitance coupling of tail current sources (the first current source I1 and the second current source I2 in the figure 3) to emitter degeneration resistance on high-frequency performance, and can also generate a zero point fz of 1/2 pi Re (2C2// C)_je1) And therefore, the high-frequency gain of the circuit is ensured, and finally, the 3dB bandwidth of the cascade amplification unit is related to the first capacitor C1 and the second capacitor C2.

The feedforward auxiliary amplification unit modulates the collector current of the input differential tube by adopting a feedforward technology, transmits the collector nonlinearity of the input geminate tube to the collector of the output geminate tube through positive feedback, and compensates the current of the output differential tube, thereby inhibiting the nonlinearity of the circuit.

In detail, as shown in fig. 4, the clock module outputs a delay-adjustable clock signal Vclkout to the track-hold switch module under the selection control of the control signals Ctr1, Ctr2 and Ctr3, and the clock signal Vclkout drives the sampling switch tube to perform state switching. The input end of the clock input circuit is connected with a clock input signal Vclkin, the output end of the clock input circuit outputs a clock signal Vclkout, Vclkinn is the negative end of the clock input signal Vclkin, Vclkinp is the positive end of the clock input signal Vclkin, Vclkoutn is the negative end of the clock signal Vclkout, and Vclkoutp is the positive end of the clock signal Vclkout.

In more detail, as shown in fig. 4, the clock module includes a first clock delay unit TB1, a second clock delay unit TB2, a third clock delay unit TB3, a fourth clock delay unit TB4, a first clock selection unit TM1, a second clock selection unit TM2, and a third clock selection unit TM3, clock input signals are respectively connected to an input terminal of the first clock delay unit TB1 and a first input terminal of the third clock selection unit TM3, an output terminal of the first clock delay unit TB1 is respectively connected to an input terminal of the second clock delay unit TB2 and a first input terminal of the second clock selection unit TM2, an output terminal of the second clock delay unit TB2 is respectively connected to an input terminal of the third clock delay unit TB3 and a second input terminal of the first clock selection unit TM1, an output terminal of the third clock delay unit TB3 is connected to an input terminal of the fourth clock delay unit TB4, an output terminal of the fourth clock delay unit 4 is connected to a first input terminal of the first clock selection unit TB1, the third input of the first clock selecting unit TM1 is connected to the first control signal Ctr1, the output of the first clock selecting unit TM1 is connected to the second input of the second clock selecting unit TM2, the third input of the second clock selecting unit TM2 is connected to the second control signal Ctr2, the output of the second clock selecting unit TM2 is connected to the second input of the third clock selecting unit TM3, the third input of the third clock selecting unit TM3 is connected to the third control signal Ctr3, and the output of the third clock selecting unit TM3 outputs the clock signal Vclkout.

As shown in fig. 4, in an alternative embodiment of the present invention, the output signal delay of the first clock delay unit TB1 is 33ps, the output signal delay of the second clock delay unit TB2 is 24ps, the output signal delay of the third clock delay unit TB3 is 25ps, the output signal delay of the fourth clock delay unit TB4 is 22ps, the output signal delay of the first clock selection unit TM1 is 25ps, the output signal delay of the second clock selection unit TM2 is 22ps, and the output signal of the third clock selection unit TM3 is not delayed. Under the control of the control signal Ctr1, the clock input signal Vclkin passes through the first clock delay unit TB1, the second clock delay unit TB2, the third clock delay unit TB3, the fourth clock delay unit TB4, the first clock selection unit TM1, the second clock selection unit TM2 and the third clock selection unit TM3 to obtain 150ps delay; the clock input signal Vclkin is delayed by 100ps by passing through the first clock delay unit TB1, the second clock delay unit TB2, the first clock selection unit TM1, the second clock selection unit TM2, and the third clock selection unit TM 3. Under the control of the control signal Ctr2, the clock input signal Vclkin is delayed by 55ps by the first clock delay unit TB1, the second clock delay unit TB2 and the third clock delay unit TB 3. Under the control of the control signal Ctr3, the clock input signal Vclkin is directly output, and the delay time is 0 ps.

In detail, as shown in fig. 5, the track-hold switch module includes a following sampling unit, a clock switch unit and a clamping unit, an input end of the following sampling unit serves as an input end of the track-hold switch module, an input end of the following sampling unit is connected to an output end of the input buffer, an output end of the following sampling unit serves as an output end of the track-hold switch module, the clock switch unit is connected to the following sampling unit, the clock switch unit switches a working state of the following sampling unit under control of a clock signal Vclkout, the clock switch unit is connected to a sampling switch tube of the following sampling unit, and a base potential of the sampling switch tube of the following sampling unit is clamped by the clamping unit in a holding state of the following sampling unit.

In more detail, as shown in fig. 5, the follow-sampling unit includes a seventh NPN transistor Q7, an eighth NPN transistor Q8, a ninth NPN transistor Q9, a tenth NPN transistor Q10, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, and a seventh capacitor C7, a collector of the seventh NPN transistor Q7 is connected to the operating voltage VDD, a base of the seventh NPN transistor Q7 is used as an input negative terminal of the track-hold switch module, a base of the seventh NPN transistor Q7 is connected to the output negative terminal Voutn1 of the series amplification unit, an emitter of the seventh NPN transistor Q7 is connected to the base of the eighth NPN transistor Q8 through a seventh resistor R7, a collector of the eighth NPN transistor Q8 is connected to the operating voltage Voutn 8 in series, and an emitter of the eighth NPN transistor Q8 is used as an output terminal of the track-hold switch module Voutn2, a collector of the ninth NPN transistor Q9 is connected to the operating voltage VDD, a base of the ninth NPN transistor Q9 serves as an input positive terminal of the tracking and holding switch module, a base of the ninth NPN transistor Q9 is connected to the output positive terminal Voutp1 of the cascade amplification unit, an emitter of the ninth NPN transistor Q9 is connected to the base of the tenth NPN transistor Q10 through the ninth resistor R9, a collector of the tenth NPN transistor Q10 is connected to the operating voltage VDD through the tenth resistor R10, an emitter of the tenth NPN transistor Q10 serves as the output positive terminal Voutp2 of the tracking and holding switch module, one end of the fourth capacitor C4 is connected to the emitter of the eighth NPN transistor Q8, the other end of the fourth capacitor C4 is grounded, one end of the fifth capacitor C5 is connected to the emitter of the tenth NPN transistor Q10, the other end of the fifth capacitor C5 is grounded, one end of the sixth capacitor C6 is connected to the base of the eighth NPN transistor Q8, and the other end of the emitter of the sixth capacitor C67 6 is connected to the emitter of the NPN transistor Q10. One end of the seventh capacitor C7 is connected to the emitter of the eighth NPN transistor Q8, and the other end of the seventh capacitor C7 is connected to the base of the tenth NPN transistor Q10, wherein the eighth NPN transistor Q8 and the tenth NPN transistor Q10 are sampling switching tubes.

More specifically, as shown in fig. 5, the clamping unit includes a unit gain buffer AMP, an eleventh NPN transistor Q11 and a twelfth NPN transistor Q12, a first input of the unit gain buffer AMP is connected to an emitter of the eighth NPN transistor Q8, a first output of the unit gain buffer AMP is connected to a base of the eleventh NPN transistor Q11, a collector of the eleventh NPN transistor Q11 is connected to the operating voltage VDD, an emitter of the eleventh NPN transistor Q11 is connected to a base of the eighth NPN transistor Q8, a second input of the unit gain buffer AMP is connected to an emitter of the tenth NPN transistor Q10, a second output of the unit gain buffer AMP is connected to a base of the twelfth NPN transistor Q12, a collector of the twelfth NPN transistor Q12 is connected to the operating voltage VDD, and an emitter of the twelfth NPN transistor Q12 is connected to a base of the tenth NPN transistor Q10.

In more detail, as shown in fig. 5, the clock switching unit includes a thirteenth NPN transistor Q13, a fourteenth NPN transistor Q14, a fifteenth NPN transistor Q15, a sixteenth NPN transistor Q16, a seventeenth NPN transistor Q17, an eighteenth NPN transistor Q18, a nineteenth NPN transistor Q19, a twentieth NPN transistor Q20, a fourth current source I4, a fifth current source I5, a sixth current source I6, and a seventh current source I7, a collector of the thirteenth NPN transistor Q13 is connected to an emitter of the seventh NPN transistor Q7, a base of the thirteenth NPN transistor Q56 13 is connected to the first clock signal T, an emitter of the thirteenth NPN transistor Q13 is grounded through the fourth current source I4 connected in series, a collector of the fourteenth NPN transistor Q14 is connected to a base of the eighth NPN transistor Q8, a base of the fourteenth NPN transistor Q14 is connected to the second clock signal H, an emitter of the fourteenth transistor Q14 is connected to an emitter Q13, a collector of the fifteenth NPN transistor Q15 is connected to a collector of the fourteenth NPN transistor Q14, a base of the fifteenth NPN transistor Q15 is connected to a base of the fourteenth NPN transistor Q14, an emitter of the fifteenth NPN transistor Q15 is grounded through the series-connected fifth current source I5, a collector of the sixteenth NPN transistor Q16 is connected to an emitter of the eighth NPN transistor Q8, a base of the sixteenth NPN transistor Q16 is connected to a base of the thirteenth NPN transistor Q13, an emitter of the sixteenth NPN transistor Q16 is connected to an emitter of the fifteenth NPN transistor Q15, a collector of the seventeenth NPN transistor Q17 is connected to an emitter of the tenth NPN transistor Q10, a base of the seventeenth NPN transistor Q17 is connected to the first clock signal T in series, an emitter of the seventeenth NPN transistor Q17 is grounded through the sixth current source I6, a collector of the eighteenth NPN transistor Q18 is connected to a base of the tenth NPN transistor Q10, and a base of the eighteenth transistor Q18 is connected to the second clock signal H, an emitter of the eighteenth NPN triode Q18 is connected to an emitter of the seventeenth NPN triode Q17, a collector of the nineteenth NPN triode Q19 is connected to a collector of the eighteenth NPN triode Q18, a base of the nineteenth NPN triode Q19 is connected to a base of the eighteenth NPN triode Q18, an emitter of the nineteenth NPN triode Q19 is grounded through a seventh current source I7 connected in series, a collector of the twentieth NPN triode Q20 is connected to an emitter of the ninth NPN triode Q9, a base of the twentieth NPN triode Q20 is connected to a base of the seventeenth NPN triode Q17, and an emitter of the twentieth NPN triode Q20 is connected to an emitter of the nineteenth NPN triode Q19.

The first clock signal T and the second clock signal H are signals of two differential output ports of the clock signal Vclkout, respectively.

In more detail, as shown in fig. 5, the track-and-hold switch module completes sampling of the input signal and outputs a track-and-hold signal under the driving of the clock signal Vclkout. The operation principle of the track and hold switch module is as follows: when the first clock signal T > the second clock signal H, the thirteenth NPN transistor Q13 and the sixteenth NPN transistor Q16 are turned on, the fourteenth NPN transistor Q14 and the fifteenth NPN transistor Q15 are turned off, and at this time, in a sampling state, the eighth NPN transistor Q8 is turned on, almost all of the current of the fourth current source I4 flows through the seventh NPN transistor Q7, almost all of the current of the fifth current source I5 flows through the eighth NPN transistor Q8, and the current flowing through the seventh resistor R7 is negligible, the output signal changes along with the input signal, and the fourth capacitor C4 stores energy, and at this time, the emitter current Iee of the eighth NPN transistor Q8 is I5; when the first clock signal T < the second clock signal H, the fourteenth NPN transistor Q14 and the fifteenth NPN transistor Q15 are turned on, the thirteenth NPN transistor Q13 and the sixteenth NPN transistor Q16 are turned off, and at this time, in a hold state, the eighth NPN transistor Q8 is turned off, and the current of the fourth current source I4 and the current of the fifth current source I5 all flow through the seventh resistor R7, so that the base potential of the eighth NPN transistor Q8 is pulled down, the current at the seventh resistor R7 is I4+ I5 ═ Ir7, the base voltage of the eighth NPN transistor Q8 (sampling switch) is dropped to Ir7 × R7 at the time of state switching, and a small seventh resistor R7 is used to pull down the base level of the eighth NPN transistor Q8 to a reasonable level without changing the on-bias current Iee of the sampling switch, thereby setting a reasonable level, ensuring a reasonable signal bandwidth, and improving the parasitic capacitance of the conventional NPN switch, the linearity is improved.

In more detail, as shown in fig. 5, the unity gain buffer AMP and the eleventh NPN transistor Q11 form a clamping circuit, and in the holding state, the level stored in the fourth capacitor C4 is sent to the output buffer as an output signal, and at the same time, the emitter potential of the eighth NPN transistor Q8 is transmitted to the base of the eleventh NPN transistor Q11 via the unity gain buffer AMP, so as to clamp the base potential of the eighth NPN transistor Q8, and the clamped value is related to the emitter junction conduction voltage drop Vbe11 of the eleventh NPN transistor Q11, so as to ensure that the eighth NPN transistor NPN Q8 is completely turned off, and the base potential is a fixed value, thereby eliminating the influence of the input signal fed through the parasitic capacitor to the output terminal. Meanwhile, the sixth capacitor C6 is a feedforward capacitor, and the base of the eighth NPN transistor Q8 is connected to the emitter of the tenth NPN transistor Q10, so that charge injection is counteracted and linearity is improved.

In detail, as shown in fig. 6, the output buffer includes a high-gain operational amplifier unit and a buffer amplifier unit, an input terminal of the high-gain operational amplifier unit is connected to an output terminal of the track-hold switch module, an output terminal of the high-gain operational amplifier unit is connected to an input terminal of the buffer amplifier unit, an output terminal of the buffer amplifier unit outputs a sampling signal/hold signal, in the output buffer, the high-gain operational amplifier unit performs accurate replication of an input signal, the high-gain operational amplifier unit performs front-stage and back-stage isolation, and the buffer amplifier unit amplifies the input signal, thereby optimizing linearity of the input signal.

In more detail, as shown in fig. 6, the high-gain operational amplifier unit includes a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a twenty-first NPN transistor Q21, a twenty-second NPN transistor Q22, a twenty-third NPN transistor Q23, a twenty-fourth NPN transistor Q24, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, an eighth current source I8, a ninth current source I9, and a tenth current source I10, a source of the first PMOS transistor P1 is connected to the operating voltage VDD, a gate of the first PMOS transistor P1 is connected to a drain of the first PMOS transistor P1, a drain of the first PMOS transistor P1 is connected in series to the ground via the eighth current source I8, a source of the second PMOS transistor P8 is connected to the operating voltage, a gate of the second PMOS transistor P8 is connected in series to the gate of the first PMOS transistor P8, a source of the third PMOS transistor P8 is connected to the gate of the second PMOS transistor P8, a collector of the second PMOS transistor P8 is connected to the gate of the second PMOS transistor P8, a collector of the second PMOS transistor P8, the base of the twenty-first NPN triode Q21 is connected to the output negative terminal Voutn2 of the tracking and maintaining switch module, the emitter of the twenty-first NPN triode Q21 is grounded through the serially connected ninth current source I9, the collector of the twenty-second NPN triode Q22 is connected to the drain of the second PMOS transistor P2 through the serially connected twelfth resistor R12, the emitter of the twenty-second NPN triode Q22 is connected to the emitter of the twenty-first NPN triode Q21, the collector of the twenty-third NPN triode Q23 is connected to the operating voltage VDD through the serially connected thirteenth resistor R113, the base of the twenty-third NPN triode Q23 is connected to the output positive terminal Voutp2 of the tracking and maintaining switch module, the emitter of the twenty-third NPN triode Q23 is grounded through the serially connected tenth current source I10, the collector of the twenty-fourth NPN triode Q24 is connected to the drain of the third PMOS transistor P3 through the serially connected fourteenth resistor R14, and the emitter of the twenty-fourth NPN Q24 is connected to the emitter 23, the base electrode of the twenty-first NPN triode Q21 is used as the input negative terminal of the high-gain operational amplifier unit, the base electrode of the twenty-second NPN triode Q22 is used as the output negative terminal of the high-gain operational amplifier unit, the base electrode of the twenty-third NPN triode Q23 is used as the input positive terminal of the high-gain operational amplifier unit, and the base electrode of the twenty-fourth NPN triode Q24 is used as the output positive terminal of the high-gain operational amplifier unit.

In more detail, as shown in fig. 6, the buffer amplifying unit includes a twenty-fifth NPN transistor Q25, a twenty-sixth NPN transistor Q26, a twenty-seventh NPN transistor Q27, a twenty-eighth NPN transistor Q28, a twenty-ninth NPN transistor Q29, a thirty-third NPN transistor Q30, a fifteenth resistor R15, a sixteenth resistor R16, a seventeenth resistor R17, an eighteenth resistor R18, a nineteenth resistor R19, a twentieth resistor R20, an eleventh current source I11, a twelfth current source I12, a thirteenth current source I13, and a fourteenth current source I14, wherein a collector of the twenty-fifth NPN transistor Q25 is connected in series with the operating voltage VDD through a fifteenth resistor R15, a base of the twenty-fifth NPN transistor Q25 is connected to a drain of the second PMOS transistor P2, an emitter of the twenty-fifth NPN transistor Q25 is connected in series with a base R16 and an eleventh current source I11, and an emitter 25 of the twenty-fifth NPN transistor Q22, a collector of a twenty-sixth NPN triode Q26 is connected to the working voltage VDD through a seventeenth resistor R17 connected in series, a base of a twenty-sixth NPN triode Q26 is connected to a collector of a twenty-fifth NPN triode Q25, an emitter of the twenty-sixth NPN triode Q26 is connected to a collector of a twenty-seventh NPN triode Q27, a collector of a twenty-seventh NPN triode Q27 is connected to a base of a twenty-seventh NPN triode Q27, an emitter of the twenty-seventh NPN triode Q27 is connected to ground through a twelfth current source I12 connected in series, a collector of a twenty-eighth NPN triode Q28 is connected to the working voltage VDD through an eighteenth resistor R18 connected in series, a base of the twenty-eighth NPN triode Q28 is connected to a drain of a third PMOS P3, an emitter of the twenty-eighth NPN triode Q28 is connected to ground through a nineteenth resistor R19 and a thirteenth current source I13 connected in series in sequence, and an emitter of the twenty-eighth triode Q28 is further connected to a base of a twenty-fourth NPN PMOS Q24, a collector of the twenty-ninth NPN triode Q29 is connected to the working voltage VDD through a twentieth resistor R20 connected in series, a base of the twenty-ninth NPN triode Q29 is connected to a collector of the twenty-eighth NPN triode Q28, an emitter of the twenty-ninth NPN triode Q29 is connected to a collector of the thirty-ninth NPN triode Q30, a collector of the thirty-ninth NPN triode Q30 is connected to a base of the thirty-eighth NPN triode Q30, and an emitter of the thirty-ninth NPN triode Q30 is connected to the ground through a fourteenth current source I14 connected in series, wherein an emitter of the twenty-seventh NPN triode Q27 serves as an output negative terminal Voutn of the buffer amplification unit (or output buffer), and an emitter of the thirty-ninth NPN triode Q30 serves as an output positive terminal Voutp of the buffer amplification unit (or output buffer).

In more detail, as shown in fig. 6, the output buffer provided by the present invention is used for isolating a holding capacitor from an output load, reducing charge leakage in a holding state, providing a certain voltage gain, and buffering an output signal, and includes a high-gain operational amplifier unit and a buffer amplifier unit. The high-gain operational amplifier unit is a quasi-differential feedback amplifier, and mirrors the current of the eighth current source I8 to the twelfth resistor R12 through a MOS current mirror formed by the first PMOS transistor P1 and the second PMOS transistor P2, so as to provide a driving current for a symmetrical replica structure formed by the twenty-first NPN triode Q21 and the twenty-second NPN triode Q22, wherein the emitter current Ie22 of the twenty-second NPN triode Q22 is I8I 9/2, and the tracking and holding signal output by the tracking and holding switch module is accurately replicated to an output terminal (the base of the twenty-second NPN Q22) through a symmetrical replica structure formed by the twenty-first NPN triode Q21 and the twenty-second NPN triode Q22, so that the isolation between the tracking and holding signal and a rear-end load is greatly improved, and the droop rate of the front-stage holding signal can be effectively improved. In the buffer amplification unit, the twenty-fifth NPN triode Q25 is used as an amplification tube, the amplitude of an output signal can be reasonably adjusted according to requirements, the LSB of a rear-end signal quantization step length is increased, the precision of an analog-to-digital converter is improved, and the twenty-seventh NPN triode Q27 is used as an emitter follower tube to provide large-current drive for a rear-stage circuit.

In an alternative embodiment of the present invention, the effect of the broadband high-speed track-and-hold circuit provided by the present invention is further explained by combining with simulation tests:

1. simulation conditions are as follows:

the invention adopts 0.18 μm SiGe BiCMOS process, and simulates the characteristic of the track-and-hold circuit in Cadence software.

2. Simulation content:

the main reference indexes of the broadband high-speed tracking and holding circuit comprise sampling clock frequency, input clock frequency, dynamic performance parameters, bandwidth and the like.

3. And (3) simulation results:

FIG. 7 is a time domain waveform diagram of the present invention including a clock waveform, an analog input waveform and a track and hold output waveform, with the abscissa of FIG. 7 being the time of the simulation circuit of the present invention and the ordinate being the amplitude of the variation of the three waveforms of the present invention.

Fig. 8 is a frequency domain dynamic performance parameter diagram obtained by performing transient simulation and FFT transformation on the trace-hold output waveform according to the clock signal and the analog input signal applied in fig. 7. The abscissa in fig. 8 is the value of the analog input frequency of the present invention and the ordinate is the value of the output signal power.

From fig. 7 and 8, it can be seen that under the 2GHz clock input and the 0.99GHz analog input nyquist frequency, the SFDR of the output sample-hold signal is 80.77dB, and the effective number ENOB is 12.82Bit, and it can be seen that the invention can meet the requirements of ultra high speed and high precision.

FIG. 9 is a waveform diagram of the simulation of AC bandwidth of the present invention. The abscissa in fig. 9 is the frequency value of the frequency domain simulation and the ordinate is the power value of the output AC signal. From the results of fig. 9, it can be seen that the bandwidth of the present invention can reach 4GHz, which satisfies the design of the broadband track-and-hold circuit.

It can be understood that the broadband high-speed tracking and holding circuit in the above embodiment is developed based on a fully differential structure, but the broadband high-speed tracking and holding circuit provided by the present invention may also be developed based on a single-ended structure, and the specific development manner may refer to the fully differential structure, which is not described herein.

In summary, in the broadband high-speed tracking and holding circuit provided by the invention, the input buffer is designed based on the addition of the cascade amplification unit and the feedforward auxiliary amplification unit, so that the nonlinearity of exponential increase of the third harmonic distortion of the common-emitter circuit along with the frequency increase is reduced, the linearity is improved, and the voltage differential swing is increased; the tracking and holding switch module is designed based on the following sampling unit, the clock switch unit and the clamping unit, when the tracking and holding switch module is in a holding state, the base electrode potential is effectively reduced through the base electrode resistance of the sampling switch tube, and the base electrode voltage is fixed to a fixed value through the clamping unit, so that the base error of the sampling switch tube is reduced, the signal establishing time is prolonged, and the signal bandwidth is ensured; an output buffer is designed on the basis of a high-gain operational amplifier unit and a buffer amplifier unit, the high-gain operational amplifier unit is used for realizing the isolation of the input signal and the output signal of the current stage, and the high-gain operational amplifier unit adopts a high-loop gain design, so that the levels of the input ends of the operational amplifier are the same, the accurate voltage-to-current conversion is completed, the larger bandwidth and the higher low-frequency loop gain are ensured, the harmonic distortion is reduced, and the linearity of the rear stage is improved; through the sampling delay adjustable technology, the clock module is designed based on the plurality of clock delay units and the clock selection unit, so that the clock signal with flexibly adjustable delay is obtained, and the improvement of the post-stage quantization and comparison precision is facilitated. Based on the above description, the invention effectively solves the defects existing in the existing high-speed track-hold circuit, has higher use value, and can be applied to the front end of a high-speed high-precision analog-to-digital converter.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims

1. A wideband high speed track and hold circuit, comprising:

2. The wideband high-speed track-and-hold circuit according to claim 1, wherein the input buffer includes a tandem amplification unit and a feedforward auxiliary amplification unit, an input terminal of the tandem amplification unit is connected to the differential input signal, a small signal gain of the differential input signal is increased by the tandem amplification unit, one terminal of the feedforward auxiliary amplification unit is connected to an input terminal of the tandem amplification unit, another terminal of the feedforward auxiliary amplification unit is connected to an output terminal of the tandem amplification unit, and a collector nonlinearity of an input pair transistor of the tandem amplification unit is transmitted to a collector of an output pair transistor of the tandem amplification unit by the feedforward auxiliary amplification unit, so as to compensate an output current of the output pair transistor and suppress a nonlinearity of the output current.

3. The broadband high-speed tracking and holding circuit according to claim 2, wherein the cascade amplifying unit comprises a first NPN transistor, a second NPN transistor, a third NPN transistor, a fourth NPN transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a second capacitor, a first current source and a second current source, wherein a collector of the first NPN transistor is connected to a working voltage through the first resistor in series, a base of the first NPN transistor is connected to a first bias voltage, an emitter of the first NPN transistor is connected to a collector of the second NPN transistor, an emitter of the second NPN transistor is grounded through the second resistor and the first current source in series, a base of the second NPN transistor is connected to a negative terminal of the differential input signal, and a collector of the third NPN transistor is connected to the working voltage through the third resistor in series, a base electrode of the third NPN triode is connected to the first bias voltage, an emitter electrode of the third NPN triode is connected to a collector electrode of the fourth NPN triode, an emitter electrode of the fourth NPN triode is grounded after passing through the fourth resistor and the second current source which are sequentially connected in series, a base electrode of the fourth NPN triode is connected to a positive end of the differential input signal, one end of the first capacitor is connected to a collector electrode of the first NPN triode, the other end of the first capacitor is connected to a collector electrode of the third NPN triode, one end of the second capacitor is connected to an emitter electrode of the second NPN triode, and the other end of the second capacitor is connected to an emitter electrode of the fourth NPN triode, wherein the second NPN triode and the fourth NPN triode are used as input pair transistors of the tandem amplification unit, and the first NPN triode and the third NPN triode are used as output pair transistors of the tandem amplification unit, and the collector electrode of the first NPN triode is used as the positive output terminal of the cascade amplification unit, and the collector electrode of the third NPN triode is used as the negative output terminal of the cascade amplification unit.

4. The broadband high-speed tracking and holding circuit according to claim 3, wherein the feedforward auxiliary amplifying unit comprises a fifth NPN triode, a sixth NPN triode, a fifth resistor, a sixth resistor, a third capacitor and a third current source, wherein a collector of the fifth NPN triode is connected with a collector of the third NPN triode, a base of the fifth NPN triode is connected with a collector of the second NPN triode, an emitter of the fifth NPN triode is grounded after being sequentially connected with the fifth resistor and the third current source in series, a collector of the sixth NPN triode is connected with a collector of the first NPN triode, a base of the sixth NPN triode is connected with a collector of the fourth NPN triode, and an emitter of the sixth NPN triode is connected with a common terminal of the fifth resistor and the third current source after being connected with the sixth resistor in series, one end of the third capacitor is connected with the emitter of the fifth NPN triode, and the other end of the third capacitor is connected with the emitter of the sixth NPN triode.

5. The wideband high speed track-and-hold circuit of claim 1, wherein the track-and-hold switch module comprises a following sample unit, a clock switch unit, and the clamp unit, the input end of the following sampling unit is used as the input end of the track-hold switch module, the input end of the following sampling unit is connected with the output end of the input buffer, the output end of the following sampling unit is used as the output end of the track-hold switch module, the clock switch unit is connected with the following sampling unit, the clock switch unit switches the working state of the following sampling unit under the control of a clock signal, the clock switch unit is connected with a sampling switch tube of the following sampling unit, and under the holding state of the following sampling unit, clamping the base electrode potential of the sampling switch tube of the following sampling unit through the clamping unit.

6. The broadband high-speed track-hold circuit according to claim 5, wherein the follow-sample unit comprises a seventh NPN transistor, an eighth NPN transistor, a ninth NPN transistor, a tenth NPN transistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a fourth capacitor, a fifth capacitor, a sixth capacitor and a seventh capacitor, wherein a collector of the seventh NPN transistor is connected to the working voltage, a base of the seventh NPN transistor is used as an input negative terminal of the track-hold switch module, an emitter of the seventh NPN transistor is connected to an NPN base of the eighth transistor after the seventh resistor, a collector of the eighth NPN transistor is connected to the working voltage after the eighth resistor, an emitter of the eighth NPN transistor is used as an output negative terminal of the track-hold switch module, and a collector of the ninth NPN transistor is connected to the working voltage, a base electrode of the ninth NPN triode is used as an input positive terminal of the tracking and maintaining switch module, an emitter electrode of the ninth NPN triode is connected to a base electrode of the tenth NPN triode after passing through the ninth resistor connected in series, a collector electrode of the tenth NPN triode is connected to the working voltage after passing through the tenth resistor connected in series, an emitter electrode of the tenth NPN triode is used as an output positive terminal of the tracking and maintaining switch module, one end of the fourth capacitor is connected to an emitter electrode of the eighth NPN triode, the other end of the fourth capacitor is grounded, one end of the fifth capacitor is connected to an emitter electrode of the tenth NPN triode, the other end of the fifth capacitor is grounded, one end of the sixth capacitor is connected to a base electrode of the eighth NPN triode, the other end of the sixth capacitor is connected to an emitter electrode of the tenth NPN triode, and one end of the seventh capacitor is connected to an emitter electrode of the eighth NPN triode, the other end of the seventh capacitor is connected with a base electrode of the tenth NPN triode, wherein the eighth NPN triode and the tenth NPN triode are the sampling switch tubes.

7. The wideband high speed track-and-hold circuit of claim 6, wherein the clamping unit comprises a unity gain buffer, an eleventh NPN transistor and a twelfth NPN transistor, the first input end of the unit gain buffer is connected with the emitter of the eighth NPN triode, the first output end of the unit gain buffer is connected with the base electrode of the eleventh NPN triode, the collector of the eleventh NPN triode is connected with the working voltage, the emitter of the eleventh NPN triode is connected with the base of the eighth NPN triode, the second input end of the unit gain buffer is connected with the emitter of the tenth NPN triode, the second output end of the unit gain buffer is connected with the base electrode of the twelfth NPN triode, and the collector of the twelfth NPN triode is connected with the working voltage, and the emitter of the twelfth NPN triode is connected with the base of the tenth NPN triode.

8. The broadband high-speed tracking and holding circuit of claim 7, wherein the clock switch unit comprises a thirteenth NPN transistor, a fourteenth NPN transistor, a fifteenth NPN transistor, a sixteenth NPN transistor, a seventeenth NPN transistor, an eighteenth NPN transistor, a nineteenth NPN transistor, a twentieth NPN transistor, a fourth current source, a fifth current source, a sixth current source and a seventh current source, wherein a collector of the thirteenth NPN transistor is connected to an emitter of the seventh NPN transistor, a base of the thirteenth NPN transistor is connected to a first clock signal, an emitter of the thirteenth NPN transistor is grounded after the fourth NPN current source is connected in series, a collector of the fourteenth NPN transistor is connected to a base of the eighth NPN transistor, a base of the fourteenth NPN transistor is connected to a second clock signal, and an emitter of the fourteenth NPN transistor is connected to an emitter of the thirteenth NPN transistor, a collector of the fifteenth NPN triode is connected to the collector of the fourteenth NPN triode, a base of the fifteenth NPN triode is connected to the base of the fourteenth NPN triode, an emitter of the fifteenth NPN triode is grounded through the fifth current source connected in series, a collector of the sixteenth NPN triode is connected to the emitter of the eighth NPN triode, a base of the sixteenth NPN triode is connected to the base of the thirteenth NPN triode, an emitter of the sixteenth NPN triode is connected to the emitter of the fifteenth NPN triode, a collector of the seventeenth NPN triode is connected to the emitter of the tenth NPN triode, a base of the seventeenth NPN triode is connected to the first clock signal, an emitter of the seventeenth NPN triode is grounded through the sixth current source connected in series, and a collector of the eighteenth NPN triode is connected to the base of the tenth NPN triode, the base electrode of the eighteenth NPN triode is connected with the second clock signal, the emitting electrode of the eighteenth NPN triode is connected with the emitting electrode of the seventeenth NPN triode, the collecting electrode of the nineteenth NPN triode is connected with the collecting electrode of the eighteenth NPN triode, the base electrode of the nineteenth NPN triode is connected with the base electrode of the eighteenth NPN triode, the emitting electrode of the nineteenth NPN triode is grounded after passing through the seventh current source which is connected in series, the collecting electrode of the twentieth NPN triode is connected with the emitting electrode of the ninth NPN triode, the base electrode of the twentieth NPN triode is connected with the base electrode of the seventeenth NPN triode, and the emitting electrode of the twentieth NPN triode is connected with the emitting electrode of the nineteenth NPN triode.

9. The broadband high-speed track-hold circuit according to claim 1, wherein the output buffer comprises a high-gain operational amplifier unit and a buffer amplifier unit, an input terminal of the high-gain operational amplifier unit is connected to an output terminal of the track-hold switch module, an output terminal of the high-gain operational amplifier unit is connected to an input terminal of the buffer amplifier unit, an output terminal of the buffer amplifier unit outputs the sampling signal or the hold signal, in the output buffer, accurate copying of an input signal is performed through the high-gain operational amplifier unit, front and back stages are isolated through the high-gain operational amplifier unit, and the input signal is amplified through the buffer amplifier unit, so that linearity of the input signal is optimized.

10. The broadband high-speed tracking and holding circuit according to claim 9, wherein the high-gain operational amplifier unit comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a twenty-first NPN transistor, a twenty-second NPN transistor, a twenty-third NPN transistor, a twenty-fourth NPN transistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, an eighth current source, a ninth current source, and a tenth current source, wherein a source of the first PMOS transistor is connected to the operating voltage, a gate of the first PMOS transistor is connected to a drain of the first PMOS transistor, a drain of the first PMOS transistor is grounded via the eighth current source connected in series, a source of the second PMOS transistor is connected to the operating voltage, a gate of the second PMOS transistor is connected to the gate of the first PMOS transistor, a source of the third PMOS transistor is connected to the operating voltage, and a gate of the third PMOS transistor is connected to the gate of the first PMOS transistor, a collector of the twenty-first NPN triode is connected to the working voltage through the eleventh resistor in series, a base of the twenty-first NPN triode is connected to the negative output terminal of the tracking and holding switch module, an emitter of the twenty-first NPN triode is grounded through the ninth current source in series, a collector of the twenty-second NPN triode is connected to the drain of the second PMOS transistor through the twelfth resistor in series, an emitter of the second twelve NPN triode is connected to the emitter of the twenty-first NPN triode, a collector of the twenty-third NPN triode is connected to the working voltage through the thirteenth resistor in series, a base of the twenty-third NPN triode is connected to the positive output terminal of the tracking and holding switch module, an emitter of the twenty-third NPN triode is connected to the ground through the tenth current source in series, and a collector of the twenty-fourth NPN is connected to the drain of the third PMOS transistor through the fourteenth resistor in series An emitter of the twenty-fourth NPN triode is connected to an emitter of the twenty-third NPN triode, wherein a base of the twenty-first NPN triode serves as an input negative terminal of the high-gain operational amplifier unit, a base of the twenty-second NPN triode serves as an output negative terminal of the high-gain operational amplifier unit, a base of the twenty-third NPN triode serves as an input positive terminal of the high-gain operational amplifier unit, and a base of the twenty-fourth NPN triode serves as an output positive terminal of the high-gain operational amplifier unit.

11. The broadband high-speed tracking and holding circuit according to claim 10, wherein the buffer amplifying unit comprises a twenty-fifth NPN transistor, a twenty-sixth NPN transistor, a twenty-seventh NPN transistor, a twenty-eighth NPN transistor, a twenty-ninth NPN transistor, a thirty-third NPN transistor, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, a twentieth resistor, an eleventh current source, a twelfth current source, a thirteenth current source, and a fourteenth current source, wherein a collector of the twenty-fifth NPN transistor is connected in series to the fifteenth resistor and then to the operating voltage, a base of the twenty-fifth NPN transistor is connected to the drain of the second PMOS transistor, an emitter of the twenty-fifth NPN transistor is connected in series to the sixteenth resistor and then to the eleventh current source and then to ground, and an emitter of the twenty-fifth NPN transistor is further connected to a base of the twelfth NPN transistor, a collector of the twenty-sixth NPN triode is connected with the working voltage through the seventeenth resistor in series, a base of the twenty-sixth NPN triode is connected with a collector of the twenty-fifth NPN triode, an emitter of the twenty-sixth NPN triode is connected with a collector of the twenty-seventh NPN triode, a collector of the twenty-seventh NPN triode is connected with a base of the twenty-seventh NPN triode, an emitter of the twenty-seventh NPN triode is connected with the ground through the twelfth current source in series, a collector of the twenty-eighth NPN triode is connected with the working voltage through the eighteenth resistor in series, a base of the twenty-eighteenth NPN triode is connected with a drain of the third NPN transistor, an emitter of the twenty-eighth NPN triode is connected with the nineteenth resistor and the thirteenth current source in series in sequence and then connected with the ground, and an emitter of the twenty-eighth NPN triode is further connected with a base of the twenty-fourteenth NPN triode, the collector of the twenty-ninth NPN triode is connected with the working voltage through the twentieth resistor in series, the base of the twenty-ninth NPN triode is connected with the collector of the twenty-eighteenth NPN triode, the emitter of the twenty-ninth NPN triode is connected with the collector of the thirty-ninth NPN triode, the collector of the thirty-ninth NPN triode is connected with the base of the thirty-fifth NPN triode, and the emitter of the thirty-fifth NPN triode is connected with the ground through the fourteenth current source in series, wherein the emitter of the twenty-seventh NPN triode serves as the negative output terminal of the buffer amplification unit, and the emitter of the thirty-fifth NPN triode serves as the positive output terminal of the buffer amplification unit.

12. The wideband high speed track and hold circuit of claim 1 wherein the clock module outputs a delay adjustable clock signal to the track and hold switch module under selective control of a control signal.

13. The broadband high-speed track-and-hold circuit according to claim 12, wherein the clock module comprises a first clock delay unit, a second clock delay unit, a third clock delay unit, a fourth clock delay unit, a first clock selection unit, a second clock selection unit, and a third clock selection unit, wherein a clock input signal is respectively connected to an input terminal of the first clock delay unit and a first input terminal of the third clock selection unit, an output terminal of the first clock delay unit is respectively connected to an input terminal of the second clock delay unit and a first input terminal of the second clock selection unit, an output terminal of the second clock delay unit is respectively connected to an input terminal of the third clock delay unit and a second input terminal of the first clock selection unit, and an output terminal of the third clock delay unit is connected to an input terminal of the fourth clock delay unit, the output end of the fourth clock delay unit is connected with the first input end of the first clock selection unit, the third input end of the first clock selection unit is connected with a first control signal, the output end of the first clock selection unit is connected with the second input end of the second clock selection unit, the third input end of the second clock selection unit is connected with a second control signal, the output end of the second clock selection unit is connected with the second input end of the third clock selection unit, the third input end of the third clock selection unit is connected with a third control signal, and the output end of the third clock selection unit outputs the clock signal.