CN114221647A

CN114221647A - Self-adaptive driving circuit, IO interface circuit, chip and electronic equipment

Info

Publication number: CN114221647A
Application number: CN202111490203.XA
Authority: CN
Inventors: 张阳; 刘勇江
Original assignee: Chengdu Haiguang Microelectronics Technology Co Ltd
Current assignee: Chengdu Haiguang Microelectronics Technology Co Ltd
Priority date: 2021-12-08
Filing date: 2021-12-08
Publication date: 2022-03-22

Abstract

The application relates to a self-adaptive driving circuit, an IO interface circuit, a chip and electronic equipment, and belongs to the technical field of electronic circuits. The adaptive driving circuit comprises: a driving main circuit and a voltage dividing circuit; a driving main circuit for outputting a driving signal; the first end of the voltage division circuit is used for being connected with a first power supply, the second end of the voltage division circuit is grounded, the output end of the voltage division circuit is connected with the driving main body circuit, and the voltage division circuit is used for outputting a control power supply of an output transistor in the driving main body circuit, so that the pull-up capability and the pull-down capability of the driving main body circuit are consistent under different PVT conditions. The pull-up capability and the pull-down capability of the driving main body circuit are consistent under different PVT conditions, and compared with a traditional driving circuit, the maximum on-resistance value of the PMOS tube can be reduced, and further the layout area of the whole driving circuit can be reduced.

Description

Self-adaptive driving circuit, IO interface circuit, chip and electronic equipment

Technical Field

The application belongs to the technical field of electronic circuits, and particularly relates to a self-adaptive driving circuit, an IO interface circuit, a chip and electronic equipment.

Background

An IO (Input Output) interface circuit is widely applied to various IO interface chips (e.g., processors, memories, etc.), and whether the IO interface circuit works normally directly determines the availability of the whole chip. The driving circuit is used as an important component of the IO interface circuit, and the quality of an output signal of the driving circuit directly determines the quality of the output signal of the IO interface circuit.

The voltage resistance of a MOS (Metal Oxide Semiconductor) transistor decreases with the progress of Semiconductor processes, and therefore a cascode MOS transistor structure is usually used to solve the problem of voltage resistance of the device. The conventional driving circuit is shown in fig. 1, and includes two independent power supplies of VDDH and VDDL, the maximum voltage difference that all MOS devices can bear is VDDL, the control signal pre _ pgate is a square wave control signal of VDDL to VDDH, and the control signal pre _ ngate is a square wave control signal of 0 to VDDL. The resistor R1 and PMOS tubes P1 and P2 form a drive pull-up branch, and the resistor R2 and NMOS tubes N1 and N2 form a drive pull-down branch.

When the PAD signal is switched (from low level to high level or from high level to low level), the MOS transistor operates as a switching transistor in a deep linear region due to the presence of the resistors R1 and R2. The pull-up resistance at the final PAD is the sum of R1 and the on-resistance of MOS transistors P1, P2 operating in the deep linear region. The pull-down resistance at the PAD is the sum of R2 and the on-resistances of MOS transistors N1 and N2 working in the deep linear region. When the P1 tube is conducted, the | VGS | voltage is VDDH-VDDL, the | VGS | voltage of the P2 tube is vp1-VDDL, the | VGS | voltage of the N1 tube is VDDL-vn1, the | VGS | voltage of the N2 tube is VDDL, wherein vp1 is the voltage of the source end of the P2 tube, vp1 is approximately equal to VDDH, vn1 is the voltage of the source end of the N1 tube, and vn1 is approximately equal to 0.

Since VDDH and VDDL are different power supplies, under different PVT (Process Voltage Temperature, combination of Process, Voltage and Temperature), the gate-source Voltage of PMOS transistor is (VDDH min-VDDMMax) to (VDDH max-VDDMMLmin), and the gate-source Voltage of NMOS transistor is VDDMmin-VDDMMax. Therefore, the gate-source voltage range of the NMOS transistor is (VDDMMax-VDDMmin), and the gate-source voltage range of the PMOS transistor is (VDDhmax-VDDVHmin + VDDMMax-VDDMmin). The pull-up capability of the drive circuit for driving the pull-up branch circuit is not matched with the pull-down capability of the drive circuit for driving the pull-down branch circuit under different PVT conditions, which greatly deteriorates the quality of the output signal of the drive circuit. In addition, because the influence of the gate-source voltage of the PMOS transistor is large under different PVT conditions, the deviation of the output on-resistance of the drive pull-up branch is large under different PVT conditions, and especially when the gate-source voltage difference of the PMOS transistor is small, if the maximum on-resistance of the PMOS transistor meets the design requirement, the area of the PMOS transistor needs to be increased, so that the layout area of the whole drive circuit is increased.

Disclosure of Invention

In view of this, an object of the present application is to provide an adaptive driving circuit, an IO interface circuit, a chip, and an electronic device, so as to solve the problems that the pull-up capability and the pull-down capability of the conventional driving circuit are not matched under different PVT conditions, and the output on-resistance of the pull-up branch is driven to have large deviation under different PVT conditions.

The embodiment of the application is realized as follows:

in a first aspect, an embodiment of the present application provides an adaptive driving circuit, including: a driving main circuit and a voltage dividing circuit; a driving main circuit for outputting a driving signal; the first end of the voltage division circuit is used for being connected with a first power supply, the second end of the voltage division circuit is grounded, the output end of the voltage division circuit is connected with the driving main body circuit, and the voltage division circuit is used for outputting a control power supply of an output transistor in the driving main body circuit, so that the pull-up capability and the pull-down capability of the driving main body circuit are consistent under different PVT conditions. In the embodiment of the application, a self-adaptive adjustment technology is adopted, a voltage division circuit is used for dividing a first power supply (such as VDDH), the voltage obtained through voltage division is used as a control power supply of an output transistor in a driving main body circuit, the function of dynamically adjusting the control power supply of the output transistor in the driving main body circuit along with the VDDH is achieved, the control power supply can dynamically change along with the VDDH and is affected by different PVT conditions consistently, therefore, the pull-up capability and the pull-down capability of the driving main body circuit can be kept consistent under different PVT conditions, the maximum on-resistance value of a PMOS (P-channel metal oxide semiconductor) tube can be reduced, and the layout area of the whole driving circuit can be reduced.

With reference to one possible implementation manner of the embodiment of the first aspect, the voltage dividing circuit includes: a voltage division basic circuit and an operational amplifier; the first end of the voltage division basic circuit is used for being connected with the first power supply, the second end of the voltage division basic circuit is grounded, and the voltage division basic circuit is used for outputting an internal power supply; the first input end of the operational amplifier is connected with the output end of the voltage division basic circuit, the second input end of the operational amplifier is connected with the output end of the operational amplifier, and the output end of the operational amplifier is used as a control power supply of an output transistor in the driving main body circuit. In the embodiment of the present application, the operational amplifier is equivalent to a unity gain buffer (buffer), and by adding a unity gain, it can provide sufficient driving capability to enhance the driving capability of the voltage division basic circuit.

With reference to one possible implementation manner of the embodiment of the first aspect, the voltage dividing basic circuit includes: a first current limiting device, a second current limiting device; the first end of the first current limiting device is connected with the first power supply, the second end of the first current limiting device is grounded through the second current limiting device, the second end of the first current limiting device is further connected with the first input end of the operational amplifier, and the second end of the first current limiting device is the output end of the voltage division basic circuit. In the embodiment of the application, the purpose of voltage division can be realized by adopting the common components such as the first current limiting device and the second current limiting device, and the cost can be saved while the purpose is realized.

With reference to one possible implementation manner of the embodiment of the first aspect, a resistance value of the first current limiting device is consistent with a resistance value of the second current limiting device. In the embodiment of the present application, the first current limiting device and the second current limiting device have the same resistance value, so that the divided voltage is equal to 0.5 × VDDH, which is the first power supply.

With reference to one possible implementation manner of the embodiment of the first aspect, the voltage dividing basic circuit includes a first output end and a second output end, where the first output end is configured to output a first internal power source, and the second output end is configured to output a second internal power source; correspondingly, the operational amplifier comprises a first operational amplifier and a second operational amplifier, wherein a first input end of the first operational amplifier is connected with the first output end, a second input end of the first operational amplifier is connected with an output end of the first operational amplifier, and an output end of the first operational amplifier is used as a control power supply for driving an output transistor in a pull-up branch in the driving main body circuit; the first input end of the second operational amplifier is connected with the second output end, the second input end of the second operational amplifier is connected with the output end of the second operational amplifier, and the output end of the second operational amplifier is used as a control power supply of an output transistor in a drive pull-down branch in the drive main body circuit. In the embodiment of the application, two internal power supplies are output, wherein one internal power supply is used as a control power supply for driving the output transistor in the pull-up branch circuit, and the other internal power supply is used as a control power supply for driving the output transistor in the pull-down branch circuit, so that the body effect influence of the output transistor can be eliminated.

With reference to one possible implementation manner of the embodiment of the first aspect, the voltage dividing basic circuit includes: a first current limiting device, a second current limiting device, a third current limiting device; the first end of the first current limiting device is connected with the first power supply, the second end of the first current limiting device is connected with the first end of the second current limiting device, the second end of the second current limiting device is grounded through the third current limiting device, the second end of the first current limiting device is further connected with the first input end of the second operational amplifier, the second end of the first current limiting device is the second output end, the second end of the second current limiting device is further connected with the first input end of the first operational amplifier, and the second end of the second current limiting device is the first output end. In the embodiment of the application, the purpose of voltage division can be realized by adopting the first current limiting device, the second current limiting device and the third current limiting device, and the voltage divider has the advantages of simple structure and easiness in realization.

With reference to one possible implementation manner of the embodiment of the first aspect, the voltage dividing basic circuit includes: the current limiting device comprises a first current limiting device, a second current limiting device, a third current limiting device and a fourth current limiting device; the first end of the first current limiting device is connected with the first power supply, the second end of the first current limiting device is grounded through the second current limiting device, the second end of the first current limiting device is also connected with the first input end of the first operational amplifier, and the second end of the first current limiting device is the first output end; the first end of the third current limiting device is connected with the first power supply, the second end of the third current limiting device is grounded through the fourth current limiting device, the second end of the third current limiting device is further connected with the first input end of the second operational amplifier, and the second end of the third current limiting device is the second output end. In the embodiment of the application, two voltage division branches are formed by 4 current limiting devices to obtain two internal power supplies, so that the adjustment of each internal power supply is more flexible.

With reference to a possible implementation manner of the embodiment of the first aspect, the current limiting device in the voltage division basic circuit includes a current limiting resistor or an MOS transistor, and if the current limiting device is an MOS transistor, a drain and a gate of the MOS transistor jointly serve as a connection terminal. In the embodiment of the application, a common current-limiting resistor or a common MOS (metal oxide semiconductor) tube is adopted to form the voltage division circuit, so that the purpose of the invention is realized, and the design cost of the circuit can be saved.

With reference to one possible implementation manner of the embodiment of the first aspect, the magnitude of the control power output by the first operational amplifier as the output transistor in the pull-up driving branch is 0.5 × VDDH-V1, the magnitude of the control power output by the second operational amplifier as the output transistor in the pull-down driving branch is 0.5 × VDDH + V2, VDDH is the first power, V1 is a first preset threshold, and V2 is a second preset threshold. In the embodiment of the application, 2 power supplies with specific sizes are output to eliminate the influence of the body effect of the output transistor, so that the quality of signals output by the driving circuit can be further improved.

In a second aspect, an embodiment of the present application further provides an IO interface circuit, including a control logic circuit and an adaptive driving circuit provided as in the foregoing first aspect and/or in combination with any one of the possible implementations of the first aspect, where the control logic circuit is configured to provide a driving signal for the adaptive driving circuit.

In a third aspect, an embodiment of the present application further provides an IO interface chip integrated with the IO interface circuit provided in the second aspect.

In a fourth aspect, an embodiment of the present application further provides an electronic device, including a body and the adaptive driving circuit provided in the foregoing first aspect and/or in combination with any possible implementation manner of the first aspect, or the IO interface circuit provided in the foregoing second aspect.

Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the embodiments of the application. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and drawings.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts. The foregoing and other objects, features and advantages of the application will be apparent from the accompanying drawings. Like reference numerals refer to like parts throughout the drawings. The drawings are not intended to be to scale as practical, emphasis instead being placed upon illustrating the subject matter of the present application.

Fig. 1 is a schematic circuit diagram of a conventional driving circuit.

Fig. 2 shows a schematic structural diagram of an adaptive driving circuit provided in an embodiment of the present application.

Fig. 3 shows a schematic structural diagram of another adaptive driving circuit provided in an embodiment of the present application.

Fig. 4 shows a schematic circuit diagram of an adaptive driving circuit according to an embodiment of the present application.

Fig. 5 shows a schematic structural diagram of another adaptive driving circuit provided in an embodiment of the present application.

Fig. 6 shows a schematic circuit diagram of another adaptive driving circuit provided in an embodiment of the present application.

Fig. 7 shows a schematic circuit diagram of another adaptive driving circuit provided in an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, relational terms such as "first," "second," and the like may be used solely in the description herein to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, article, or apparatus that comprises the element.

Further, the term "and/or" in the present application is only one kind of association relationship describing the associated object, and means that three kinds of relationships may exist, for example, a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone.

In the description of the present application, it is also to be noted that, unless otherwise explicitly specified or limited, the terms "connected" and "connected" are to be interpreted broadly, e.g., as meaning either a fixed connection, a detachable connection, or an integral connection; or may be an electrical connection; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.

In view of the problem that the pull-up capability of the pull-up branch circuit and the pull-down capability of the pull-down branch circuit in the conventional driving circuit are not matched under different PVT (Process Voltage Temperature, combination of Process Voltage and Temperature) conditions, which may greatly deteriorate the quality of the output signal of the driving circuit, and the problem that the output on-resistance of the pull-up branch circuit has large deviation under different PVT conditions, in order to make the maximum on-resistance of the PMOS transistor meet the design requirement when the gate-source Voltage difference of the PMOS transistor is small, the area of the PMOS transistor needs to be increased, so that the layout area of the whole driving circuit is increased. The embodiment of the application provides a self-adaptive driving circuit, which adopts a self-adaptive adjusting technology, utilizes a voltage division circuit to divide a first power supply (such as VDDH), and uses the voltage obtained by voltage division as a control power supply for driving an output transistor in a main body circuit, so as to realize the dynamic adjustment function of the control power supply for driving the output transistor in the main body circuit along with the power supply VDDH, not only can the pull-up capability and the pull-down capability of the main body circuit be kept consistent under different PVT conditions, but also the maximum on-resistance value of a PMOS (P-channel metal oxide semiconductor) tube can be reduced, and thus the layout area of the whole driving circuit can be reduced.

For ease of understanding, the adaptive driving circuit provided in the embodiment of the present application will be described below with reference to fig. 2. The self-adaptive driving circuit comprises a voltage division circuit and a driving main body circuit.

The driving main body circuit is used for outputting driving signals and comprises a PMOS tube P1, a PMOS tube P2, a resistor R1, an NMOS tube N1, an NMOS tube N2 and a resistor R2. The resistor R1, the PMOS tubes P1 and P2 form a drive pull-up branch, the resistor R2, the NMOS tubes N1 and N2 form a drive pull-down branch, and the resistance value of the resistor R1 is consistent with that of the resistor R2. The transistors P2 and N1 are output transistors in the main body circuit. Pre _ pgate in fig. 2 is a square wave control signal of VDDL _1 to VDDH, and pre _ ngate is a square wave control signal of 0 to VDDL _ 1.

The control power supply of the output transistor in the driving main body circuit is not a VDDL power supply which is independent from VDDH, but is a power supply VDDL _1 obtained by dividing a first power supply (such as VDDH), under different PVT conditions, VDDL _1 can dynamically change along with the power supply VDDH, and the influence of different PVT conditions is consistent.

The gate-source voltage | VGS | when the P1 tube is conducted is VDDH-VDDL _1, the | VGS | voltage of the P2 tube is vp1-VDDL _1, the | VGS | voltage of the N1 tube is VDDL _1-vn1, the | VGS | voltage of the N2 tube is VDDL _1, wherein vp1 is the voltage of the source end of the P2 tube, vp1 is approximately equal to VDDH, vn1 is the voltage of the source end of the N1 tube, and vn1 is approximately equal to 0. Assuming that VDDL _1 is 0.5 × VDDH, so that the gate-source voltage | VGS | of the PMOS transistor is 0.5 × VDDHmin to 0.5 × VDDHmax, and the gate-source voltage | VGS | of the NMOS transistor is also 0.5 × VDDHmin to 0.5 VDDHmax, since the gate-source voltage | VGS | of the NMOS transistor is equal to the gate-source voltage | VGS | of the PMOS transistor, the resistance values of the on-resistances of the NMOS transistor and the PMOS transistor are equal to each other under different PVT conditions, that is, the resistance values of the on-resistances of the pull-up branch and the pull-down branch are equal to each other under different PVT conditions, so that the pull-up capability and the pull-down capability of the driving main circuit are equal to each other under different PVT conditions. The on-resistance value of the NMOS tube is equal to that of the PMOS tube under different PVT conditions, so that the pull-up capability and the pull-down capability of the driving circuit are the same, and the quality of output signals of the driving circuit is improved.

The on-resistance formula of the MOS tube working in the linear region is as follows:

mu is the carrier mobility of the MOS transistor, Cox is the capacitance of the MOS gate oxide layer, W is the channel width of the MOS transistor, L is the channel length of the MOS transistor, | VGS | is the gate-source voltage of the MOS transistor, and VTH is the threshold voltage of the MOS transistor.

Meanwhile, the deviation of the conduction resistance of the PMOS tube is small relative to the traditional drive circuit under different PVT conditions, relative to the traditional drive circuit, the minimum grid source voltage of the PMOS tube is changed from (VDDHmin-VDDMax) to 0.5 VDDDHmin, relative to the traditional drive circuit, the grid source voltage of the PMOS tube of the drive main body circuit is larger, further the maximum conduction resistance value of the PMOS tube is smaller relative to the traditional drive circuit, the effect that the maximum output resistance value of the drive pull-up branch circuit is the same as that of the drive pull-up branch circuit of the traditional drive circuit is obtained, and the layout area of the drive circuit can be reduced. It should be noted that, under different PVT conditions, the influence on the power supply voltage is large, and the fluctuation range thereof can reach 10%, that is, the voltage values under different PVT conditions can fluctuate within 10% of the standard value, for example, assuming that the standard value is 2, the maximum value can be 2.2, and the minimum value is 1.8.

For better understanding, the present application is larger than the gate-source voltage of the PMOS transistor in the conventional driving circuit, and the following description is given by way of example, if VDDH is 4, and VDDL is also 0.5VDDH, then VDDHmin is 4 0.9 is 3.6, VDDLmax is 2.1 is 2.2, and the minimum gate-source voltage VDDHmin-VDDLmax of the PMOS transistor in the conventional driving circuit is 3.6-2.2 is 1.4; and the minimum grid source voltage of the PMOS tube in this application is 0.5 VDDHmin-0.5X 3.6-1.8, and for traditional drive circuit, the grid source voltage of the PMOS tube of the drive main body circuit of this application is bigger, and then makes the maximum on resistance value of the PMOS tube smaller than that of the traditional drive circuit.

The first terminal of the voltage division circuit is used for connecting a first power supply VDDH, the second terminal of the voltage division circuit is grounded, the output terminal of the voltage division circuit is connected with the driving main body circuit, and the voltage division circuit is used for outputting control power supplies of output transistors (a transistor P2 and a transistor N1) in the driving main body circuit.

In an alternative embodiment, a voltage divider circuit includes: the circuit diagram of the voltage division basic circuit and the operational amplifier is shown in fig. 3. The first end of the voltage division basic circuit is used for being connected with a first power supply, the second end of the voltage division basic circuit is grounded, and the voltage division basic circuit is used for outputting an internal power supply. The first input end of the operational amplifier is connected with the output end of the voltage division basic circuit, the second input end of the operational amplifier is connected with the output end of the operational amplifier, and the output end of the operational amplifier is used as a control power supply for driving an output transistor in the main body circuit. Optionally, the first input terminal of the operational amplifier is a non-inverting input terminal, and the second input terminal of the operational amplifier is an inverting input terminal. The operational amplifier of the above connection mode is equivalent to a unity gain buffer circuit, and by further adding a unity gain buffer circuit, it can provide sufficient driving capability to enhance the driving capability of the voltage division basic circuit.

In one embodiment, when the voltage-dividing basic circuit includes only one output terminal, the voltage-dividing basic circuit includes: a first current limiting device (as represented by R3), a second current limiting device (as represented by R4), and a schematic circuit diagram thereof as shown in fig. 4. The first end of the first current limiting device is connected with a first power supply, the second end of the first current limiting device is grounded through a second current limiting device, the second end of the first current limiting device is further connected with the first input end of the operational amplifier, and the second end of the first current limiting device is the output end of the voltage division basic circuit. Optionally, the resistance of the first current limiting device is identical to the resistance of the second current limiting device, such that VDDL _1 is 0.5 × VDDH.

Considering that the voltage of vp1 is not completely equal to VDDH, and the voltage of vn1 is not completely equal to 0, that is, the voltages of the source terminal and the substrate terminal of the P2 transistor are not equal to the voltages of the source terminal and the substrate terminal of the N1 transistor, the threshold voltages of the P2 transistor and the N1 transistor will increase due to the MOS body effect, and the conduction resistances of the P2 transistor and the N1 transistor will increase. To counteract the effect of the threshold voltage on the on-resistance, 2 internal power supplies VDDL _1 and VDDL _2 may be generated by a voltage divider circuit, where VDDL _1 is equal to (0.5 × VDDH-V1) and VDDL _2 is equal to (0.5 × VDDH + V2) to eliminate the bulk effect.

Wherein V1 is a first preset threshold, V2 is a second preset threshold, optionally, V1 is VDDH-vp1+ Δ Vth, V2 is vn1+ Δ Vth, Δ Vth is a threshold voltage variation, where vp1 is the voltage of the source terminal of P2 transistor, vn1 is the voltage of the source terminal of N1 transistor,

gamma is the bulk coefficient, VSB is the source-to-substrate voltage difference, phi_F＝(kT/q)ln(N_sub/ni), k is Boltzmann constant, T is temperature, q is charge, N is_subIs the doping concentration of the substrate and ni is the intrinsic carrier concentration. Since Δ Vth has a small and negligible value, V1 is VDDH-vp1 and V2 is vn1 in one embodiment.

In another embodiment, the voltage division basic circuit includes a first output terminal for outputting the first internal power (VDDL _1) and a second output terminal for outputting the second internal power (VDDL _2), and the op-amp includes a first op-amp (e.g., buffer1) and a second op-amp (e.g., buffer2), and the circuit diagram thereof is as shown in fig. 5. The first input end of the first operational amplifier is connected with the first output end, the second input end of the first operational amplifier is connected with the output end of the first operational amplifier, and the output end of the first operational amplifier is used as a control power supply for driving an output transistor (P2) in a pull-up branch in the main body circuit. The first input end of the second operational amplifier is connected with the second output end, the second input end of the second operational amplifier is connected with the output end of the second operational amplifier, and the output end of the second operational amplifier is used as a control power supply for driving an output transistor (N1) in a pull-down branch in the main body circuit.

When the voltage-dividing basic circuit includes 2 output terminals, in one embodiment, the voltage-dividing basic circuit includes: a first current limiting device (as represented by R3), a second current limiting device (as represented by R4), and a third current limiting device (as represented by R5), and a circuit diagram thereof is shown in fig. 6. The first end of the first current limiting device is connected with a first power supply, the second end of the first current limiting device is connected with the first end of the second current limiting device, the second end of the second current limiting device is grounded through a third current limiting device, the second end of the first current limiting device is further connected with the first input end of the second operation amplifier, the second end of the first current limiting device is a second output end, the second end of the second current limiting device is further connected with the first input end of the first operation amplifier, and the second end of the second current limiting device is a first output end.

In another embodiment, when the voltage division basic circuit includes 2 output terminals, the voltage division basic circuit includes: the voltage division basic circuit includes: a first current limiting device (as represented by R3), a second current limiting device (as represented by R4), a third current limiting device (as represented by R5), and a fourth current limiting device (as represented by R6), the circuit diagram of which is shown in fig. 7. The first end of the first current limiting device is connected with a first power supply, the second end of the first current limiting device is grounded through a second current limiting device, the second end of the first current limiting device is also connected with the first input end of the first operational amplifier, and the second end of the first current limiting device is a first output end; the first end of the third current limiting device is connected with the first power supply, the second end of the third current limiting device is grounded through the fourth current limiting device, the second end of the third current limiting device is further connected with the first input end of the second operational amplifier, and the second end of the third current limiting device is the second output end.

The current limiting device in the voltage division basic circuit may be a resistor, a MOS transistor, a diode, or the like. If the current limiting device is an MOS tube, the drain electrode and the grid electrode of the MOS tube are jointly used as one connecting terminal, and the source electrode of the MOS tube is used as the other connecting terminal. The MOS tube can be an NMOS tube or a PMOS tube, when the MOS tube is the NMOS tube, the drain electrode and the grid electrode of the MOS tube are grounded, the source electrode of the MOS tube is connected with a first power supply, when the MOS tube is the PMOS tube, the drain electrode and the grid electrode of the MOS tube are connected with the first power supply, and the source electrode of the MOS tube is grounded.

It should be noted that, in an alternative embodiment, the voltage dividing circuit may only include a voltage dividing basic circuit. At this time, the voltage dividing circuit is equivalent to the voltage dividing base circuit, and therefore the above voltage dividing circuit including the voltage dividing base circuit and the op amp cannot be understood as a limitation of the present application.

Based on the same inventive concept, the embodiment of the present application further provides an IO interface circuit, which includes a control logic circuit and the adaptive driving circuit. The control logic circuit is used for providing a driving signal for the self-adaptive driving circuit. For example, the control logic is configured to provide a pre _ pgate drive signal and a pre _ ngate drive signal to the adaptive drive circuit of fig. 2.

The implementation principle and the generated technical effect of the adaptive driving circuit provided by the embodiment of the IO interface circuit are the same as those of the foregoing adaptive driving circuit embodiment, and for a brief description, reference may be made to corresponding contents in the foregoing adaptive driving circuit embodiment for a part not mentioned in the embodiment of the IO interface circuit.

Based on the same inventive concept, the embodiment of the application also provides an IO interface chip, and the IO interface chip is integrated with the self-adaptive driving circuit. The IO interface chip may be various IO interface chips commonly used at present, such as a memory, a processor, and the like.

The Processor may be a general-purpose Processor, including a Central Processing Unit (CPU), a Network Processor (NP), and the like; it may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), or a Field Programmable Gate Array (FPGA). A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

The Memory may be, but is not limited to, a Random Access Memory (RAM), a Read Only Memory (ROM), a Programmable Read-Only Memory (PROM), an Erasable Read-Only Memory (EPROM), an electrically Erasable Read-Only Memory (EEPROM), and the like.

The implementation principle and the generated technical effect of the adaptive driving circuit provided by the embodiment of the IO interface chip are the same as those of the foregoing adaptive driving circuit embodiment, and for brief description, reference may be made to corresponding contents in the foregoing adaptive driving circuit embodiment for parts of the embodiment of the IO interface chip that are not mentioned.

Based on the same inventive concept, the embodiment of the present application further provides an electronic device, which includes a body and the IO interface circuit or the IO interface chip. The electronic device may be any electronic device including an IO interface circuit or an IO interface chip, for example, a mobile phone, a tablet, a computer, a server, and the like.

The adaptive driving circuit provided in the embodiment of the electronic device has the same implementation principle and technical effect as those of the foregoing adaptive driving circuit embodiment, and for brevity of description of parts of the embodiment of the electronic device that are not mentioned, reference may be made to the corresponding contents in the foregoing adaptive driving circuit embodiment.

It should be noted that, in the present specification, the embodiments are all described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. An adaptive drive circuit, comprising:

a driving main circuit for outputting a driving signal;

the first end of the voltage division circuit is used for being connected with a first power supply, the second end of the voltage division circuit is grounded, the output end of the voltage division circuit is connected with the driving main body circuit, and the voltage division circuit is used for outputting a control power supply of an output transistor in the driving main body circuit, so that the pull-up capacity and the pull-down capacity of the driving main body circuit are consistent under different PVT conditions.

2. The adaptive drive circuit according to claim 1, wherein the voltage divider circuit comprises:

the first end of the voltage division basic circuit is used for being connected with the first power supply, the second end of the voltage division basic circuit is grounded, and the voltage division basic circuit is used for outputting an internal power supply;

and a first input end of the operational amplifier is connected with an output end of the voltage division basic circuit, a second input end of the operational amplifier is connected with an output end of the operational amplifier, and the output end of the operational amplifier is used as a control power supply of an output transistor in the driving main body circuit.

3. The adaptive drive circuit according to claim 2, wherein the voltage division base circuit comprises: a first current limiting device, a second current limiting device;

the first end of the first current limiting device is connected with the first power supply, the second end of the first current limiting device is grounded through the second current limiting device, the second end of the first current limiting device is further connected with the first input end of the operational amplifier, and the second end of the first current limiting device is the output end of the voltage division basic circuit.

4. The adaptive driving circuit according to claim 2, wherein the voltage dividing basic circuit comprises a first output terminal for outputting a first internal power supply, a second output terminal for outputting a second internal power supply; accordingly, the number of the first and second electrodes,

the operational amplifier comprises a first operational amplifier and a second operational amplifier, wherein a first input end of the first operational amplifier is connected with a first output end, a second input end of the first operational amplifier is connected with an output end of the first operational amplifier, and an output end of the first operational amplifier is used as a control power supply for driving an output transistor in a pull-up branch in the driving main body circuit;

the first input end of the second operational amplifier is connected with the second output end, the second input end of the second operational amplifier is connected with the output end of the second operational amplifier, and the output end of the second operational amplifier is used as a control power supply of an output transistor in a drive pull-down branch in the drive main body circuit.

5. The adaptive drive circuit according to claim 4, wherein the voltage division base circuit comprises:

a first current limiting device, a second current limiting device, a third current limiting device;

the first end of the first current limiting device is connected with the first power supply, the second end of the first current limiting device is connected with the first end of the second current limiting device, the second end of the second current limiting device is grounded through the third current limiting device, the second end of the first current limiting device is further connected with the first input end of the second operational amplifier, the second end of the first current limiting device is the second output end, the second end of the second current limiting device is further connected with the first input end of the first operational amplifier, and the second end of the second current limiting device is the first output end.

6. The adaptive drive circuit according to claim 4, wherein the voltage division base circuit comprises:

the first end of the first current limiting device is connected with the first power supply, the second end of the first current limiting device is grounded through the second current limiting device, the second end of the first current limiting device is also connected with the first input end of the first operational amplifier, and the second end of the first current limiting device is the first output end;

the first end of the third current limiting device is connected with the first power supply, the second end of the third current limiting device is grounded through the fourth current limiting device, the second end of the third current limiting device is also connected with the first input end of the second operational amplifier, and the second end of the third current limiting device is the second output end.

7. The adaptive driving circuit according to claim 4, wherein the first operational amplifier outputs a control power supply of 0.5 VDDH-V1 as the output transistor in the pull-up driving branch, the second operational amplifier outputs a control power supply of 0.5VDDH + V2 as the output transistor in the pull-down driving branch, VDDH is the first power supply, V1 is the first predetermined threshold, and V2 is the second predetermined threshold.

8. An IO interface circuit comprising a control logic circuit and an adaptive drive circuit as claimed in any one of claims 1 to 7, the control logic circuit being arranged to provide a drive signal to the adaptive drive circuit.

9. An IO interface chip incorporating the IO interface circuit of claim 8.

10. An electronic device comprising a body and an IO interface circuit according to claim 8, or an IO interface chip according to claim 9.