CN114220818A - Erasable memory and manufacturing method thereof - Google Patents
Erasable memory and manufacturing method thereof Download PDFInfo
- Publication number
- CN114220818A CN114220818A CN202111525709.XA CN202111525709A CN114220818A CN 114220818 A CN114220818 A CN 114220818A CN 202111525709 A CN202111525709 A CN 202111525709A CN 114220818 A CN114220818 A CN 114220818A
- Authority
- CN
- China
- Prior art keywords
- metal oxide
- heterojunction
- layer
- oxide layer
- top surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
Abstract
The invention provides an erasable memory, which comprises a substrate, a barrier layer, a first heterojunction, a second heterojunction, a tunneling layer, a channel layer, a source electrode and a drain electrode, wherein the barrier layer is arranged on the top surface of the substrate; the first heterojunction and the second heterojunction have the characteristic of unidirectional conducting charges, and are respectively used for data writing operation and data erasing operation of the erasable memory; the tunneling layer comprises a horizontal part and a vertical part, and the vertical part is used for separating the first heterojunction and the second heterojunction so as to avoid the conduction of transverse charges of the first heterojunction and the second heterojunction; the channel layer is used for the migration of charges. The two heterojunction are respectively used as a data writing channel and a data erasing channel of the erasable memory, so that the data writing channel and the data erasing channel of the erasable memory are more stable and symmetrical, the data erasing speed and the data writing speed are improved, and the dynamic power consumption is reduced. The invention also provides a manufacturing method of the erasable memory.
Description
Technical Field
The invention relates to the field of erasable memories, in particular to an erasable memory and a manufacturing method thereof.
Background
Today's mainstream storage technologies fall into two categories: volatile memory technology and non-volatile memory technology. The volatile rewritable memory mainly includes static random access memory and dynamic random access memory. The volatile erasable memory has nanosecond writing speed, but the data retention capacity is only millisecond level, so that the volatile erasable memory can be only used in limited storage fields such as cache. For non-volatile memory technologies, such as flash memory technology, the data retention capacity can reach 10 years, however, the relatively slow write operation greatly limits the application of the technology in the cache field. For flash memory technology, the flash memory has a low erasing speed due to the contradiction between the thickness reduction of the tunneling oxide layer and the charge holding capacity. At the same time, the charge trapping layer shares a portion of the voltage, which results in an increase in the erase voltage. On the other hand, in order to increase the charge retention, an insulating medium rich in deep level defects is used as a trapping layer, which results in that charges are difficult to erase from the trapping layer and the erasing speed is slow.
The invention patent with publication number CN100570897C discloses a method for increasing data erasing speed of a non-volatile erasable and writable memory, which includes a substrate, a source and a drain formed in the substrate, and a gate formed above the substrate, wherein three stacked insulating layers are further provided between the gate and the substrate, a middle layer is used for trapping charges, and two insulating layers are used for locking the charges in the middle layer, the method loads a negative voltage on the gate during data erasing, and simultaneously loads a negative voltage on the substrate. But the data erasing speed of the erasable memory of the invention is lower.
Therefore, it is desirable to provide a rewritable memory and a manufacturing method thereof to solve the above-mentioned problems in the prior art.
Disclosure of Invention
The invention aims to provide an erasable memory and a manufacturing method thereof, which aim to solve the problem of low data erasing speed of the erasable memory.
In order to achieve the above object, the erasable memory of the present invention comprises a substrate, a blocking layer, a first heterojunction, a second heterojunction, a tunneling layer, a channel layer, a source electrode and a drain electrode;
the substrate is used as a grid electrode of the erasable memory;
the barrier layer is arranged on the top surface of the substrate;
the first heterojunction and the second heterojunction are respectively arranged at two opposite ends of the top surface of the barrier layer, the first heterojunction and the second heterojunction have unidirectional conduction charge characteristics, the charge conduction direction of the first heterojunction is opposite to that of the second heterojunction, and the first heterojunction and the second heterojunction are respectively used for data writing operation and data erasing operation of the erasable memory;
the tunneling layer comprises a horizontal part and a vertical part, the horizontal part covers the top surfaces of the first heterojunction and the second heterojunction, and the vertical part is used for separating the first heterojunction and the second heterojunction so as to avoid the conduction of transverse charges of the first heterojunction and the second heterojunction;
the channel layer covers the top surface of the tunneling layer and is used for transferring charges;
the source electrode and the drain electrode of the channel layer are respectively arranged at two opposite ends of the top surface of the channel layer.
The erasable memory of the invention has the advantages that:
the first heterojunction and the second heterojunction are respectively arranged at two opposite ends of the top surface of the barrier layer and are respectively used for data writing operation and data erasing operation of the erasable memory; the first heterojunction and the second heterojunction with the one-way conduction charge characteristic are respectively used as data writing and data erasing channels of the erasable memory, and the charge conduction directions of the first heterojunction and the second heterojunction are opposite, so that the data writing and the data erasing of the erasable memory are more stable and symmetrical, the data erasing speed and the data writing speed of the erasable memory are consistent, and the data erasing speed and the data writing speed of the erasable memory are improved; the vertical part of the tunneling layer is used for isolating the first heterojunction and the second heterojunction, so that the conduction of transverse charges of the first heterojunction and the second heterojunction is avoided, and the dynamic power consumption of the erasable memory is reduced.
Optionally, the first heterojunction includes a first metal oxide layer and a second metal oxide layer, the first metal oxide layer is connected to the top surface of the blocking layer, the bottom surface of the second metal oxide layer is connected to the first metal oxide layer, the top surface of the second metal oxide layer is connected to the horizontal portion, and the first metal oxide layer and the second metal oxide layer are made of different materials.
Optionally, the second heterojunction includes a third metal oxide layer and a fourth metal oxide layer, the third metal oxide layer is connected to the top surface of the barrier layer, the bottom surface of the fourth metal oxide layer is connected to the third metal oxide layer, and the top surface of the fourth metal oxide layer is connected to the horizontal portion;
the third metal oxide layer and the second metal oxide layer are made of the same material, and the fourth metal oxide layer and the first metal oxide layer are made of the same material. The erasable memory has the advantages that the first heterojunction and the second heterojunction have the characteristic of unidirectional conduction of charges, the third metal oxide layer and the second metal oxide layer are made of the same material, and the fourth metal oxide layer and the first metal oxide layer are made of the same material, so that the charge conduction directions of the first heterojunction and the second heterojunction are opposite, the first heterojunction conducts the charges to realize the writing operation of the erasable memory, and the second heterojunction can conduct the charges to realize the erasing operation of the erasable memory. And the data erasing speed and the data writing speed of the erasable memory are symmetrical, namely the data erasing speed and the data writing speed of the erasable memory are consistent. The first heterojunction and the second heterojunction are both composed of two different metal oxide layers, so that the data erasing and writing speed of the erasable memory is improved.
Optionally, when a first electric field is applied to the erasable programmable read-write memory, the first heterojunction is in an on state, the second heterojunction is in a reverse bias off state, and charges in the channel layer pass through the tunneling layer and the second metal oxide layer and are stored in the first metal oxide layer, so as to complete data writing operation of the erasable programmable read-write memory, wherein an electric field direction of the first electric field is directed from the substrate to the channel layer. The erasable memory has the beneficial effects that the erasable memory is applied with the first electric field, so that the first heterojunction conducts the electric charge to complete the data writing operation of the erasable memory.
Optionally, when a second electric field is applied to the erasable programmable read-write memory, the second heterojunction is in an on state, the first heterojunction is in a reverse bias off state, and charges in the second heterojunction pass through the tunneling layer and enter the channel layer, so as to complete a data erasing operation of the erasable programmable read-write memory, wherein an electric field direction of the second electric field is opposite to an electric field direction of the first electric field. The erasable memory is applied with a second electric field, so that the second heterojunction conducts charges to complete data erasing operation of the erasable memory.
The invention also provides a manufacturing method of the erasable memory, which comprises the following steps:
s1: providing a substrate, and depositing an insulating medium on the substrate to form a barrier layer;
s2: forming a first heterojunction in a first region of a top surface of the barrier layer, a second heterojunction in a second region of the top surface of the barrier layer, and a partition region between the first region and the second region;
s3: depositing an insulating medium to form a tunneling layer such that the tunneling layer covers the first heterojunction top surface, the second heterojunction top surface, and the partition region to partition the first heterojunction and the second heterojunction;
s4: and forming a channel layer on the top surface of the tunneling layer, and forming a source electrode and a drain electrode at two ends of the top surface of the channel layer respectively.
The manufacturing method of the erasable memory has the advantages that:
according to the manufacturing method of the erasable memory, the first heterojunction and the second heterojunction are formed on the top surface of the barrier layer and are used as the charge storage medium, so that the process complexity is reduced, the symmetry of data erasing and data writing operations of the erasable memory is improved, and the data erasing and data writing speeds of the erasable memory are increased; the tunneling layer covers the top surface of the first heterojunction, the top surface of the second heterojunction and the partition region to partition the first heterojunction and the second heterojunction, so that the conduction of transverse charges of the first heterojunction and the second heterojunction is avoided, and the dynamic power consumption of the erasable memory is reduced.
Optionally, in the step S2, the step of forming a first heterojunction in a first region of the top surface of the barrier layer and a second heterojunction in a second region of the top surface of the barrier layer includes:
depositing a first metal oxide on the top surface of the barrier layer to form an original first metal oxide layer, and etching the original first metal oxide layer to form a first metal oxide layer in the first area;
depositing a second metal oxide on the first metal oxide layer to form an original second metal oxide layer, and etching the original second metal oxide layer to form a second metal oxide layer in the first area, so that the second metal oxide layer covers the first metal oxide layer.
Optionally, in step S2, the step of forming a first heterojunction in a first region of the top surface of the barrier layer and forming a second heterojunction in a second region of the top surface of the barrier layer further includes:
depositing a third metal oxide on the top surface of the barrier layer to form an original third metal oxide layer, and etching the original third metal oxide layer to form a third metal oxide layer in the second area;
depositing a fourth metal oxide on the third metal oxide layer to form an original fourth metal oxide layer, etching the original fourth metal oxide layer to form a fourth metal oxide layer in a second area, and enabling the fourth metal oxide layer to cover the third metal oxide layer, wherein the first metal oxide and the fourth metal oxide are made of the same material, and the second metal oxide and the third metal oxide are made of the same material.
Optionally, the first metal oxide includes any one of zinc oxide, indium gallium zinc oxide, indium oxide, gallium oxide, aluminum-doped zinc oxide, and tin dioxide, and the second metal oxide includes any one of nickel oxide, cuprous oxide, and aluminum-doped cuprous oxide.
Optionally, in the step S2, the step of forming a partition region between the first region and the second region includes removing materials of the first heterojunction and the second heterojunction contacting end by photolithography and etching techniques to form the partition region.
Drawings
FIG. 1 is a cross-sectional structure diagram of an erasable memory according to an embodiment of the present invention;
FIG. 2 is a flow chart of a method for manufacturing a flash memory according to an embodiment of the present invention;
FIG. 3 is a cross-sectional view of a structure formed after deposition of a barrier layer according to an embodiment of the present invention;
FIG. 4 is a cross-sectional view of a structure formed after depositing a first metal oxide over the structure shown in FIG. 3 in accordance with a first embodiment of the present invention;
FIG. 5 is a cross-sectional view of a structure formed after etching a first metal oxide layer over the structure shown in FIG. 4;
FIG. 6 is a cross-sectional view of the structure shown in FIG. 5 after deposition of a second metal oxide over the structure;
FIG. 7 is a cross-sectional view of a structure formed after etching a second metal oxide layer over the structure shown in FIG. 6;
FIG. 8 is a cross-sectional view of a structure formed after depositing a third metal oxide over the structure shown in FIG. 7;
FIG. 9 is a cross-sectional view of a structure formed after etching a third metal oxide layer over the structure shown in FIG. 8;
FIG. 10 is a cross-sectional view of a structure formed after depositing a fourth metal oxide over the structure shown in FIG. 9;
FIG. 11 is a cross-sectional view of a structure formed after etching a fourth metal oxide layer over the structure shown in FIG. 10;
FIG. 12 is a cross-sectional view of a structure formed after depositing a third metal oxide over the structure shown in FIG. 5 in accordance with a second embodiment of the present invention;
FIG. 13 is a cross-sectional view of a structure formed after etching a third metal oxide layer over the structure shown in FIG. 12;
FIG. 14 is a cross-sectional view of the structure shown in FIG. 13 after deposition of a second metal oxide over the structure;
FIG. 15 is a cross-sectional view of a structure formed after forming a blocking area in addition to the structure shown in FIG. 11;
FIG. 16 is a cross-sectional view of the structure shown in FIG. 15 after a tunneling layer has been deposited thereon;
FIG. 17 is a cross-sectional view of a structure formed after depositing a channel layer over the structure shown in FIG. 16;
fig. 18 is a cross-sectional view of a structure formed after forming a source electrode and a drain electrode on the basis of the structure shown in fig. 17.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below, and it is obvious that the described embodiments are a part of the embodiments of the present invention, but not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. As used herein, the word "comprising" and similar words are intended to mean that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items.
To solve the problems in the prior art, an embodiment of the present invention provides an erasable memory, fig. 1 is a cross-sectional structure diagram of the erasable memory according to the embodiment of the present invention, and referring to fig. 1, the erasable memory according to the present invention includes a substrate 1, a blocking layer 2, a first heterojunction 3, a second heterojunction 4, a tunneling layer 5, a channel layer 6, a source 7, and a drain 8;
the substrate 1 is used as a grid electrode of the erasable memory;
the barrier layer 2 is arranged on the top surface of the substrate 1;
the first heterojunction 3 and the second heterojunction 4 are respectively arranged at two opposite ends of the top surface of the barrier layer 2, the first heterojunction 3 and the second heterojunction 4 have unidirectional conduction charge characteristics, the charge conduction direction of the first heterojunction 3 is opposite to that of the second heterojunction 4, and the first heterojunction 3 and the second heterojunction 4 are respectively used for data writing operation and data erasing operation of the erasable memory;
the front section of the tunneling layer 5 is in a shape of a 'T', the tunneling layer 5 includes a horizontal portion 52 and a vertical portion 51, the horizontal portion 52 covers top surfaces of the first heterojunction 3 and the second heterojunction 4, and the vertical portion 51 is used for separating the first heterojunction 3 and the second heterojunction 4 to prevent lateral electric charges of the first heterojunction 3 and the second heterojunction 4 from being conducted;
the channel layer 6 covers the top surface of the tunneling layer 5 and is used for charge migration;
the source 7 and the drain 8 of the channel layer 6 are respectively arranged at two opposite ends of the top surface of the channel layer 6.
The erasable memory of the invention has the advantages that:
the first heterojunction 3 and the second heterojunction 4 are respectively used for data writing operation and data erasing operation of the erasable memory by respectively arranging the first heterojunction 3 and the second heterojunction 4 at two opposite ends of the top surface of the barrier layer 2; the first heterojunction 3 and the second heterojunction 4 with the one-way conduction charge characteristic are respectively used as data writing and data erasing channels of the erasable memory, the charge conduction directions of the first heterojunction 3 and the second heterojunction 4 are opposite, so that the data writing and the data erasing of the erasable memory are more stable and symmetrical, the data erasing speed and the data writing speed of the erasable memory are consistent, and the data erasing speed and the data writing speed of the erasable memory are improved; the first heterojunction 3 and the second heterojunction 4 are separated by the vertical portion 51 of the tunneling layer 5, and the conduction of the lateral charges of the first heterojunction 3 and the second heterojunction 4 is avoided, thereby reducing the dynamic power consumption of the erasable memory.
As an alternative embodiment of the present invention, as shown in fig. 1, the first heterojunction 3 includes a first metal oxide layer 30 and a second metal oxide layer 31, the first metal oxide layer 30 is connected to the top surface of the barrier layer 2, the bottom surface of the second metal oxide layer 31 is connected to the first metal oxide layer 30, the top surface of the second metal oxide layer 31 is connected to the horizontal portion 52, and the first metal oxide layer 30 and the second metal oxide layer 31 are made of different materials.
As an alternative embodiment of the present invention, as shown in fig. 1, the second heterojunction 4 includes a third metal oxide layer 40 and a fourth metal oxide layer 41, the third metal oxide layer 40 is connected to the top surface of the barrier layer 2, the bottom surface of the fourth metal oxide layer 41 is connected to the third metal oxide layer 40, and the top surface of the fourth metal oxide layer 41 is connected to the horizontal portion 52;
the third metal oxide layer 40 and the second metal oxide layer 31 are made of the same material, and the fourth metal oxide layer 41 and the first metal oxide layer 30 are made of the same material. The first heterojunction 3 and the second heterojunction 4 have the characteristic of unidirectional conduction charge, the third metal oxide layer 40 and the second metal oxide layer 31 are made of the same material, and the fourth metal oxide layer 41 and the first metal oxide layer 30 are made of the same material, so that the charge conduction directions of the first heterojunction 3 and the second heterojunction 4 are opposite, the first heterojunction 3 is convenient to conduct the charge to realize the writing operation of the erasable memory, and the second heterojunction 4 can conduct the charge to realize the erasing operation of the erasable memory; the first heterojunction 3 and the second heterojunction 4 are both composed of two different metal oxide layers, so that the data erasing speed and the data writing speed of the erasable memory are improved.
In some optional embodiments, the thicknesses of the first metal oxide layer 30 and the fourth metal oxide layer 41 are the same, and the thicknesses of the second metal oxide layer 31 and the third metal oxide layer 40 are the same, so that the charge conduction directions of the first heterojunction 3 and the second heterojunction 4 are opposite, the data erasing speed and the data writing speed of the erasable memory are consistent, and the symmetry of the data erasing speed and the data writing speed, that is, the data erasing speed and the data writing speed of the erasable memory are consistent, is ensured.
As an alternative embodiment of the present invention, when a positive voltage is applied to the substrate 1 of the rewritable memory, a first electric field is applied to the rewritable memory, and the direction of the electric field is directed from the substrate 1 to the channel layer 6. The first heterojunction 3 is in an on-state and the second heterojunction 4 is in a reverse biased off-state, and charges in the channel layer 6 pass through the tunneling layer 5 into the first heterojunction 3. After entering the first heterojunction 3, the charges pass through the second metal oxide layer 31 and enter the first metal oxide layer 30 in the first longitudinal direction, and after entering the first metal oxide layer 30, the charges are stored in the first metal oxide layer 30, thereby completing the data writing operation of the erasable memory. The erasable memory is applied with a first electric field, so that the first heterojunction conducts the charges to complete the data writing operation of the erasable memory.
As an alternative embodiment of the present invention, when a negative voltage is applied to the substrate 1 of the erasable memory, a second electric field is applied to the erasable memory, the direction of the second electric field is opposite to the direction of the first electric field, and the direction of the second electric field is directed from the channel layer 6 to the substrate 1. The second heterojunction 4 is in a conducting state, the first heterojunction 3 is in a reverse bias cut-off state, and charges in the second heterojunction 4 longitudinally penetrate through the tunneling layer 5 to enter the channel layer 6 along the second direction, so that the data erasing operation of the erasable memory is completed. The erasable memory is applied with a second electric field, so that the second heterojunction conducts the charges to complete the data erasing operation of the erasable memory.
It is to be noted that the charges in the data write operation and the erase operation of the above-described rewritable memory refer to negative charges.
FIG. 2 is a flow chart of a method for manufacturing a rewritable memory according to an embodiment of the invention. Referring to fig. 2, the present invention further provides a method for manufacturing an erasable memory, comprising the steps of:
s1: providing a substrate, and depositing an insulating medium on the substrate to form a barrier layer;
s2: forming a first heterojunction in a first region of a top surface of the barrier layer, a second heterojunction in a second region of the top surface of the barrier layer, and a partition region between the first region and the second region;
s3: depositing an insulating medium to form a tunneling layer such that the tunneling layer covers the first heterojunction top surface, the second heterojunction top surface, and the partition region to partition the first heterojunction and the second heterojunction;
s4: and forming a channel layer on the top surface of the tunneling layer, and forming a source electrode and a drain electrode at two ends of the top surface of the channel layer respectively.
In some alternative embodiments, the substrate 1 is any one of a low resistance silicon substrate, a silicon-on-insulator substrate, a tantalum nitride substrate, a silicon dioxide substrate, a silicon substrate, and a titanium nitride substrate.
In some alternative embodiments, the present invention selects a low resistance silicon substrate as the substrate 1.
Figure 3 is a cross-sectional view of a structure formed after deposition of a barrier layer according to an embodiment of the present invention.
In some alternative embodiments, referring to fig. 3, the step of depositing an insulating dielectric material on the substrate to form a barrier layer in step S1 is to deposit a barrier layer 2 on the top surface of the substrate 1 by an atomic layer deposition technique.
In some alternative embodiments, the material of the barrier layer 2 is silicon oxide (SiO)2) Hafnium oxide (HfO)2) Tantalum pentoxide (Ta)2O5) Titanium dioxide (TiO)2) And hafnium zirconium oxygen (HfZrO)4) Any one or more of these may be combined.
In some alternative embodiments, the invention is not limited to forming the barrier layer 2 on the substrate 1 by atomic layer deposition techniques, but the barrier layer 2 may be formed by any one of chemical vapor deposition techniques, physical vapor deposition techniques, pulsed laser deposition techniques, and electron beam evaporation techniques.
In the first embodiment of the present invention, the step of forming a first heterojunction in a first region of the top surface of the barrier layer and a second heterojunction in a second region of the top surface of the barrier layer in the step S2 includes:
depositing a first metal oxide on the top surface of the barrier layer to form an original first metal oxide layer, and etching the original first metal oxide layer to form a first metal oxide layer in the first area;
depositing a second metal oxide on the first metal oxide layer to form an original second metal oxide layer, and etching the original second metal oxide layer to form a second metal oxide layer in the first area, so that the second metal oxide layer covers the first metal oxide layer.
In the step S2, the step of forming a first heterojunction in a first region of the top surface of the barrier layer and forming a second heterojunction in a second region of the top surface of the barrier layer further includes:
depositing a third metal oxide on the top surface of the barrier layer to form an original third metal oxide layer, and etching the original third metal oxide layer to form a third metal oxide layer in the second area;
depositing a fourth metal oxide on the third metal oxide layer to form an original fourth metal oxide layer, etching the original fourth metal oxide layer to form a fourth metal oxide layer in a second area, and enabling the fourth metal oxide layer to cover the third metal oxide layer, wherein the first metal oxide and the fourth metal oxide are made of the same material, and the second metal oxide and the third metal oxide are made of the same material.
Specifically, the first heterojunction and the second heterojunction are formed by the following steps:
s201: forming a first metal oxide layer;
s202: forming a second metal oxide layer;
s203: forming a third metal oxide layer;
s204: and forming a fourth metal oxide layer.
FIG. 4 is a cross-sectional view of a structure formed after depositing a first metal oxide over the structure shown in FIG. 3 in accordance with a first embodiment of the present invention; fig. 5 is a cross-sectional view of a structure formed by etching a first metal oxide layer on the basis of the structure shown in fig. 4.
In some optional embodiments, referring to fig. 4 and 5, the step of forming the first metal oxide layer in step S201 includes:
depositing a first metal oxide on the top surface of the barrier layer 2 by an atomic layer deposition technique to form a raw first metal oxide layer 301, and depositing the raw first metal oxide layer 301 to form a pattern as shown in fig. 4;
the original first metal oxide layer 301 is etched by photolithography and etching techniques to form a first metal oxide layer 30 in the first region, forming a pattern as shown in fig. 5.
In some embodiments of the present invention, after depositing the original first metal oxide layer 301 on the barrier layer 2, a photoresist is spin-coated on the top surface of the original first metal oxide layer 301, and a photoresist pattern for defining the shape of the original first metal oxide layer 301 is formed by a photolithography process including exposure and development; the photoresist is used as a mask, and the original first metal oxide layer 301 is etched by any one of dry etching, ion milling etching, plasma etching, reactive ion etching, laser ablation, inductively coupled plasma etching and wet etching by using an etchant solution, so that the first metal oxide layer 30 in the first region is obtained.
FIG. 6 is a cross-sectional view of the structure shown in FIG. 5 after deposition of a second metal oxide over the structure; fig. 7 is a cross-sectional view of a structure formed after etching a second metal oxide layer over the structure shown in fig. 6.
In some optional embodiments, referring to fig. 6 and 7, the step of forming a second metal oxide layer in step S202 includes:
depositing a second metal oxide on the upper surface of the first metal oxide layer 30 and the upper surface of the barrier layer 2 by an atomic layer deposition technique to form an original second metal oxide layer 311, wherein the formed pattern is as shown in fig. 6;
the original second metal oxide layer 311 is etched by photolithography and etching techniques to form a second metal oxide layer 31 in the first region, and the second metal oxide layer 31 covers the first metal oxide layer 30 to form a pattern as shown in fig. 7.
The specific step of forming the second metal oxide layer 31 in step S202 may refer to the specific step of forming the first metal oxide layer 30, and is not described herein again.
FIG. 8 is a cross-sectional view of a structure formed after depositing a third metal oxide over the structure shown in FIG. 7; fig. 9 is a cross-sectional view of a structure formed by etching a third metal oxide layer over the structure shown in fig. 8.
In some optional embodiments, referring to fig. 8 and 9, the step of forming a third metal oxide layer in step S203 includes:
depositing a third metal oxide on the top surfaces of the barrier layer 2 and the second metal oxide layer 31 by using an atomic layer deposition technique to form an original third metal oxide layer 401, wherein the formed pattern is as shown in fig. 8;
the original third metal oxide layer 401 is etched by photolithography and etching techniques to form a third metal oxide layer 40 in the second region, the pattern being formed as shown in fig. 9.
FIG. 10 is a cross-sectional view of a structure formed after depositing a fourth metal oxide over the structure shown in FIG. 9; fig. 11 is a cross-sectional view of a structure formed by etching a fourth metal oxide layer over the structure shown in fig. 10.
In some optional embodiments, referring to fig. 10 and 11, the step of forming a fourth metal oxide layer in step S204 includes:
depositing a fourth metal oxide on the second metal oxide layer 31 and the third metal oxide layer 40 by using an atomic layer deposition technique to form an original fourth metal oxide layer 411, wherein the formed pattern is as shown in fig. 10;
the original fourth metal oxide layer 411 is etched by photolithography and etching techniques to form a fourth metal oxide layer 41 in the second region, and the fourth metal oxide layer 41 covers the third metal oxide layer 40, so as to form a pattern as shown in fig. 11. The first metal oxide and the fourth metal oxide are made of the same material, and the second metal oxide and the third metal oxide are made of the same material.
In the second embodiment of the present invention, the first heterojunction 3 and the second heterojunction 4 are formed by the steps of:
s211: forming a first metal oxide layer;
s212: forming a third metal oxide layer;
s213: forming a second metal oxide layer;
s214: and forming a fourth metal oxide layer.
In some optional embodiments, referring to fig. 4 and 5, the step of forming the first metal oxide layer in step S211 includes:
depositing a first metal oxide on the barrier layer 2 by an atomic layer deposition technique to form an original first metal oxide layer 301, and forming a pattern as shown in fig. 4;
the original first metal oxide layer 301 is etched by photolithography and etching techniques to form a first metal oxide layer 30 in the first region, the pattern being formed as shown in fig. 5.
FIG. 12 is a cross-sectional view of a structure formed after depositing a third metal oxide over the structure shown in FIG. 5 in accordance with a second embodiment of the present invention; fig. 13 is a cross-sectional view of a structure formed after etching a third metal oxide layer on the basis of the structure shown in fig. 12.
In some optional embodiments, referring to fig. 12 and 13, the step of forming a third metal oxide layer in step S212 includes:
depositing a third metal oxide on the barrier layer 2 and the first metal oxide layer 30 by using an atomic layer deposition technique to form an original third metal oxide layer 401, wherein the formed pattern is as shown in fig. 12;
the original third metal oxide layer 401 is etched by photolithography and etching techniques to form a third metal oxide layer 40 in the second region, the pattern being formed as shown in fig. 13.
Fig. 14 is a cross-sectional view of a structure formed after depositing a second metal oxide over the structure shown in fig. 13.
In some optional embodiments, referring to fig. 14 and 9, the step of forming a second metal oxide layer in step S213 includes:
depositing a second metal oxide on the first metal oxide layer 30 and the third metal oxide layer 40 by an atomic layer deposition technique to form an original second metal oxide layer 311, and forming a pattern as shown in fig. 14;
the original second metal oxide layer 311 is etched by photolithography and etching techniques to form a second metal oxide layer 31 in the first region, and the pattern is as shown in fig. 9.
In some optional embodiments, referring to fig. 10 and 11, the step of forming a fourth metal oxide layer in step S214 includes:
referring to fig. 10, depositing a fourth metal oxide on the second metal oxide layer 31 and the third metal oxide layer 40 by an atomic layer deposition technique to form an original fourth metal oxide layer 411, which is patterned as in fig. 10;
the original fourth metal oxide layer 411 is etched by photolithography and etching techniques to form a fourth metal oxide layer 41 in the second region, and the pattern is as shown in fig. 11.
As an alternative embodiment of the present invention, the first metal oxide and the fourth metal oxide include zinc oxide (ZnO), Indium Gallium Zinc Oxide (IGZO), indium oxide (In) having electron conductivity2O3) Gallium oxide (Ga)2O3) Aluminum-doped zinc oxide (AlZnO) and tin dioxide (SnO)2) Any one of them.
The second metal oxide and the third metal oxide include nickel oxide (NiO), cuprous oxide (Cu) having hole conductivity2O), aluminum-doped cuprous oxide (CuAlO)2) And stannous oxide (SnO).
Fig. 15 is a schematic view of the first heterojunction and the second heterojunction after forming partition regions according to the embodiment of the invention.
In some alternative embodiments, referring to fig. 15, in step S2, the step of forming a partition area between the first area and the second area includes:
and removing materials of contact ends of the first heterojunction 3 and the second heterojunction 4 by photoetching and etching technologies, specifically, taking the top surface of the second metal oxide layer 31 and the top surface of the fourth metal oxide layer 41 as etching initial surfaces and the top surface of the barrier layer 2 as an etching end surface, and etching part of the second metal oxide layer 31, part of the fourth metal oxide layer 41, part of the first metal oxide layer 30 and part of the third metal oxide layer 40 of the two heterojunction contact ends to form an isolation area.
In some embodiments, the present invention may select zinc oxide (ZnO) as a constituent material of the first and second metal oxide layers 30 and 31, and may select nickel oxide (NiO) as a constituent material of the second and third metal oxide layers 31 and 40.
Fig. 16 is a cross-sectional view of a structure formed after depositing a tunneling layer over the structure shown in fig. 15.
In some optional embodiments, referring to fig. 16, the step of depositing an insulating medium to form a tunneling layer in step S3 such that the tunneling layer covers the first heterojunction top surface, the second heterojunction top surface and the partition region to partition the first heterojunction and the second heterojunction comprises:
depositing an insulating medium on the top surfaces of the first heterojunction 3 and the second heterojunction 4 by using an atomic layer deposition technique to form an insulating medium layer, so that the insulating medium layer covers the top surfaces of the first heterojunction 3 and the second heterojunction 4, and part of the insulating medium layer completely fills the partition region to form the tunneling layer 5, and the formed pattern is as shown in fig. 16.
Referring to fig. 16, the tunneling layer 5 has a T-shaped front cross-section, the tunneling layer 5 includes a horizontal portion 52 and a vertical portion 51, the horizontal portion 52 covers the top surface of the second metal oxide layer 31 and the top surface of the fourth metal oxide layer 41, the vertical portion 51 is inserted into the blocking area to block the first heterojunction 3 and the second heterojunction 4, and the vertical portion 51 has a shape identical to that of the blocking area.
It should be noted that the present invention is not limited to depositing the insulating medium to form the tunneling layer 5 by the atomic layer deposition technique, and the insulating medium may be deposited by any one of chemical vapor deposition, physical vapor deposition, pulsed laser deposition, and electron beam evaporation to form the tunneling layer 5.
In some embodiments of the present invention, the insulating medium of the material of the tunneling layer 5 is silicon oxide (SiO)2) Hafnium oxide (HfO)2) Tantalum pentoxide (Ta)2O5) Titanium dioxide (TiO)2) And hafnium zirconium oxygen (HfZrO)4) A stacked layer combination of any one or more of them.
Fig. 17 is a cross-sectional view of a structure formed after depositing a channel layer on the basis of the structure shown in fig. 16.
In some embodiments of the present invention, referring to fig. 17, in the step S4, the specific steps of forming the channel layer on the top surface of the tunneling layer are:
a channel layer 6 is deposited on the top surface of the tunneling layer 5 by a physical vapor deposition process, and the resulting pattern is as shown in fig. 17.
It may be noted that the present invention is not limited to depositing the channel layer 6 by a physical vapor deposition process, and the channel layer 6 may be deposited by a process of atomic layer deposition, pulsed laser deposition, electron beam evaporation, or the like.
In some embodiments of the present invention, the channel layer 6 is made of Indium Gallium Zinc Oxide (IGZO) or indium oxide (In) as a material2O3) Gallium oxide (Ga)2O3) Zinc oxide (ZnO), aluminum-doped zinc oxide (AlZnO), nickel oxide (NiO) and cuprous oxide (Cu)2O).
Fig. 18 is a cross-sectional view of a structure formed after forming a source electrode and a drain electrode on the basis of the structure shown in fig. 17.
Referring to fig. 18, in step S4, the specific steps of forming a source and a drain at two ends of the top surface of the channel layer respectively are:
a metal material is deposited on the top surface of the channel layer 6 by a physical vapor deposition process. The metal material is then etched by photolithography and etching techniques to form the source 7 and drain 8 electrodes, patterned as shown in figure 18.
In summary, the manufacturing method of the erasable memory of the present invention has the following advantages:
according to the manufacturing method of the erasable memory, the first heterojunction 3 is formed in the first area on the top surface of the barrier layer 2, the second heterojunction 4 is formed in the second area on the top surface of the barrier layer 2, the partition area is arranged between the first heterojunction 3 and the second heterojunction 4, the first area and the second area are symmetrical about the partition area, and therefore the first heterojunction 3 and the second heterojunction 4 are formed on the barrier layer 2, the two heterojunctions are jointly used as charge storage media, process complexity is reduced, symmetry of data erasing and data writing operation of the erasable memory is improved, and data erasing and data writing speed of the erasable memory is improved. The first heterojunction 3 and the second heterojunction 4 are blocked by the vertical portion 51 of the tunneling layer 5, and the conduction of the lateral charges of the first heterojunction 3 and the second heterojunction 4 is prevented, thereby reducing the dynamic power consumption of the erasable memory.
Although the embodiments of the present invention have been described in detail hereinabove, it is apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it is to be understood that such modifications and variations fall within the scope and spirit of the present invention as set forth in the appended claims. Moreover, the invention as described herein is capable of other embodiments and of being practiced or of being carried out in various ways.
Claims (10)
1. An erasable memory is characterized by comprising a substrate, a barrier layer, a first heterojunction, a second heterojunction, a tunneling layer, a channel layer, a source electrode and a drain electrode;
the substrate is used as a grid electrode of the erasable memory;
the barrier layer is arranged on the top surface of the substrate;
the first heterojunction and the second heterojunction are respectively arranged at two opposite ends of the top surface of the barrier layer, the first heterojunction and the second heterojunction have unidirectional conduction charge characteristics, the charge conduction direction of the first heterojunction is opposite to that of the second heterojunction, and the first heterojunction and the second heterojunction are respectively used for data writing operation and data erasing operation of the erasable memory;
the tunneling layer comprises a horizontal part and a vertical part, the horizontal part covers the top surfaces of the first heterojunction and the second heterojunction, and the vertical part is used for separating the first heterojunction and the second heterojunction so as to avoid the conduction of transverse charges of the first heterojunction and the second heterojunction;
the channel layer covers the top surface of the tunneling layer and is used for transferring charges;
the source electrode and the drain electrode of the channel layer are respectively arranged at two opposite ends of the top surface of the channel layer.
2. The erasable memory of claim 1, wherein the first heterojunction comprises a first metal oxide layer and a second metal oxide layer, the first metal oxide layer is connected to the top surface of the barrier layer, the bottom surface of the second metal oxide layer is connected to the first metal oxide layer, the top surface of the second metal oxide layer is connected to the horizontal portion, and the first metal oxide layer and the second metal oxide layer are made of different materials.
3. The erasable memory of claim 2, wherein the second heterojunction comprises a third metal oxide layer and a fourth metal oxide layer, the third metal oxide layer is connected to the top surface of the barrier layer, the bottom surface of the fourth metal oxide layer is connected to the third metal oxide layer, and the top surface of the fourth metal oxide layer is connected to the horizontal portion;
the third metal oxide layer and the second metal oxide layer are made of the same material, and the fourth metal oxide layer and the first metal oxide layer are made of the same material.
4. The erasable programmable memory of claim 3, wherein when a first electric field is applied to the erasable programmable memory, the first heterojunction is in an on state, the second heterojunction is in a reverse bias off state, and charges in the channel layer are stored in the first metal oxide layer after passing through the tunneling layer and the second metal oxide layer, so as to complete a data writing operation of the erasable programmable memory, wherein an electric field direction of the first electric field is directed to the channel layer from the substrate.
5. The erasable memory of claim 4, wherein when a second electric field is applied to the erasable memory, the second heterojunction is in an on state, the first heterojunction is in a reverse biased off state, and charges in the second heterojunction pass through the tunneling layer into the channel layer to complete a data erasing operation of the erasable memory, wherein the electric field direction of the second electric field is opposite to the electric field direction of the first electric field.
6. A method for manufacturing an erasable memory is characterized by comprising the following steps:
s1: providing a substrate, and depositing an insulating medium on the substrate to form a barrier layer;
s2: forming a first heterojunction in a first region of a top surface of the barrier layer, a second heterojunction in a second region of the top surface of the barrier layer, and a partition region between the first region and the second region;
s3: depositing an insulating medium to form a tunneling layer such that the tunneling layer covers the first heterojunction top surface, the second heterojunction top surface, and the partition region to partition the first heterojunction and the second heterojunction;
s4: and forming a channel layer on the top surface of the tunneling layer, and forming a source electrode and a drain electrode at two ends of the top surface of the channel layer respectively.
7. The method of manufacturing of claim 6, wherein the step of forming a first heterojunction in a first region of the top surface of the barrier layer and a second heterojunction in a second region of the top surface of the barrier layer in step S2 comprises:
depositing a first metal oxide on the top surface of the barrier layer to form an original first metal oxide layer, and etching the original first metal oxide layer to form a first metal oxide layer in the first area;
depositing a second metal oxide on the first metal oxide layer to form an original second metal oxide layer, and etching the original second metal oxide layer to form a second metal oxide layer in the first area, so that the second metal oxide layer covers the first metal oxide layer.
8. The method of manufacturing of claim 7, wherein the step of forming a first heterojunction in a first region of the top surface of the barrier layer and a second heterojunction in a second region of the top surface of the barrier layer in step S2 further comprises:
depositing a third metal oxide on the top surface of the barrier layer to form an original third metal oxide layer, and etching the original third metal oxide layer to form a third metal oxide layer in the second area;
depositing a fourth metal oxide on the third metal oxide layer to form an original fourth metal oxide layer, etching the original fourth metal oxide layer to form a fourth metal oxide layer in a second area, and enabling the fourth metal oxide layer to cover the third metal oxide layer, wherein the first metal oxide and the fourth metal oxide are made of the same material, and the second metal oxide and the third metal oxide are made of the same material.
9. The method of manufacturing of claim 8, wherein the first metal oxide comprises any one of zinc oxide, indium gallium zinc oxide, indium oxide, gallium oxide, aluminum-doped zinc oxide, and tin dioxide, and the second metal oxide comprises any one of nickel oxide, cuprous oxide, and aluminum-doped cuprous oxide.
10. The method of manufacturing of claim 6, wherein the step of forming a partition region between the first region and the second region in step S2 comprises removing material of the first heterojunction and the second heterojunction contacting end by photolithography and etching techniques to form the partition region.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111525709.XA CN114220818A (en) | 2021-12-14 | 2021-12-14 | Erasable memory and manufacturing method thereof |
| PCT/CN2022/101218 WO2023109077A1 (en) | 2021-12-14 | 2022-06-24 | Erasable memory and manufacturing method therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111525709.XA CN114220818A (en) | 2021-12-14 | 2021-12-14 | Erasable memory and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114220818A true CN114220818A (en) | 2022-03-22 |
Family
ID=80701660
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111525709.XA Pending CN114220818A (en) | 2021-12-14 | 2021-12-14 | Erasable memory and manufacturing method thereof |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN114220818A (en) |
| WO (1) | WO2023109077A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023109077A1 (en) * | 2021-12-14 | 2023-06-22 | 上海集成电路制造创新中心有限公司 | Erasable memory and manufacturing method therefor |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5234848A (en) * | 1991-11-05 | 1993-08-10 | Texas Instruments Incorporated | Method for fabricating lateral resonant tunneling transistor with heterojunction barriers |
| CN102800675B (en) * | 2011-05-25 | 2015-08-26 | 中国科学院微电子研究所 | A kind of charge-captured non-volatilization memory and manufacture method thereof |
| CN104183649A (en) * | 2014-09-03 | 2014-12-03 | 东南大学 | Threshold-voltage-adjustable thin film transistor |
| CN111463212B (en) * | 2020-03-12 | 2022-06-21 | 复旦大学 | Quick erasable floating gate memory and preparation method thereof |
| CN113451428B (en) * | 2021-06-28 | 2022-10-21 | 复旦大学 | Double-half floating gate photoelectric memory and preparation process thereof |
| CN114220818A (en) * | 2021-12-14 | 2022-03-22 | 上海集成电路制造创新中心有限公司 | Erasable memory and manufacturing method thereof |
-
2021
- 2021-12-14 CN CN202111525709.XA patent/CN114220818A/en active Pending
-
2022
- 2022-06-24 WO PCT/CN2022/101218 patent/WO2023109077A1/en unknown
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023109077A1 (en) * | 2021-12-14 | 2023-06-22 | 上海集成电路制造创新中心有限公司 | Erasable memory and manufacturing method therefor |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2023109077A1 (en) | 2023-06-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI361489B (en) | Transistor with independent gate structures | |
| CN103811496B (en) | For the method and apparatus with the non-volatile memory cells improving programming efficiency | |
| CN106611816B (en) | RRAM device and forming method thereof | |
| US10636552B2 (en) | Multi-function electronic device having memristor and memcapacitor and method for manufacturing the same | |
| CN100477266C (en) | Non-volatile memory devices including barrier layers and methods of manufacturing the same | |
| JPH03181178A (en) | Nonvolatile semiconductor memory device and its manufacture | |
| CN100580934C (en) | Nonvolatile semiconductor storage device and manufacturing method of the same | |
| TWI401831B (en) | Select devices including an open volume, memory devices and systems including same, and methods for forming same | |
| KR20030067956A (en) | Memory device with quantum dot and method of manufacturing the same | |
| JP2004056095A (en) | Nonvolatile semiconductor memory device and method of manufacturing the same | |
| CN111490045B (en) | Semi-floating gate memory based on two-dimensional material and preparation method thereof | |
| CN114220818A (en) | Erasable memory and manufacturing method thereof | |
| CN111627920A (en) | Ferroelectric memory cell | |
| KR20120114082A (en) | Non-volatile memory device using threshold switching material and manufacturing method of the same | |
| CN111446254A (en) | Semi-floating gate memory based on metal oxide semiconductor and preparation method thereof | |
| WO2023082652A1 (en) | Thin film transistor memory and preparation method therefor | |
| KR20070082509A (en) | Semiconductor memory device using alloy metal gate electrode | |
| US8148757B2 (en) | Semiconductor device, and its manufacturing method | |
| CN110364573B (en) | Memory device, memory and method for preparing memory device | |
| KR100607173B1 (en) | Non-volitile memory device having oxide charge storage layer | |
| KR100609067B1 (en) | Non-volatile memory device and method for fabricating the same | |
| JPS63224366A (en) | Semiconductor storage device | |
| CN111477628A (en) | Semi-floating gate TFT memory and preparation method thereof | |
| US11502189B2 (en) | Charge storage and sensing devices and methods | |
| TWI447765B (en) | Capacitor unit having multi-layer conductive plate |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |