CN114220767A - Semiconductor structure, manufacturing method thereof and memory - Google Patents

Semiconductor structure, manufacturing method thereof and memory Download PDF

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Publication number
CN114220767A
CN114220767A CN202111391757.4A CN202111391757A CN114220767A CN 114220767 A CN114220767 A CN 114220767A CN 202111391757 A CN202111391757 A CN 202111391757A CN 114220767 A CN114220767 A CN 114220767A
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layer
groove
top surface
dielectric layer
insulating layer
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邹欣伟
华子群
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials

Abstract

The invention provides a semiconductor structure, a manufacturing method thereof and a memory. The manufacturing method of the semiconductor structure comprises the following steps: forming a plurality of grooves in the insulating layer; forming a dielectric layer on the side wall of the groove and the top surface of the insulating layer; forming an interconnection layer in the groove formed with the dielectric layer and on the top surface of the insulating layer formed with the dielectric layer; and removing the interconnection layer on the top surface of the insulating layer and part of the interconnection layer in the groove by a chemical mechanical polishing process, wherein the dielectric layer on the top surface of the insulating layer is used as a stop layer of the chemical mechanical polishing process.

Description

Semiconductor structure, manufacturing method thereof and memory
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor structure, a manufacturing method thereof and a memory.
Background
With the development of semiconductor technology, the integration degree of integrated circuit chips has reached the scale of several hundreds of millions or even billions of semiconductor devices. The wiring design of integrated circuit chips has become more and more complex due to different requirements. In order to meet the demand, in the related art, interconnections between a plurality of semiconductor devices in an integrated circuit are realized by a multilayer interconnection structure.
However, as the miniaturization of integrated circuits progresses, the critical dimension of the interconnect structure is continuously shrinking, and the reliability of the interconnect structure is greatly challenged.
Disclosure of Invention
In order to solve the related technical problems, embodiments of the present invention provide a semiconductor structure, a manufacturing method thereof, and a memory.
An embodiment of the present invention provides a method for manufacturing a semiconductor structure, including: forming a plurality of grooves in the insulating layer; forming a dielectric layer on the side wall of the groove and the top surface of the insulating layer;
forming an interconnection layer in the groove formed with the dielectric layer and on the top surface of the insulating layer formed with the dielectric layer;
and removing the interconnection layer on the top surface of the insulating layer and a part of the interconnection layer in the groove by a Chemical Mechanical Polishing (CMP) process, wherein the dielectric layer on the top surface of the insulating layer is used as a stop layer of the CMP process.
In the above scheme, the method further comprises: and removing the dielectric layer on the top surface of the insulating layer and part of the dielectric layer and part of the interconnection layer in the groove by the chemical mechanical grinding process.
In the above scheme, the size of the opening of the groove decreases with the increase of the depth of the groove; the thickness of the dielectric layer on the side wall of the groove is reduced along with the increase of the depth of the groove.
In the above scheme, the forming a dielectric layer on the sidewall of the groove and the top surface of the insulating layer includes:
forming dielectric layers on the side wall and the bottom of the groove and the top surface of the insulating layer;
and removing the dielectric layer at the bottom of the groove to obtain the dielectric layer positioned on the side wall of the groove and the top surface of the insulating layer.
In the above scheme, the method further comprises:
forming a barrier layer in the groove having the dielectric layer formed on the sidewall thereof and on the dielectric layer on the top surface of the insulating layer;
forming an interconnection layer on the surface of the barrier layer;
the removing the interconnect layer on the top surface of the insulating layer includes:
and removing the interconnection layer on the top surface of the insulating layer and the barrier layer on the top surface of the insulating layer.
In another aspect, an embodiment of the present invention provides a semiconductor structure, which is prepared by the method according to any one of the above embodiments of the present invention, and includes:
an insulating layer;
a plurality of grooves in the insulating layer;
the dielectric layer is positioned on the side wall of the groove and the top surface of the insulating layer;
an interconnect layer located in the recess; wherein the dielectric layer on the top surface of the insulating layer is flush with the top surface of the interconnect layer; the dielectric layer on the top surface of the insulating layer is used as a stop layer of the chemical mechanical polishing process.
An embodiment of the present invention further provides another semiconductor structure, which is prepared by the method according to any one of the above embodiments of the present invention, and the semiconductor structure includes:
an insulating layer;
a plurality of grooves in the insulating layer;
the dielectric layer is positioned on the side wall of the groove;
an interconnect layer located in the recess; wherein the dielectric layer on the sidewall of the groove is flush with the top surface of the interconnection layer and the top surface of the insulation layer; the dielectric layer on the top surface of the insulating layer is used as a stop layer of the chemical mechanical polishing process.
In the above scheme, the size of the opening of the groove decreases with the increase of the depth of the groove; the thickness of the dielectric layer on the side wall of the groove is reduced along with the increase of the depth of the groove.
In the above scheme, the semiconductor structure further includes a barrier layer located between the interconnection layer and the dielectric layer.
In the above scheme, the material of the dielectric layer includes a high dielectric constant material.
In the above scheme, the material of the dielectric layer includes a low dielectric constant material.
An embodiment of the present invention further provides a memory, including: the semiconductor structure of any of the above embodiments of the present invention.
The embodiment of the invention provides a semiconductor structure, a manufacturing method thereof and a memory. The manufacturing method of the semiconductor structure comprises the following steps: forming a plurality of grooves in the insulating layer; forming a dielectric layer on the side wall of the groove and the top surface of the insulating layer; forming an interconnection layer in the groove formed with the dielectric layer and on the top surface of the insulating layer formed with the dielectric layer; and removing the interconnection layer on the top surface of the insulating layer and part of the interconnection layer in the groove by a chemical mechanical polishing process, wherein the dielectric layer on the top surface of the insulating layer is used as a stop layer of the chemical mechanical polishing process. In the embodiment of the invention, on one hand, the dielectric layer is formed on the side wall of the groove for forming the semiconductor structure so as to reduce the probability of lateral voltage breakdown (lateral direction can be understood as a direction vertical to the depth direction of the groove) caused by the closer distance between two adjacent semiconductor structures, thereby improving the reliability of the semiconductor structure; on the other hand, in the process of forming the semiconductor structure, the dielectric layer is arranged on the top surface of the insulating layer, so that when the interconnection layer on the top surface of the insulating layer is removed through a chemical mechanical polishing process in the following process, the dielectric layer on the top surface of the insulating layer is used as a stop layer of the chemical mechanical polishing process, the removal amount of the insulating layer by the chemical mechanical polishing process can be reduced, and the manufacturing cost is further reduced.
Drawings
FIG. 1a is a schematic cross-sectional view illustrating a voltage breakdown problem between interconnect structures in the related art;
FIG. 1b is a schematic cross-sectional view illustrating an electromigration problem between interconnect structures according to the related art;
fig. 2 is a schematic flow chart illustrating a method for fabricating a semiconductor structure according to an embodiment of the present invention;
fig. 3a to fig. 3h are schematic cross-sectional views illustrating a manufacturing process of a semiconductor structure according to an embodiment of the invention.
Detailed Description
In order to make the technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be further elaborated with reference to the drawings and the embodiments. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention can be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
The present invention is more particularly described in the following paragraphs with reference to the accompanying drawings by way of example. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
It is to be understood that the meaning of "on … …", "above … …" and "above … …" in the present invention should be interpreted in the broadest sense such that "on … …" not only means that it is "on" something without intervening features or layers therebetween (i.e., directly on something), but also includes the meaning of being "on" with intervening features or layers therebetween.
Furthermore, spatially relative terms such as "on … …," "over … …," "over … …," "on," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated for ease of description. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
In embodiments of the present invention, the term "substrate" refers to a material on which subsequent layers of material are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may comprise a variety of semiconductor materials, such as silicon, silicon germanium, arsenic, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers.
In embodiments of the present invention, the term "layer" refers to a portion of material that includes a region having a thickness. A layer may extend over the entirety of the underlying or overlying structure or may have an extent that is less than the extent of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure, or a layer may be between any horizontal pair at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically and/or along inclined surfaces. The layer may comprise a plurality of sub-layers. For example, the interconnect layer may include one or more conductors and contact sub-layers (in which interconnect lines and/or via contacts are formed), and one or more dielectric sub-layers.
In the embodiments of the present invention, the terms "first", "second", and the like are used for distinguishing similar objects, and are not necessarily used for describing a particular order or sequence.
With the development of semiconductor technology, the integration of very large scale integrated circuit chips has reached the scale of hundreds of millions or even billions of semiconductor devices, and the wiring of very large scale integrated circuits is more complicated. As the number of semiconductor devices in an integrated circuit increases, signal integration of the semiconductor devices requires more and more high-density interconnection structures to achieve connection.
In particular, the interconnect structure is formed in a Back-End-Of-Line (BEOL) process Of a semiconductor device, and different interconnect structures can be grown on a semiconductor substrate according to different requirements Of an integrated circuit. However, as the miniaturization of integrated circuits progresses, the process size of semiconductor devices is continuously shrinking, so that there are many problems affecting reliability between a plurality of interconnection structures.
For example, in the related art, in order to reduce the cost, it is often implemented by reducing the critical dimension of the interconnect structure to increase the density of the interconnect structure in the same area. In the formation of the interconnect structure, the interconnect structure formed by a related process, such as a Physical Vapor Deposition (PVD) process, generally has a structure with a large top diameter and a small bottom diameter, i.e., a structure with a large top and a small bottom diameter. Also, due to the close distance between the multiple interconnect structures, a Voltage Breakdown (VBD) problem may occur between the tops of two interconnect structures, as shown in fig. 1 a.
For example, in the related art, in the process of forming an interconnect structure, as the critical dimension of the interconnect structure is reduced, the Aspect Ratio (AR) of the interconnect structure is increased, which in turn causes an abnormal Electron Migration (EM) problem of the interconnect structure formed by the related process, as shown in fig. 1 b.
Accordingly, in order to solve at least part of the above problems, embodiments of the present invention provide a method for manufacturing a semiconductor; fig. 2 is a schematic flow chart illustrating an implementation of a method for fabricating a semiconductor structure according to an embodiment of the present invention. As shown in fig. 2, the method comprises the steps of:
step 201: forming a plurality of grooves in the insulating layer;
step 202: forming a dielectric layer on the side wall of the groove and the top surface of the insulating layer;
step 203: forming an interconnection layer in the groove formed with the dielectric layer and on the top surface of the insulating layer formed with the dielectric layer;
step 204: and removing the interconnection layer on the top surface of the insulating layer and part of the interconnection layer in the groove by a chemical mechanical polishing process, wherein the dielectric layer on the top surface of the insulating layer is used as a stop layer of the chemical mechanical polishing process.
Fig. 3a-3h are cross-sectional views illustrating an example of a process for fabricating a semiconductor structure according to an embodiment of the present invention. It should be understood that the operations shown in FIG. 2 are not exclusive, and other operations may be performed before, after, or between any of the operations shown; and it should be understood that the specific operational steps shown in fig. 2 do not have to be performed in the order shown in fig. 2, and that other operational steps may be performed before, after, or between any of the specific operational steps. Methods of forming semiconductor structures according to various embodiments of the present invention are described below with reference to fig. 2 and 3a-3 h.
Here, the semiconductor structure may be used to form at least a portion of a semiconductor device, such as an interconnect structure.
It should be noted that before forming the plurality of grooves in the insulating layer, the insulating layer 301 needs to be provided, as shown in fig. 3 a.
In practical applications, the insulating Layer 301 may be formed by PVD, Chemical Vapor Deposition (CVD) process, Atomic Layer Deposition (ALD) process, or a combination thereof. The constituent material of the insulating layer 301 may include an oxide such as, but not limited to, silicon dioxide.
In step 201, referring to fig. 3b, a plurality of recesses 302 are formed in the insulating layer 301.
It should be noted that, before the formation of the recess 302, a patterned mask layer needs to be formed over the insulating layer 301, and the formation of the patterned mask layer involves a series of process steps, such as first depositing a mask layer, coating a photoresist on the mask layer, exposing and developing, and removing the photoresist by dissolving or ashing to finally form the patterned mask layer. The material of the mask layer may be, for example, silicon nitride.
It is understood that the pattern of the mask layer employed in the semiconductor structure of the embodiment of the present invention may include a series of predetermined patterns.
In practice, the method for forming the recess 302 may include, but is not limited to, dry plasma etching.
It should be noted that, in the process of forming the groove with a deeper groove, since the number of ions bombarded to the opening of the groove by the plasma decreases with the increase of the depth of the groove, the width of the top diameter of the groove is different from the width of the bottom diameter of the groove in the process of forming the groove.
Based on this, in some embodiments, the opening size of the groove decreases with increasing depth of the groove, as shown in fig. 3 b.
It should be noted that in some embodiments, the grooves may have a top width substantially the same as a bottom width due to different selected processing methods. In this embodiment, the difference between the top diameter width and the bottom diameter width of the groove is taken as an example for explanation.
In step 202, a dielectric layer 303 is formed on the sidewalls of the recess 302 and the top surface of the insulating layer, as shown in fig. 3 c.
In practical applications, by forming the dielectric layer 303 on the sidewall of the recess 302, the dielectric layer 303 can be used to reduce the voltage breakdown problem, the electromigration problem, and the resistance-capacitance delay (RC) delay problem caused by the close distance between the two semiconductor structures.
Here, RC delay is the signal delay in an integrated circuit caused by the process of charging and discharging a capacitor (C) controlled by a resistor (R).
Specifically, the material for forming the dielectric layer includes a High dielectric constant material (High K material). The high-K material includes: hafnium oxide (HfO)2) Zirconium oxide (ZrO)2) And the like.
Here, a high-K material generally refers to a material having a dielectric constant higher than 3.9.
It is understood that a higher dielectric constant of a material indicates that the less conductive the material is, the better the insulating properties. Therefore, the material of the dielectric layer is set to be a high dielectric constant material, and the dielectric layer has high breakdown voltage resistance; and the probability of voltage breakdown between two adjacent semiconductor structures can be reduced.
In addition, the material of the dielectric layer 303 may further include a Low dielectric constant material (Low K material), such as carbon-doped silicon oxide (also referred to as silicon oxycarbide).
Here, low K materials generally refer to materials having a dielectric constant below 2.8.
Because the low-K material has better conductivity, the dielectric layer with low dielectric constant can be used for reducing the parasitic capacitance between two adjacent semiconductor structures, so that the RC delay is reduced, and the response rate of a semiconductor device is improved.
In the process of manufacturing the integrated circuit chip, the dielectric constant of the dielectric layer used in the integrated circuit is reduced, so that the leakage current of the integrated circuit is reduced, the capacitance effect between semiconductor structures is further reduced, and the heating degree and the like of the integrated circuit can be reduced.
In practice, the dielectric layer 303 may be formed by PVD, CVD, ALD, or a combination thereof.
In some embodiments, the forming a dielectric layer 303 on the sidewall of the groove 302 and the top surface of the insulating layer includes:
forming a dielectric layer on the side wall and the bottom of the groove 302 and the top surface of the insulating layer 301;
and removing the dielectric layer 303 at the bottom of the groove 302 to obtain the dielectric layer 303 positioned on the side wall of the groove and the top surface of the insulating layer.
In practical applications, the deposition pattern may be selected to be different, which may result in different positions for forming the dielectric layer. In the embodiment of the present invention, the dielectric layer 303 is located on the sidewall and the bottom of the recess 302 and the top surface of the insulating layer 301.
For example, as shown in fig. 3c, in the process of forming the dielectric layer, since the deposition process itself is self-limiting, there may be a phenomenon that the dielectric layer 303 is formed at the bottom of a part of the groove 302, and the dielectric layer 303 is not formed at the bottom of another part of the groove 302, so that the dielectric layer 303 at the bottom of the groove needs to be removed in order to satisfy the uniformity of the plurality of grooves.
In addition, in order to satisfy the requirement that an interconnection layer in contact with the bottom of the groove 302 is formed in the groove 302 in which the dielectric layer 303 is formed; during the process of forming the dielectric layer 303, the dielectric layer 303 at the bottom of the recess also needs to be removed.
Based on this, in the embodiment of the present invention, after the dielectric layer 303 is formed on the sidewall and the bottom of the groove 302 and the top surface of the insulating layer 301, the dielectric layer 303 at the bottom of the groove is etched back to remove the dielectric layer 303 at the bottom of the groove 302, as shown in fig. 3 d.
It is understood that the method used in the process of the etching back treatment includes, but is not limited to, dry plasma etching.
It should be noted that, in the process of performing the etching back treatment, the etching process may also trim the dielectric layer located on the sidewall of the groove, so that the uniformity of the side, away from the sidewall of the groove, of the dielectric layer located on the sidewall of the groove is improved; the method is more favorable for improving the step coverage rate of the interconnection layer formed in the subsequent process (such as a filling process), improving the reliability of the semiconductor structure and increasing the process window of the semiconductor reliability.
Since the recess 302 formed with the dielectric layer 303 is subjected to the etch-back process, the bottom of the interconnect layer formed in the recess 302 is in direct contact with the bottom of the recess 302.
In some embodiments, as shown in fig. 3e, the method further comprises:
a barrier layer 304 is formed in the recess having a dielectric layer 303 formed on its sidewalls and on the dielectric layer 303 located on the top surface of the insulating layer.
In practical applications, as shown in fig. 3e, a blocking layer is formed to cover the upper surface of the dielectric layer, the sidewall of the recess 302 and the bottom of the recess 302, so as to block the diffusion of charges in the interconnect layer 305.
Here, the material of the barrier layer may include nitride, such as titanium nitride (TiN); or the material of the barrier layer may comprise a material different from that of the dielectric layer and any suitable material of the interconnect layer.
In practice, the barrier layer may be formed by a method including, but not limited to, CVD, PVD, ALD, etc.
In step 203, as shown in fig. 3f, an interconnect layer 305 is formed in the groove formed with the dielectric layer 303 and on the top surface of the insulating layer 301 formed with the dielectric layer 303.
Forming an interconnect layer 305 in the groove 302 having the dielectric layer 303 formed on the sidewall thereof and on the top surface of the insulating layer having the dielectric layer 303 formed thereon, including: an interconnect layer 305 is formed on the surface of the barrier layer 304.
Here, the interconnect layer 305 may include metal tungsten, polysilicon, or the like.
In practice, the interconnect layer 305 may be formed by PVD, CVD, ALD, or a combination thereof.
It should be noted that the bottom of the interconnect layer 305 is directly in contact with the bottom of the recess 302, and it is understood that in a specific application scenario, the bottom of the interconnect layer 305 may be electrically connected to other device structures (e.g., a source) in the insulating layer; alternatively, according to the practical application, after a portion of the insulating layer 301 is removed, the interconnect layer 305 penetrates through the insulating layer 301, so that the bottom of the interconnect layer 305 can be electrically connected to other device structures.
In step 204, the interconnect layer 305 on the top surface of the insulating layer 301 and the portion of the interconnect layer 305 in the recess are removed.
In practice, the interconnect layer 305 on the top surface of the insulating layer 301 and a portion of the interconnect layer 305 in the recess may be removed by a chemical mechanical polishing process to form the interconnect layer 305 with a top surface substantially flush with the top surface of the barrier layer 304, as shown in fig. 3 g.
Here, substantially flush may be understood as a case where the top surface of the interconnect layer 305 and the top surface of the barrier layer 304 are formed to be flush with each other on the same plane after the chemical mechanical polishing process, and a situation where the top surface of the interconnect layer 305 and the top surface of the barrier layer 304 are not flush with each other on the same plane due to a process margin during the chemical mechanical polishing process.
It should be noted that, due to different applicable scenarios of the semiconductor structure, there is a difference in the structural requirements of the semiconductor, for example, the interconnection layer in the semiconductor structure is required to be flush with the top surface of the insulating layer.
Based on this, in some embodiments, the method further comprises: and removing the dielectric layer on the top surface of the insulating layer and part of the dielectric layer and part of the interconnection layer in the groove by the chemical mechanical grinding process.
Here, as shown in fig. 3h, a dielectric layer 303 and an interconnect layer 305 are formed with top surfaces substantially flush with the top surface of the insulating layer 301.
It should be noted that the above process of forming the dielectric layer 303 and the interconnect layer 305 with top surfaces substantially flush with the top surface of the insulating layer 301 may be completed by one step through a chemical mechanical polishing process, that is, the interconnect layer 305 and the dielectric layer 303 on the top surface of the insulating layer and a portion of the interconnect layer 305 and the dielectric layer 303 in the groove are removed together through the chemical mechanical polishing process at a time; the step of removing the interconnect layer 305 on the top surface of the insulating layer 301 and the portion of the interconnect layer 305 in the recess may also be performed by a chemical mechanical polishing process; removing the dielectric layer 303 on the top surface of the insulating layer 301 and a portion of the interconnection layer 305 in the groove; to form a dielectric layer 303 and an interconnect layer 305 in the recess having top surfaces substantially flush with the top surface of the insulating layer; here, the bottom of the interconnect layer 305 is in direct contact with the bottom of the recess 302; the dielectric layer 303 on the top surface of the insulating layer 301 is used as a stop layer for the chemical mechanical polishing process.
It can be understood that the dielectric layer is used as a stop layer for the chemical mechanical polishing process, which can reduce the removal of the insulating layer, i.e. reduce the removal amount, and thus reduce the manufacturing cost. On the other hand, the depth-to-width ratio of the groove formed in the early-stage process can be reduced, so that the process window of the deposition process is improved when the dielectric layer is deposited in the groove.
It is appreciated that reducing the aspect ratio of the recess may also reduce the ohmic contact of the semiconductor structure.
It should be noted that in the above embodiments of the present invention, the barrier layer 304 is located between the dielectric layer 303 and the interconnect layer 305, and therefore, in some specific embodiments, removing the interconnect layer 305 and the dielectric layer 303 located on the top surface of the insulating layer 301 includes:
the interconnect layer 305, the barrier layer 304, and the dielectric layer 303 on the top surface of the insulating layer 301 are removed.
In some embodiments, the thickness of the dielectric layer 303 formed in the above embodiments of the present invention decreases as the depth of the recess increases.
In practical application, the opening size of the groove 302 decreases with the increase of the groove depth, so that the radial width of the groove presents a shape with a large upper part and a small lower part; here, the thickness of the dielectric layer 303 on the sidewall of the groove is set to decrease with the increase of the opening depth of the groove 302, and the dielectric layer is in a form of being thick at the top and thin at the bottom, so that the step coverage rate of the interconnection layer formed in the groove 302 with the dielectric layer 303 can be improved in the subsequent process.
It is often necessary to form a dielectric layer in a High Aspect Ratio (HAR) opening during the fabrication of a semiconductor device. The step coverage of a dielectric layer is generally measured by the ratio of the thickness of the dielectric layer at the bottom of the opening (Btop) to the thickness of the dielectric layer at the top of the opening (Ttop). Ideally, the thickness of the dielectric layer remains constant as the opening depth increases, i.e., the step coverage is 1.
It should be noted that, here, the thickness of the dielectric layer located in the groove can be understood as the thickness of the dielectric layer located on the sidewall of the groove, and the starting point of the thickness is calculated as the sidewall of the groove.
In the related art, since the opening size of the groove decreases with the increase of the depth of the groove, the width of the groove exhibits a shape with a larger top and a smaller bottom, and thus the thickness of the semiconductor structure formed in the corresponding groove decreases with the increase of the depth of the opening, i.e., the step coverage ratio is less than 1, and exhibits a shape with a larger top and a smaller bottom.
Based on this, when the semiconductor structures are small in size, the probability of voltage breakdown occurring between the tops of the two semiconductor structures is increased, and the problem of electron migration in the semiconductor structures is liable to occur, thereby affecting the electrical performance of the semiconductor device.
Therefore, in the embodiment of the invention, the interconnection layer is formed in the groove formed with the dielectric layer, which is beneficial to improving the step coverage rate of the interconnection layer, so that the up-and-down uniformity of the side wall of the interconnection layer is well improved, namely the verticality of the side wall of the interconnection layer is better, and the problem of electron migration in a semiconductor structure can be effectively reduced.
It should be noted that, in some embodiments, when the verticality of the sidewall of the formed groove is good, that is, the top radial width and the bottom radial width of the groove are substantially the same, the thickness of the dielectric layer formed on the sidewall of the groove is substantially the same, that is, the step coverage of the dielectric layer is good. Also, the step coverage rate of the semiconductor structure formed in the groove 302 formed with the dielectric layer 303 in the subsequent process can be improved.
In practical applications, the verticality of the sidewall of the interconnect layer 305 is better, that is, the size of the opening of the interconnect layer 305 is substantially constant with the increase of the depth; which in turn may reduce electromigration issues of the interconnect layer 305.
In practical application, as shown in fig. 3h, the dielectric layer 303 and the interconnect layer 305 on the upper surface of the insulating layer 301 are removed, and a portion of the interconnect layer 305 in the recess 302 is removed by a chemical mechanical polishing process, so as to form the interconnect layer 305 in the recess 302 with a top surface flush with the top surface of the insulating layer 301. Of the interconnect layer 305.
It is understood that the dielectric layer 303 on the upper surface of the insulating layer 301 serves as an etch stop layer for the cmp process, which can reduce the process cost of the cmp process.
It should be noted that, in the related art, in the process of forming an interconnection layer having a top surface flush with the top substrate of the insulating layer without adding a dielectric layer, a groove with a deeper depth needs to be formed on the insulating layer due to the application requirement of the chemical mechanical polishing process, so that the aspect ratio of the groove is increased; then, removing the barrier layer and the interconnection layer on the insulating layer by a chemical mechanical polishing process; wherein, in the chemical mechanical polishing process, a portion of the insulating layer needs to be removed to obtain a semiconductor structure with a predetermined height.
By adopting the manufacturing method of the semiconductor structure in the embodiment of the invention, the dielectric layer (namely the dielectric layer positioned in the groove) arranged between the interconnection layer and the side wall of the groove can reduce the probability of lateral voltage breakdown (the lateral direction can be understood as the direction vertical to the depth direction of the groove) caused by the closer distance between two adjacent semiconductor structures, thereby improving the reliability of the semiconductor structure; the dielectric layer on the top surface of the insulating layer is used as a stop layer of the chemical mechanical polishing process, and the quantity of the insulating layer removed in the chemical mechanical polishing process can be reduced; thereby reducing the cost. In particular, the amount of the solvent to be used,
in the above embodiments of the present invention, the semiconductor structure with a predetermined height can be obtained without removing the insulating layer in the chemical mechanical polishing process. Therefore, the loss of the insulating layer can be reduced; thereby reducing the cost. Furthermore, because the chemical mechanical polishing does not need to remove part of the insulating layer, when the groove is formed in the insulating layer, the depth of the groove does not need to be too deep, so that the depth-to-width ratio of the groove can be reduced, the process window is enlarged, and the reliability of the semiconductor structure is improved.
An embodiment of the present invention further provides a semiconductor structure, which is prepared by the method for manufacturing a semiconductor structure according to any one of the above embodiments of the present invention, as shown in fig. 3g, and the semiconductor structure includes:
an insulating layer;
a plurality of grooves in the insulating layer;
the dielectric layer is positioned on the side wall of the groove and the top surface of the insulating layer;
an interconnect layer located in the recess; wherein the dielectric layer on the top surface of the insulating layer is flush with the top surface of the interconnect layer; the dielectric layer on the top surface of the insulating layer is used as a stop layer of the chemical mechanical polishing process.
An embodiment of the present invention further provides another semiconductor structure, which is prepared by the method for manufacturing a semiconductor structure according to any one of the above embodiments of the present invention, as shown in fig. 3h, and the semiconductor structure includes:
an insulating layer;
a plurality of grooves in the insulating layer;
the dielectric layer is positioned on the side wall of the groove;
an interconnect layer located in the recess; wherein the dielectric layer on the sidewall of the groove is flush with the top surface of the interconnection layer and the top surface of the insulation layer; the dielectric layer on the top surface of the insulating layer is used as a stop layer of the chemical mechanical polishing process.
In practice, the material of the insulating layer 301 includes, but is not limited to, an oxide, such as silicon oxide.
Referring to fig. 3g, 3h, the insulating layer 301 includes a plurality of grooves 302 therein.
In some embodiments, the size of the opening of the groove decreases with increasing depth of the groove.
A dielectric layer 303 is disposed on the sidewalls of recess 302 and on the top surface of insulating layer 301.
In some embodiments, the thickness of the dielectric layer decreases as the depth of the recess increases.
The interconnect layer 305 is disposed in the recess; wherein the bottom of the interconnect layer 305 is in contact with the bottom of the recess 302.
In some embodiments, the semiconductor structure further comprises: a barrier layer 304 between the interconnect layer 305 and the insulating layer 301.
The various layers of the semiconductor structure of the embodiments of the present invention may be formed by epitaxial growth such as oxidation, atomic layer deposition, CVD or PVD, and the like, as well as by methods known to those skilled in the art.
In practical applications, by forming the dielectric layer 303 on the sidewall of the recess 302, the dielectric layer 303 can be used to reduce the voltage breakdown problem, the electromigration problem and the RC delay problem caused by the close distance between two adjacent semiconductor structures.
In some embodiments, the material of the dielectric layer 303 includes a high dielectric constant material or a low dielectric constant material.
In practical applications, the material of the dielectric layer 303 may include a material with a high dielectric constant K; materials of high K dielectric constant include: HfO2、ZrO2And the like. In the embodiment of the invention, the material of the dielectric layer is set to be a high dielectric constant material, and the dielectric layer has high breakdown voltage resistance; and the probability of voltage breakdown between the semiconductor structures can be better reduced.
In practical applications, the material of the dielectric layer 303 may also include a low dielectric constant material, such as carbon-doped silicon oxide (also referred to as silicon oxycarbide).
Here, when the material of the dielectric layer includes a high dielectric constant material, the dielectric layer may be better used to reduce the problem of voltage breakdown between two adjacent semiconductor structures. The material of the dielectric layer can also be set to be a low dielectric constant material during the use of the semiconductor device. It is understood that the low-k material can also be used to reduce the parasitic capacitance existing between two adjacent semiconductor structures, thereby reducing the RC delay and increasing the response rate of the semiconductor device.
It can be understood that in an integrated circuit chip, the leakage current of the integrated circuit is reduced by reducing the dielectric constant of the dielectric material used in the integrated circuit, so that the capacitance effect between semiconductor structures is reduced, and the heating temperature of the integrated circuit can be reduced.
Here, RC delay is the signal delay in an integrated circuit caused by the process of charging and discharging a capacitor (C) controlled by a resistor (R).
In practical applications, since the opening size of the groove 302 decreases with the increase of the groove depth, the radial width of the groove presents a form with a large top and a small bottom; the thickness of the dielectric layer 303 on the sidewall of the groove is set to decrease with the increase of the opening depth of the groove, and the dielectric layer 303 is thick at the top and thin at the bottom, so that the step coverage rate of the interconnection layer 305 formed in the groove 302 with the dielectric layer 303 can be improved in the subsequent process.
It can be understood that the step coverage of the interconnect layer 305 is improved, so that the uniformity of the interconnect layer 305 is improved, and the electromigration problem occurring in the semiconductor structure can be effectively reduced.
In the embodiment of the invention, on one hand, the dielectric layer is formed on the side wall of the groove for forming the semiconductor structure so as to reduce the probability of lateral voltage breakdown (lateral direction can be understood as a direction vertical to the depth direction of the groove) caused by the closer distance between two adjacent semiconductor structures, thereby improving the reliability of the semiconductor structure; on the other hand, in the process of forming the semiconductor structure, the dielectric layer is arranged on the top surface of the insulating layer, so that when the interconnection layer on the top surface of the insulating layer is removed through a chemical mechanical polishing process in the following process, the dielectric layer on the top surface of the insulating layer is used as a stop layer of the chemical mechanical polishing process, the removal amount of the insulating layer by the chemical mechanical polishing process can be reduced, and the manufacturing cost is further reduced.
It should be noted that, in some embodiments, when the verticality of the sidewall of the formed groove is good, that is, the diameter width of the top of the groove is substantially the same as the diameter width of the bottom of the groove, by using the manufacturing method of the semiconductor structure provided in the above embodiments of the present invention, a dielectric layer with a substantially consistent upper and lower thickness may also be formed on the sidewall of the groove, that is, the step coverage of the dielectric layer is good, and on the one hand, the step coverage of the interconnection layer 305 formed on the sidewall of the groove 302 in the subsequent process may also be improved; on the other hand, the probability of voltage breakdown between two adjacent semiconductor structures is reduced, so that the reliability of the semiconductor structures is improved.
An embodiment of the present invention further provides a memory, including: the semiconductor structure of any of the above embodiments of the present invention.
In some embodiments, the memory comprises a three-dimensional NAND-type memory; the semiconductor structure is used to form an interconnect structure for a three-dimensional NAND-type memory.
In practical applications, the Memory is, for example, a 3D NAND Memory, a Dynamic Random Access Memory (DRAM), or a Phase Change Memory (PCM). The semiconductor structure is not limited to the memory, and may be a logic operator or an analog circuit.
The technical means described in the embodiments of the present invention may be arbitrarily combined without conflict.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.

Claims (12)

1. A method for fabricating a semiconductor structure, comprising:
forming a plurality of grooves in the insulating layer;
forming a dielectric layer on the side wall of the groove and the top surface of the insulating layer;
forming an interconnection layer in the groove formed with the dielectric layer and on the top surface of the insulating layer formed with the dielectric layer;
and removing the interconnection layer on the top surface of the insulating layer and part of the interconnection layer in the groove by a chemical mechanical polishing process, wherein the dielectric layer on the top surface of the insulating layer is used as a stop layer of the chemical mechanical polishing process.
2. The method of manufacturing according to claim 1, further comprising: and removing the dielectric layer on the top surface of the insulating layer and part of the dielectric layer and part of the interconnection layer in the groove by the chemical mechanical grinding process.
3. The method of manufacturing according to claim 1, wherein an opening size of the groove decreases as a depth of the groove increases; the thickness of the dielectric layer on the side wall of the groove is reduced along with the increase of the depth of the groove.
4. The method of claim 1, wherein forming a dielectric layer on the sidewalls of the trench and the top surface of the insulating layer comprises:
forming dielectric layers on the side wall and the bottom of the groove and the top surface of the insulating layer;
and removing the dielectric layer at the bottom of the groove to obtain the dielectric layer positioned on the side wall of the groove and the top surface of the insulating layer.
5. The method of manufacturing according to claim 4, further comprising:
forming a barrier layer in the groove having the dielectric layer formed on the sidewall thereof and on the dielectric layer on the top surface of the insulating layer;
forming an interconnection layer on the surface of the barrier layer;
the removing the interconnect layer on the top surface of the insulating layer includes:
and removing the interconnection layer on the top surface of the insulating layer and the barrier layer on the top surface of the insulating layer.
6. A semiconductor structure prepared by the method of any one of claims 1 to 5, the semiconductor structure comprising:
an insulating layer;
a plurality of grooves in the insulating layer;
the dielectric layer is positioned on the side wall of the groove and the top surface of the insulating layer;
an interconnect layer located in the recess; wherein the dielectric layer on the top surface of the insulating layer is flush with the top surface of the interconnect layer; the dielectric layer on the top surface of the insulating layer is used as a stop layer of the chemical mechanical polishing process.
7. A semiconductor structure prepared by the method of any one of claims 1 to 5, the semiconductor structure comprising:
an insulating layer;
a plurality of grooves in the insulating layer;
the dielectric layer is positioned on the side wall of the groove;
an interconnect layer located in the recess; wherein the dielectric layer on the sidewall of the groove is flush with the top surface of the interconnection layer and the top surface of the insulation layer; the dielectric layer on the top surface of the insulating layer is used as a stop layer of the chemical mechanical polishing process.
8. The semiconductor structure of claim 6 or 7, wherein the opening size of the recess decreases with increasing depth of the recess; the thickness of the dielectric layer on the side wall of the groove is reduced along with the increase of the depth of the groove.
9. The semiconductor structure of claim 6 or 7, further comprising a barrier layer between the interconnect layer and the dielectric layer.
10. The semiconductor structure of claim 6 or 7, wherein the material of the dielectric layer comprises a high dielectric constant material.
11. The semiconductor structure of claim 6 or 7, wherein the material of the dielectric layer comprises a low dielectric constant material.
12. A memory, comprising: the semiconductor structure of any one of claims 6 to 11.
CN202111391757.4A 2021-11-23 2021-11-23 Semiconductor structure, manufacturing method thereof and memory Pending CN114220767A (en)

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