CN114206006A - PCB design method and system based on solder joint reliability test - Google Patents
PCB design method and system based on solder joint reliability test Download PDFInfo
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- CN114206006A CN114206006A CN202111511409.6A CN202111511409A CN114206006A CN 114206006 A CN114206006 A CN 114206006A CN 202111511409 A CN202111511409 A CN 202111511409A CN 114206006 A CN114206006 A CN 114206006A
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- 238000000034 method Methods 0.000 title claims abstract description 106
- 238000013461 design Methods 0.000 title claims abstract description 72
- 238000012360 testing method Methods 0.000 title claims abstract description 63
- 229910000679 solder Inorganic materials 0.000 title claims abstract description 41
- 238000004381 surface treatment Methods 0.000 claims description 54
- 238000003466 welding Methods 0.000 claims description 43
- 239000003990 capacitor Substances 0.000 claims description 42
- 238000012550 audit Methods 0.000 claims description 12
- 238000012790 confirmation Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 238000007654 immersion Methods 0.000 description 5
- 238000003860 storage Methods 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 238000012938 design process Methods 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0005—Apparatus or processes for manufacturing printed circuits for designing circuits by computer
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
- G01R31/2836—Fault-finding or characterising
- G01R31/2849—Environmental or reliability testing, e.g. burn-in or validation tests
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Environmental & Geological Engineering (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
The invention relates to the technical field of PCB design, in particular to a PCB design method and a system based on solder joint reliability test, wherein the design system comprises a solder joint test recording module, a preset auditing module, a process selection module and a wiring module.
Description
Technical Field
The invention relates to the technical field of PCB design, in particular to a PCB design method and a system based on solder joint reliability test.
Background
The PCB, namely the printed circuit board, is a very important electronic component, and is used as a carrier for electrical connection of electronic components, and is mostly made by adopting an electronic printing technology, so that the design layout of the printed circuit board becomes a more important problem;
in the prior art, a part of the printed circuit board which is designed is found to be easy to fall off due to the welding spot of the plug-in capacitor in the using process, so that the printed circuit board is out of work, and therefore, the design link needs to be improved, and the service life of the printed circuit board can be ensured on the basis of firm welding spot.
Disclosure of Invention
The invention aims to provide a PCB design method and system based on solder joint reliability test, which aim to solve the problem that in the prior art, the designed PCB is easy to have insufficient service life due to the falling of solder joints.
In order to achieve the above object, the present invention provides a PCB design method based on solder joint reliability test, which comprises the following steps:
obtaining a plug-in capacitance object related in PCB design and generating a plug-in capacitance list;
determining the effective distance of each plug-in capacitor in the plug-in capacitor list by adopting a solder joint reliability test, wherein the effective distance refers to the distance from a pin solder joint of each plug-in capacitor related in the PCB design to the center of the corresponding plug-in capacitor under the condition that the pin solder joint is not separated;
determining a surface treatment process according to requirements;
and determining the wiring layer according to the surface treatment process and the effective distance and performing predetermined auditing to complete the PCB design.
The PCB design method is improved, the effective distance of the plug-in capacitor used in the position is determined by utilizing the reliability test of the welding spots, the condition that the pin welding spots fall off in the use process of the plug-in capacitor is further avoided, on the basis, the surface treatment process and the wiring layers are sequentially selected, the PCB is designed, the preset audit is finally carried out, the wiring layers and the plug-in capacitor are prevented from being misconnected through the preset audit, and the design accuracy of the PCB is improved.
The method for determining the effective distance by adopting the solder joint reliability test comprises the following steps:
traversing the plug-in capacitor list, welding each plug-in capacitor on the PCB to obtain a device to be tested, and obtaining the welding spot information of each pin of each plug-in capacitor;
placing the device to be tested into an experimental box for providing stress test, and connecting any two pin welding points of each plug-in capacitor with a resistance test system by using connecting wires to form a test path;
and when one of the pin welding spots is found to be invalid within the specified test time, changing the distance between the invalid pin welding spot and the plug-in capacitance center, and repeatedly testing until the situation that the pin-free welding spot is invalid occurs, thus determining the effective distance.
The connecting wire is utilized to connect any two pin welding spots, the change of the measured resistance timely discovers the length of the pin welding spots easy to separate from the PCB, and therefore the effective distance of the pin welding spots difficult to separate from the PCB is confirmed through experiments, and further the distance from the pin welding spots to the center of the plug-in capacitor can be set as required when the PCB is designed.
Wherein the determining of the surface treatment process according to the requirements comprises the following steps:
acquiring a surface treatment process related in PCB design, and generating a surface treatment process list;
and selecting at least one of the surface treatment process lists according to requirements.
The surface treatment process list comprises hot air leveling, chemical nickel gold immersion, whole board nickel gold electroplating, organic coating, chemical silver immersion and chemical tin immersion, and at least one surface treatment process is selected, so that when the PCB is designed, the understanding of surface process treatment, which is caused by unsmooth communication in production, can be prevented from deviating.
Wherein the predetermined audit comprises the steps of:
confirming whether a surface treatment process is selected;
confirming whether a plug-in capacitor used in the PCB design is selected;
it is confirmed whether the wiring layer conflicts with the effective distance of the card capacitance.
And judging whether the PCB design selects a surface treatment process or not, whether a plug-in capacitor is selected or not and whether the wiring layer conflicts with the plug-in capacitor or not by using the preset audit, so that the process loopholes in the PCB design are avoided according to the preset audit, and the integrity of the PCB design is improved.
The invention also provides a PCB design system based on solder joint reliability test, which adopts the design method,
the design system comprises a welding spot test recording module, a preset auditing module, a process selection module and a wiring module,
the welding spot test recording module is used for recording effective distance data of each plug-in capacitance acquired in the welding spot reliability test,
the preset auditing module is used for presetting and auditing the selection of each plug-in capacitance, the setting of effective distance data corresponding to the plug-in capacitance, the selection of a surface treatment process and the setting of a wiring layer to meet the requirements;
the process selection module is used for determining the surface treatment process used by the PCB from the surface treatment process list;
the wiring module is used for establishing a wiring layer according to the effective distance and the surface treatment process.
And correspondingly proposing a design system corresponding to the change of the design method, and by utilizing the change of the design system and the matching of the design method, realizing the confirmation of whether the surface treatment process is selected through the process confirmation unit, realizing the selection of the plug-in capacitance through the plug-in capacitance confirmation unit, and realizing the confirmation of whether the wiring of the wiring layer conflicts with the effective distance of the plug-in capacitance through the wiring layer confirmation unit, thereby improving the support of the design system on the design method.
The invention discloses a PCB design method and a system based on solder joint reliability test, and provides the PCB design method.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic structural diagram of a PCB design system based on solder joint reliability test provided by the present invention.
FIG. 2 is a schematic diagram of steps of a PCB design method based on solder joint reliability test according to the present invention.
FIG. 3 is a schematic diagram of a step of determining an effective distance by using a solder joint reliability test in the PCB design method based on the solder joint reliability test provided by the present invention.
Fig. 4 is a schematic diagram of a step of determining a surface treatment process according to requirements of a PCB design method based on solder joint reliability test provided by the present invention.
Fig. 5 is a schematic diagram illustrating steps of a predetermined audit of a PCB design method based on solder joint reliability test according to the present invention.
The device comprises a 1-welding spot test recording module, a 2-scheduled auditing module, a 3-process selection module, a 4-wiring module, a 5-data recording unit, a 6-resistance measuring unit, a 7-storage unit, an 8-information association unit, a 9-wiring unit and a 10-hyperlink unit.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.
In the description of the present invention, it is to be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, indicate orientations or positional relationships based on the orientations or positional relationships illustrated in the drawings, and are used merely for convenience in describing the present invention and for simplicity in description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, are not to be construed as limiting the present invention. Further, in the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
Referring to fig. 1 to 5, the present invention provides a PCB design method based on solder joint reliability test, which includes the following steps:
s101: obtaining a plug-in capacitance object related in PCB design and generating a plug-in capacitance list;
s102: determining the effective distance of each plug-in capacitor in the plug-in capacitor list by adopting a solder joint reliability test, wherein the effective distance refers to the distance from a pin solder joint of each plug-in capacitor related in the PCB design to the center of the corresponding plug-in capacitor under the condition that the pin solder joint is not separated;
s103: determining a surface treatment process according to requirements;
s104: and determining the wiring layer according to the surface treatment process and the effective distance and performing predetermined auditing to complete the PCB design.
In the embodiment, the PCB design method is improved, the effective distance of the plug-in capacitor used at the position is determined by utilizing the reliability test of the welding spot, so that the condition that the pin welding spot falls off in the use process of the plug-in capacitor is avoided, on the basis, the surface treatment process and the wiring layer are sequentially selected, the PCB is designed, the preset audit is finally carried out, the wiring layer and the plug-in capacitor are prevented from being misconnected through the preset audit, and the design accuracy of the PCB is improved.
Further, the step of determining the effective distance by using the solder joint reliability test includes the following steps:
s201: traversing the plug-in capacitor list, welding each plug-in capacitor on the PCB to obtain a device to be tested, and obtaining the welding spot information of each pin of each plug-in capacitor;
s202: placing the device to be tested into an experimental box for providing stress test, and connecting any two pin welding points of each plug-in capacitor with a resistance test system by using connecting wires to form a test path;
s203: and when any further pin welding point is found to be invalid within the specified test time, changing the distance between the invalid pin welding point and the plug-in capacitance center, and repeatedly testing until the situation that the pin-free welding point is invalid occurs, thus determining the effective distance.
In the embodiment, any two pin welding spots are connected by using the connecting wire, and the length that the pin welding spots are easy to separate from the PCB is found in time by measuring the resistance change, so that the effective distance that the pin welding spots are not easy to separate from the PCB is confirmed through experiments, and the distance from the pin welding spots to the center of the plug-in capacitor can be set as required when the PCB is designed.
Further, the surface treatment process determined according to the requirements comprises the following steps:
s301: acquiring a surface treatment process related in PCB design, and generating a surface treatment process list;
s302: and selecting at least one of the surface treatment process lists according to requirements.
In this embodiment, the list of surface treatment processes includes hot air leveling, electroless nickel gold plating, nickel gold plating on a whole board, organic coating (OSP), chemical silver immersion, and chemical tin immersion, and at least one of the surface treatment processes is selected, so that when designing a PCB, it is possible to avoid deviation in understanding of surface treatment due to unsmooth communication during production.
Further, the predetermined audit comprises the following steps:
s401: confirming whether a surface treatment process is selected;
s402: confirming whether a plug-in capacitor used in the PCB design is selected;
s403: it is confirmed whether the wiring layer conflicts with the effective distance of the card capacitance.
In the embodiment, whether the surface treatment process is selected or not, whether the plug-in capacitance is selected or not and whether the wiring layer conflicts with the plug-in capacitance or not are judged by the preset audit, so that the process loopholes in the PCB design are avoided according to the preset audit, and the integrity of the PCB design is improved.
The invention also provides a PCB design system based on solder joint reliability test, which adopts the design method,
the design system comprises a welding spot test recording module, a preset auditing module 2, a process selection module 3 and a wiring module,
the welding spot test recording module is used for recording effective distance data of each plug-in capacitance acquired in the welding spot reliability test,
the preset auditing module 2 is used for presetting and auditing the selection of each plug-in capacitance, the setting of effective distance data corresponding to the plug-in capacitance, the selection of a surface treatment process and the setting of a wiring layer to meet the requirements;
the process selection module 3 is used for determining the surface treatment process used by the PCB from the surface treatment process list;
the wiring module is used for establishing a wiring layer according to the effective distance and the surface treatment process.
In this embodiment, a design system is proposed in response to a change in a design method, and by using the design system in conjunction with a change in the design method, the process determination unit determines whether a surface treatment process is selected, the plug-in capacitance determination unit determines a plug-in capacitance, and the wiring layer determination unit is configured to determine whether wiring of a wiring layer conflicts with an effective distance of the plug-in capacitance, thereby improving support of the design system on the design method.
Further, the solder joint test recording module comprises a data recording unit 5 and a resistance measuring unit 6, the data recording module is used for recording effective distances obtained by capacitors of all plug-ins in a solder joint reliability test and recording the effective distances corresponding to the capacitors of all the plug-ins, the resistance measuring unit 6 is used for measuring resistance changes of a test path, if the resistance is increased, the test path fails, a pin solder joint is separated, if the resistance is not increased, the test path is normal, and the effective distance corresponding to the plug-in capacitor is obtained;
the process selection module 3 comprises a storage unit 7 and an information association unit 8, wherein the storage unit 7 is used for storing process information related to a surface treatment process, and the information association unit 8 is connected with the wiring module, so that the surface treatment process related to the surface treatment process list can be associated with the wiring layer;
the wiring module comprises a wiring unit 9 and a hyperlink unit 10, wherein the wiring unit 9 is used for realizing wiring, and the hyperlink unit 10 is used for being connected with the information association unit 8 so as to select a wiring template according to the selection of the surface treatment process.
In this embodiment, the data recording unit 5 records the effective distance of each card capacitance, thereby, the indexes of the capacitance of each plug-in unit in the PCB design process are limited, the resistance measuring unit 6 is matched with the resistance measurement, further, the effective distance is obtained, the storage unit 7 is used for storing the technical flows corresponding to the surface treatment processes in the surface treatment process list, the information associating unit 8 transfers the data relating to the surface treatment process stored in the storage unit 7 to the wiring module, and then realize that after selecting the surface treatment process, the related wiring layer wiring can be automatically suggested, the wiring unit 9 supports the wiring in the design process, the hyperlink unit 10 is used for transmitting the wiring layout, and whether the pin welding points of the plug-in capacitor are interfered or not is confirmed by matching with the preset auditing module 2.
The invention discloses a PCB design method and a system based on solder joint reliability test, and provides the PCB design method.
While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (6)
1. A PCB design method based on solder joint reliability test is characterized in that,
the PCB design method based on the solder joint reliability test comprises the following steps:
obtaining a plug-in capacitance object related in PCB design and generating a plug-in capacitance list;
determining the effective distance of each plug-in capacitor in the plug-in capacitor list by adopting a solder joint reliability test, wherein the effective distance refers to the distance from a pin solder joint of each plug-in capacitor related in the PCB design to the center of the corresponding plug-in capacitor under the condition that the pin solder joint is not separated;
determining a surface treatment process according to requirements;
and determining the wiring layer according to the surface treatment process and the effective distance and performing predetermined auditing to complete the PCB design.
2. The PCB design method based on solder joint reliability test as claimed in claim 1,
the method for determining the effective distance by adopting the solder joint reliability test comprises the following steps:
traversing the plug-in capacitor list, welding each plug-in capacitor on the PCB to obtain a device to be tested, and obtaining the welding spot information of each pin of each plug-in capacitor;
placing the device to be tested into an experimental box for providing stress test, and connecting any two pin welding points of each plug-in capacitor with a resistance test system by using connecting wires to form a test path;
and when one of the pin welding spots is found to be invalid within the specified test time, changing the distance between the invalid pin welding spot and the plug-in capacitance center, and repeatedly testing until the situation that the pin-free welding spot is invalid occurs, thus determining the effective distance.
3. The PCB design method based on solder joint reliability test as claimed in claim 2,
the surface treatment process determined according to the requirements comprises the following steps:
acquiring a surface treatment process related in PCB design, and generating a surface treatment process list;
and selecting at least one of the surface treatment process lists according to requirements.
4. The PCB design method based on solder joint reliability test of claim 3,
the predetermined audit comprises the following steps:
confirming whether a surface treatment process is selected;
confirming whether a plug-in capacitor used in the PCB design is selected;
it is confirmed whether the wiring layer conflicts with the effective distance of the card capacitance.
5. A PCB design system based on solder joint reliability test, using the design method of claim 4,
the design system comprises a welding spot test recording module, a preset auditing module, a process selection module and a wiring module,
the welding spot test recording module is used for recording effective distance data of each plug-in capacitance acquired in the welding spot reliability test,
the preset auditing module is used for presetting and auditing the selection of each plug-in capacitance, the setting of effective distance data corresponding to the plug-in capacitance, the selection of a surface treatment process and the setting of a wiring layer to meet the requirements;
the process selection module is used for determining the surface treatment process used by the PCB from the surface treatment process list;
the wiring module is used for establishing a wiring layer according to the effective distance and the surface treatment process.
6. The PCB design system based on solder joint reliability test of claim 5,
the preset auditing module comprises a process confirming unit, a plug-in capacitance confirming unit and a wiring layer confirming unit, wherein the process confirming unit is used for confirming whether the surface treatment process is selected, the plug-in capacitance confirming unit is used for confirming the selection of the plug-in capacitance, and the wiring layer confirming unit is used for confirming whether the wiring of the wiring layer conflicts with the effective distance of the plug-in capacitance.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202111511409.6A CN114206006A (en) | 2021-12-06 | 2021-12-06 | PCB design method and system based on solder joint reliability test |
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| CN202111511409.6A CN114206006A (en) | 2021-12-06 | 2021-12-06 | PCB design method and system based on solder joint reliability test |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103258062A (en) * | 2012-02-15 | 2013-08-21 | 鸿富锦精密工业（深圳）有限公司 | Wiring checking system and method |
| CN108225963A (en) * | 2017-12-30 | 2018-06-29 | 广州兴森快捷电路科技有限公司 | PCB design method based on the test of BGA welding spot reliabilities |
| ES2786850A1 (en) * | 2019-04-12 | 2020-10-13 | Aragonesa De Componentes Pasivos S A | MOMENTARY PUSH-BUTTON MODULE (Machine-translation by Google Translate, not legally binding) |
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- 2021-12-06 CN CN202111511409.6A patent/CN114206006A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103258062A (en) * | 2012-02-15 | 2013-08-21 | 鸿富锦精密工业（深圳）有限公司 | Wiring checking system and method |
| CN108225963A (en) * | 2017-12-30 | 2018-06-29 | 广州兴森快捷电路科技有限公司 | PCB design method based on the test of BGA welding spot reliabilities |
| ES2786850A1 (en) * | 2019-04-12 | 2020-10-13 | Aragonesa De Componentes Pasivos S A | MOMENTARY PUSH-BUTTON MODULE (Machine-translation by Google Translate, not legally binding) |
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