CN114204957A

CN114204957A - Audio transceiving circuit, and related device, method, apparatus and storage medium

Info

Publication number: CN114204957A
Application number: CN202111509366.8A
Authority: CN
Inventors: 黎绍鑫; 郝正海; 徐承
Original assignee: Hefei Ustc Iflytek Co ltd
Current assignee: Hefei Ustc Iflytek Co ltd
Priority date: 2021-12-10
Filing date: 2021-12-10
Publication date: 2022-03-18

Abstract

The application discloses audio frequency transceiver circuit and relevant equipment, method, device and storage medium, wherein, audio frequency transceiver circuit includes: the data transceiving module comprises a clock management module and a plurality of audio transceiving modules arranged in parallel, the audio transceiving modules are coupled to the pickup circuit and/or the loudspeaker circuit through the audio bus, and the output end of the clock management module is connected to each audio transceiving module so as to synchronize the clock parameters of each audio transceiving module; the transmission bus comprises a master control interface, a data interface and a first configuration interface, the plurality of audio receiving and transmitting modules are coupled to the data interface, and the configuration end of the clock management module is connected to the first configuration interface; and the main control module is connected to the main control interface so as to realize data intercommunication with the data transceiving module through the main control interface. By the scheme, all channel data can be synchronized and aligned.

Description

Audio transceiving circuit, and related device, method, apparatus and storage medium

Technical Field

The present application relates to the field of electronic information technologies, and in particular, to an audio transceiving circuit, and related device, method, apparatus, and storage medium.

Background

With the continuous development of information technology, people are more and more inclined to use a multi-person conversation system to realize online meetings, business negotiations and the like. By combining the multi-person conversation system with a corresponding algorithm, the acoustic problems of a plurality of rooms can be solved to a certain extent, such as sound source positioning, dereverberation, voice enhancement, blind source separation and the like, so that the multi-person conversation quality is improved.

Currently, a multi-person dialogue system in the market is generally implemented by integrating a microphone array and components such as a DSP (Digital Signal Processor), an ARM (Advanced RISC Machines), an MCU (Micro Control Unit), an ADC (Analog to Digital Converter), and the like. However, these methods have the problem of clock asynchronism, so it is difficult to achieve synchronization and alignment of all channel data, which directly affects the normal execution of the following algorithms. In view of the above, how to synchronize and align all the channel data becomes an urgent problem to be solved.

Disclosure of Invention

The technical problem mainly solved by the present application is to provide an audio transceiving circuit, and related device, method, apparatus and storage medium, which can implement synchronization and alignment of all channel data.

In order to solve the above technical problem, a first aspect of the present application provides an audio transceiving circuit, including: the data transceiving module comprises a clock management module and a plurality of audio transceiving modules arranged in parallel, the audio transceiving modules are coupled to the pickup circuit and/or the loudspeaker circuit through the audio bus, and the output end of the clock management module is connected to each audio transceiving module so as to synchronize the clock parameters of each audio transceiving module; the transmission bus comprises a master control interface, a data interface and a first configuration interface, the plurality of audio receiving and transmitting modules are coupled to the data interface, and the configuration end of the clock management module is connected to the first configuration interface; and the main control module is connected to the main control interface so as to realize data intercommunication with the data transceiving module through the main control interface.

In order to solve the above technical problem, a second aspect of the present application provides a multimedia device, including: a sound pickup circuit, a speaker circuit, and the audio transceiver circuit of the first aspect; the pickup circuit and the speaker circuit are coupled to the audio transceiving circuit through an audio bus.

In order to solve the above technical problem, a third aspect of the present application provides an audio transceiving method, where the audio transceiving method is applied to the audio transceiving apparatus in the first aspect, and the audio transceiving method includes: the master control module synchronizes clock parameters of each audio transceiving module through a transmission bus; based on the audio receiving and sending task, the first audio data received by each audio receiving and sending module is obtained through the transmission bus, and/or second audio data is prepared and taken away by each audio receiving and sending module through the transmission bus and sent out.

In order to solve the above technical problem, a fourth aspect of the present invention provides an audio transceiver integrated with the audio transceiver circuit in the first aspect, the audio transceiver comprising: the clock synchronization module is used for driving the master control module to synchronize clock parameters of each audio receiving and transmitting module through the transmission bus; and the data transmission module is used for driving the main control module to acquire the first audio data received by each audio transceiver module through the transmission bus based on the audio transceiving task and/or preparing second audio data, and the second audio data is taken away and sent out by each audio transceiver module through the transmission bus.

In order to solve the above technical problem, a fifth aspect of the present application provides a computer-readable storage medium storing program instructions executable by a processor, the program instructions being configured to implement the audio transceiving method in the third aspect.

In the above scheme, the audio transceiver circuit comprises a data transceiver module, a transmission bus and a main control module, the data transceiver module is coupled to the pickup circuit and/or the speaker circuit via an audio bus, an output terminal of the clock management module is connected to each audio transceiver module to synchronize clock parameters of each audio transceiver module, the transmission bus comprises a main control interface, a data interface and a first configuration interface, a plurality of audio transceiver modules are coupled to the data interface, a configuration terminal of the clock management module is connected to the first configuration interface, the main control module is connected to the main control interface to realize data intercommunication with the data transceiver module via the main control interface, on one hand, the main control interface and the data interface of the transmission bus are favorable for realizing unified data transceiving scheduling of the plurality of audio transceiver modules, on the other hand, the main control interface and the first configuration interface of the transmission bus are used, the clock parameters of the audio transceiver modules can be synchronized, so that all channel data can be synchronized and aligned.

Drawings

FIG. 1 is a block diagram of an embodiment of an audio transceiver circuit according to the present application;

FIG. 2 is a schematic diagram of a storage space of a volatile storage medium;

FIG. 3 is a block diagram of an embodiment of an audio transceiver module;

FIG. 4 is a block diagram of an embodiment of a multimedia device of the present application;

FIG. 5 is a flowchart illustrating an embodiment of an audio transceiving method according to the present application;

FIG. 6 is a block diagram of an embodiment of an audio transceiver apparatus according to the present application;

FIG. 7 is a block diagram of an embodiment of a computer-readable storage medium of the present application.

Detailed Description

The following describes in detail the embodiments of the present application with reference to the drawings attached hereto.

In the following description, for purposes of explanation and not limitation, specific details are set forth such as particular system structures, interfaces, techniques, etc. in order to provide a thorough understanding of the present application.

The terms "system" and "network" are often used interchangeably herein. The term "and/or" herein is merely an association describing an associated object, meaning that three relationships may exist, e.g., a and/or B, may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship. Further, the term "plurality" herein means two or more than two.

Referring to fig. 1, fig. 1 is a block diagram of an audio transceiver circuit 10 according to an embodiment of the present application. The audio transceiver circuit 10 includes: the data transceiver module 11 comprises a clock management module 111 and a plurality of audio transceiver modules 112 arranged in parallel, the audio transceiver modules 112 are coupled to a sound pickup circuit (not shown) and/or a speaker circuit (not shown) through an audio bus, and an output end a1 of the clock management module 111 is connected to each of the audio transceiver modules 112 to synchronize clock parameters of each of the audio transceiver modules 112; the transmission bus 12 includes a main control interface 121, a data interface 122 and a first configuration interface 123, the plurality of audio transceiver modules 112 are coupled to the data interface 122, and the configuration end a2 of the clock management module 111 is connected to the first configuration interface 123; the master control module 13 is connected to the master control interface 121 to implement data communication with the data transceiving module 11 through the master control interface 121.

In one implementation scenario, the transmission bus 12 may include, but is not limited to, AXI (Advanced eXtensible Interface), etc., and is not limited thereto.

In one implementation scenario, the clock management module 111 may include, but is not limited to: PLL (Phase Locked Loop), MMCM (Mixed-Mode Clock Manager), etc., without limitation. The working principle of the clock management module 111 can refer to the details of the related technologies such as PLL, MMCM, etc., and the words are not described in detail. Therefore, the clock signal of the audio transceiver module 112 with respect to the audio bus is configured by the clock management module 111, for example, for I2S, the frequencies of the three clock signals MCLK/LRCK/SCK can be configured by the clock management module 111, which is beneficial to adapting to different algorithm scenarios.

In one implementation scenario, the audio bus may include, but is not limited to, I2S (Inter-IC Sound, audio bus built in an integrated circuit), etc., and is not limited thereto. It should be noted that the standard I2S bus cable is composed of 3 serial conductors, one of which is a time division multiplexed data line, the other is a word select line, and the last is a clock line. The I2S bus interface may be connected as a CODEC interface to an external 16/20/24 bit stereo audio CODEC circuit (CODEC IC). It may support the I2S data format and the MSB-Justified data format. The I2S bus decouples to provide DMA (Direct Memory Access) transmission mode for the first-in-first-out queue Access instead of interrupt mode, and may send and receive data simultaneously or only send or receive data.

In one implementation scenario, data interface 122 may include, but is not limited to, an AXI-HP interface, or the like. In addition, the first configuration interface 123 may include, but is not limited to, an AXI-Lite interface, etc., and is not limited thereto.

In an implementation scenario, the transmission bus 12 may further include a second configuration interface 124, the data transceiver module 11 further includes a signal splitting module 113, the signal splitting module 113 includes a signal gathering terminal B1 and a plurality of signal splitting terminals B2, the signal gathering terminal B1 is connected to the second configuration interface 124, and the plurality of signal splitting terminals B2 are respectively connected to different audio transceiver modules 112, so as to configure the voice parameters of each audio transceiver module 112. It should be noted that the signal splitting module 113 is specifically configured to split the related signals sent by the main control module 13 to the audio transceiver module 112 into multiple paths, so that each audio transceiver module 112 can receive the signals. In addition, the specific meaning of the voice parameter may refer to the following description related to the audio transceiving method embodiment, which is not repeated herein. Therefore, the second configuration interface 124 and the signal splitting module 113 can configure the voice parameters of each audio transceiver module 112, which is beneficial to adapting to different algorithm scenarios.

In an implementation scenario, the data transceiving module 11 further includes a data scheduling module 114, the data scheduling module 114 includes a data collecting terminal C1 and a plurality of data splitting terminals C2, the data collecting terminal C1 is connected to the data interface 122, and the plurality of data splitting terminals C2 are respectively connected to different audio transceiving modules 112 to schedule data transceiving operations of the audio transceiving modules 112. Specifically, the number of data taps C2 included in the data scheduling module 114 may be equal to the number of the audio transceiving modules 112, or may be greater than the number of the audio transceiving modules 112.

In one implementation scenario, the data interface 122 is further coupled to the interrupt interface 131 of the main control module 13, and after the plurality of audio transceiving modules 112 complete data transmission, the data interface 122 generates an interrupt signal to notify the main control module 13 to perform a data processing operation through the interrupt interface 131. For details, reference may be made to the following description of the embodiments of the audio transceiving method, which is not repeated herein.

In one implementation scenario, the audio transceiver circuit 10 further includes a volatile storage medium 14, and the volatile storage medium 14 is connected to the transmission bus 12. In addition, when the audio transceiver module 112 receives the first audio data, the data interface 122 buffers the first audio data in the volatile storage medium 14, and the main control module 13 takes the first audio data from the volatile storage medium 14. Different from the audio receiving process, in the audio sending process, when the main control module 13 sends out the second audio data, the second audio data is buffered in the volatile storage medium 14 through the main control interface 121, and the audio transceiving module 112 takes away the second audio data from the volatile storage medium 14 through the data interface 122 and sends out the second audio data.

In a specific implementation scenario, the volatile storage medium 14 may include, but is not limited to, a DDR (Double Data Rate) or the like, such as DDR3, DDR4 or the like, which is not limited herein.

In a specific implementation scenario, each audio transceiver module 112 is respectively provided with different sequence bits, for example, the audio transceiver circuit 10 includes 16 audio transceiver modules 112, the sequence bit of the 1 st audio transceiver module 112 may be marked as 0, the sequence bit of the 2 nd audio transceiver module 112 may be marked as 1, and so on, which is not illustrated herein. On this basis, the storage address of each audio transceiver module 112 in the volatile storage medium 14 may be set, and the storage address is determined based on the base address, the address offset and the sequence of the audio transceiver module 112, and the address offset is related to the voice parameter configured by the audio transceiver module 112. It should be noted that the storage space may be continuous and may be recycled. Illustratively, taking a sampling time of 4ms, a sampling frequency of 16kHz, and a speech depth of 16 bits as an example, if the size of each path of speech data is 128 bytes, the address offset between each path of speech data can be determined to be 128. On this basis, the offset address of the storage space corresponding to the 1 st audio transceiver module 112 is 0 to 127, the offset address of the storage space corresponding to the 2 nd audio transceiver module 112 is 128 to 255, and so on, the offset address of the storage space corresponding to the nth audio transceiver module 112 is 128 x (n-1) to 128 x n-1. Referring to fig. 2, fig. 2 is a schematic diagram of a storage space of the volatile storage medium 14. After the current voice is taken, the next set of voices may be stored in the non-volatile storage medium 14 for cyclic multiplexing, again through the above steps, as shown in fig. 2.

In one implementation scenario, please refer to fig. 3 in combination, and fig. 3 is a schematic block diagram of an embodiment of the audio transceiver module 112. As shown in fig. 2, the audio transceiving module 112 includes a clock generating unit 1121, a serial-to-parallel converting unit 1122, and a parallel-to-serial converting unit 1123. Further, the clock generating unit 1121 includes a clock input terminal D1 and a clock output terminal D2, the clock input terminal D1 is connected to the output terminal a2 of the clock management module 111, the serial-to-parallel converting unit 1122 includes a first input terminal E1, a first output terminal E2 and a first clock configuration terminal E3, the first input terminal E1 is configured to be coupled to the sound pickup circuit, the first output terminal E2 is coupled to the data interface 122, and the first clock configuration terminal E3 is connected to the clock output terminal D2, the parallel-to-serial converting unit 1123 includes a second input terminal F1, a second output terminal F2 and a second clock configuration terminal F3, the second output terminal F2 is configured to be coupled to the speaker circuit, the second input terminal F1 is coupled to the data interface 122, and the second clock configuration terminal F3 is connected to the clock output terminal D2.

In a specific implementation scenario, as shown in fig. 3, the audio transceiver module 112 may further include a data reorganizing unit 1124, a ping-pong buffer unit 1125, a data distribution unit 1126, and a data buffer unit 1127. After the main control module 13 initializes the data transceiver module 11 through the transmission bus 12, each audio transceiver module 112 in the data transceiver module 11 can perform recording and broadcasting operations according to the set audio parameters. For a specific process, reference may be made to the following description.

In a specific implementation scenario, during recording, the serial-to-parallel conversion unit 1122 combines the received serial data into 16-24 bit parallel data, and divides the parallel data into left and right channel data through the data recombination unit 1124, and buffers the left and right channel data to the ping-pong buffer unit 1125 at the rear end, when the data amount in the ping-pong buffer unit 1125 reaches a preset threshold (e.g., 64), the data scheduling module 114 sends a request to the data scheduling module 114, and the data scheduling module 114 may schedule the data in the ping-pong buffer unit 1125 to the write port of the data interface 122 according to whether other audio transceiver modules 112 are waiting and the current queuing number of the audio transceiver module 112, so as to be buffered to the volatile storage medium 14. Further, after the transmission of the voice data of all the audio transceiver modules 112 is completed, an interrupt signal may be generated, and the main control module 13 is notified through the interrupt interface 131 to perform a data processing operation. In this case, the main control module 13 may take the audio data from the volatile storage medium 14 and perform further processing, such as sound source localization, dereverberation, speech enhancement, blind source separation, etc., without limitation.

In a specific implementation scenario, during broadcasting, the main control module 13 writes data to be broadcasted into the nonvolatile storage medium 14 and notifies the data transceiver module 11 to fetch the data, the multiple audio transceiver modules 112 read the data from the nonvolatile storage medium 14 through the data interface 122 and write the data into the data cache unit 1127, and further determines that the data cache unit 1127 is not empty through the data distribution unit 1126, and divides the read data into two channels, i.e., a left channel and a right channel, and transmits the channel to the parallel-serial conversion unit 1123, and converts the channel into a serial data stream to be output, thereby completing the broadcasting operation.

In one implementation scenario, the clock management module 111 further includes an input terminal a3 for connecting with an external crystal oscillator.

In one implementation scenario, the data transceiving module 11 is an IP core (i.e., an intellectual property core) so that the use can be authorized.

In an implementation scenario, the audio transceiver circuit 10 is implemented by a Programmable System On Chip (PSOC), the data transceiver module 11 is implemented by a Programmable Logic (PL) portion of the PSOC, the main control module 13 is implemented by a Processing System (PS) portion of the PSOC, and the transmission bus 12 is implemented by an on-Chip bus of the PSOC. Illustratively, the on-chip bus may include, but is not limited to AXI, etc., and is not limited thereto. Therefore, the PS-side high-end processor (such as the dual-core ARM core A9 inner core) can support complex speech processing algorithms such as speech recognition, synthesis, enhancement and data exchange of multi-member conversation, and is beneficial to improving universality and flexibility. In addition, since the PSOC platform usually has rich interfaces, such as a Network port, a USB (Universal Serial Bus), a Serial port, a CAN (Controller Area Network), a PCIE (Peripheral Component Interconnect Express, high speed Serial computer extended Bus standard), and a SRIO (Serial Rapid I/O), the PSOC platform CAN be applied to different scenarios, i.e., CAN be used as a plug-in card, and CAN also be used as an independent board with a dedicated function.

In a specific implementation scenario, the audio transceiver circuit 10 may be specifically implemented based on, for example, a Xilinx core board, the size of which is not more than 40mm × 35mm, and may implement 5 16I 2S IP core functions, and the hardware cost of the core board is low, so that it is beneficial to reduce the hardware cost, and simultaneously reduce the hardware size and the hardware power consumption.

In a specific implementation scenario, the IP core may also be implemented in any FPGA (Field Programmable Gate Array), or may also be embedded in a general-purpose processor as a dedicated hard core stream chip.

In one implementation scenario, the audio transceiver circuit 10 may further include an audio noise reduction module (not shown) for performing noise reduction processing on the picked-up audio data, and after the noise reduction processing, the audio transceiver module 112 continues to transmit the audio data to the volatile storage medium 14 through the data scheduling module 114 and the data interface 122.

In the above solution, the audio transceiver circuit 10 includes a data transceiver module 11, a transmission bus 12 and a main control module 13, the data transceiver module 11 includes a clock management module 111 and a plurality of audio transceiver modules 112 disposed in parallel, the audio transceiver modules 112 are configured to be coupled to a sound pickup circuit and/or a speaker circuit through an audio bus, an output a1 of the clock management module 111 is connected to each of the audio transceiver modules 112 to synchronize clock parameters of each of the audio transceiver modules 112, the transmission bus 12 includes a main control interface 121, a data interface 122 and a first configuration interface 123, the plurality of audio transceiver modules 112 are coupled to the data interface 122, a configuration end a2 of the clock management module 111 is connected to the first configuration interface 123, the main control module 13 is connected to the main control interface 121 to implement data communication with the data transceiver module 11 through the main control interface 121, on one hand, through the main control interface 121 and the data interface 122 of the transmission bus 12, on the other hand, the clock parameters of the audio transceiver modules 112 can be synchronized through the main control interface 121 and the first configuration interface 123 of the transmission bus 12, so that data synchronization and alignment of all channels can be realized.

Referring to fig. 4, fig. 4 is a block diagram of a multimedia device 40 according to an embodiment of the present application. The multimedia device 40 includes: the sound pickup circuit 41, the speaker circuit 42, and the audio transceiving circuit 43 in any of the above-mentioned embodiments, and the sound pickup circuit 41 and the speaker circuit 42 are coupled to the audio transceiving circuit 43 through an audio bus (e.g., I2S). In addition, the multimedia device 40 may include a plurality (e.g., 2, 3, 4, 5, etc.) of sound pickup circuits 41; the multimedia device 40 may also include a plurality (e.g., 2, 3, 4, 5, etc.) of speaker circuits 42. Pickup circuit 41 may include, but is not limited to: a fully directional microphone, a uni-directional microphone, etc., and is not limited herein. The speaker circuit 42 may include, but is not limited to, a hi-fi speaker, etc., and is not limited thereto. It should be noted that the multimedia device 40 may include, but is not limited to: airplane traffic equipment, conference session equipment, etc., without limitation.

In the above solution, the multimedia device 40 includes the sound pickup circuit 41, the speaker circuit 42, and the audio transceiving circuit 43 in any of the above disclosed embodiments, so that all channel data can be synchronized and aligned, which is beneficial to improving the quality of the voice conversation.

Referring to fig. 5, fig. 5 is a flowchart illustrating an audio transceiving method according to an embodiment of the present application. The embodiments of the present disclosure are specifically applied to the audio transceiver circuit in any of the above-mentioned embodiments, and reference may be specifically made to the relevant description in the foregoing embodiments, which is not repeated herein. Specifically, the embodiments of the present disclosure may include the following steps:

step S51: the master control module synchronizes the clock parameters of each audio transceiving module through the transmission bus.

In an implementation scenario, after the audio transceiver circuit is powered on, an initialization operation may be performed, at this time, the main control module may send the clock parameter of the audio transceiver module from the first configuration interface to the clock management module through the main control interface via the transmission bus, and the clock management module may synchronize the audio transceiver modules after receiving the clock parameter.

In a specific implementation scenario, the clock parameter may include, but is not limited to, a frequency division coefficient CLK _ DIV, etc., and is not limited herein. Taking the example that the clock parameter includes a frequency division coefficient, the frequency of the external clock can be divided according to the frequency division coefficient CLK _ DIV, and the divided frequency is used as the clock frequency of the audio transceiver module. Other cases may be analogized, and no one example is given here.

In an implementation scenario, in addition to the synchronous clock parameter, the main control module may configure the voice parameters of each audio transceiving module through the transmission bus based on the audio transceiving task, and the voice parameters include a first parameter when the audio transceiving task is an audio receiving task, and the voice parameters include a second parameter when the audio transceiving task is an audio sending task, and the first parameter and the second parameter are not completely the same. In the mode, the voice parameters of the audio receiving and sending module are configured based on the audio receiving and sending task, and the first parameters under the audio receiving task and the second parameters under the audio sending task are not identical, so that the voice parameters can be configured in a self-defined mode according to the specific task, and the accuracy and the flexibility of the voice parameters are improved.

In a specific implementation scenario, the first parameter includes at least one of: the input channel selection parameter (REG _ AUD _ IN _ CHN _ SEL), the effective number of input channels (VALID _ CHN _ IN _ NUM), the input DATA length (AUD _ IN _ DATA _ SIZE), the sampling frequency (SAMPLE _ FREQ), and the like, which are not limited herein. It should be noted that the input channel selection parameter indicates which audio transceiver module is selected to pick up audio, the effective number of input channels indicates the number of audio transceiver modules that effectively pick up audio, the length of input data indicates the number of sampling points (e.g., 64, 256, etc.) of one data, and the sampling frequency indicates the audio sampling frequency (e.g., 16kHz, etc.). In the above manner, the configuring the first parameter includes at least one of: the input channel selection parameters, the effective number of the input channels, the input data length and the sampling frequency can be beneficial to improving the configuration flexibility of the audio receiving and transmitting module.

In a specific implementation scenario, the second parameter includes at least one of: an output channel selection parameter (AUD _ OUT _ CHN _ SEL), an output DATA length (AUD _ OUT _ DATA _ SIZE), and a transfer bus grant status (AUD _ OUT _ XFEN). It should be noted that, the meanings of the output data length and the output channel selection parameter may refer to the meanings of the input data length and the input channel selection parameter, which are not described herein again. Further, the transfer bus permission state indicates whether or not the current transfer bus is in a state of being permitted to be used. In the above manner, the configuring the second parameter includes at least one of: the selection parameters of the output channel, the length of the output data and the permission state of the transmission bus can be beneficial to improving the configuration flexibility of the audio receiving and transmitting module.

In an implementation scenario, after initialization, the main control module may further configure whether the picked-up audio data needs to be subjected to noise reduction first, and if the picked-up audio data needs to be subjected to noise reduction first, the picked-up audio data may be subjected to noise reduction by the audio noise reduction module of the audio hand transceiver circuit.

Step S52: based on the audio receiving and sending task, the first audio data received by each audio receiving and sending module is obtained through the transmission bus, and/or second audio data is prepared and taken away by each audio receiving and sending module through the transmission bus and sent out.

In an implementation scenario, when the audio transceiving task is an audio receiving task, it may be determined whether an interrupt signal is detected at the interrupt interface, and if not, the step of determining whether the interrupt signal is detected at the interrupt interface is executed again until the interrupt signal is detected at the interrupt interface, otherwise, if it is determined that the interrupt signal is detected, it may be determined that each audio transceiving module has passed through the transmission bus, the first audio data is buffered in the nonvolatile storage medium, the first audio data is taken away from the nonvolatile storage medium through the transmission bus, and the step of determining whether the interrupt signal is detected at the interrupt interface and subsequent steps are executed again. It should be noted that the first audio data is audio data obtained by performing operations such as serial-to-parallel conversion and data reassembly on the picked audio of the audio transceiver module, and specific reference may be made to the foregoing description about the audio transceiver module, which is not described herein again. In the above manner, under the condition that the audio receiving and sending task is the audio receiving task, whether the interrupt signal is detected through detecting the interrupt interface to determine whether the first audio data is transmitted to the volatile storage medium through the transmission bus is favorable for improving the robustness and the orderliness for receiving the audio, and the efficiency for receiving the audio is improved.

In one implementation scenario, in the case that the audio transceiving task is an audio issuing task, the second audio data may be buffered to the volatile storage medium through the transmission bus, and the preparation completion field is set to a first value, and each audio transceiving module, in the case that it detects that the preparation completion field is a first value (e.g., 1), takes the second audio data from the volatile storage medium through the transmission bus and issues the second audio data, and resets the preparation completion field to a second value (e.g., 0). It should be noted that, in the audio sending process, once the main control module detects that the preparation completion field is reset to the second numerical value, the new second audio data may be buffered to the volatile storage medium through the transmission bus again, and the preparation completion field is reset to the first numerical value again, so that the audio transceiver module can continuously take the second audio data from the volatile storage medium. In the above manner, when the audio transceiving task is an audio sending task, the second audio data is cached to the volatile storage medium through the transmission bus, the preparation completion field is set to be a first numerical value, and each audio transceiving module takes away and sends the second audio data from the volatile storage medium through the transmission bus and resets the preparation completion field to be a second numerical value when detecting that the preparation completion field is the first numerical value.

It should be noted that, in a real-world scene, the audio transceiving task may be any one of an audio receiving task and an audio sending task, and of course, the audio transceiving task may also include both the audio receiving task and the audio sending task, which is not limited herein.

According to the scheme, the master control module synchronizes the clock parameters of the audio transceiver modules through the transmission bus, acquires the first audio data received by the audio transceiver modules through the transmission bus and/or prepares the second audio data based on the audio transceiver tasks, and the audio transceiver modules take away and send the second audio data through the transmission bus, so that the synchronization and alignment of all channel data can be realized.

Referring to fig. 6, fig. 6 is a schematic block diagram of an embodiment of an audio transceiver 60 according to the present application. The audio transceiver 60 is integrated in the audio transceiver circuit in any of the above-mentioned embodiments, and specific reference may be made to the related description in the above-mentioned embodiments, which is not repeated herein. The audio transceiver 60 includes: the clock synchronization module 61, the data transmission module 62 and the clock synchronization module 61 are used for driving the master control module to synchronize the clock parameters of the audio transceiver modules through the transmission bus; and the data transmission module 62 is used for driving the main control module to acquire the first audio data received by each audio transceiver module through the transmission bus based on the audio transceiving task and/or prepare second audio data, and the second audio data is taken away and sent out by each audio transceiver module through the transmission bus.

In some disclosed embodiments, the audio transceiver 60 includes a parameter configuration module, configured to configure the voice parameters of each audio transceiver module through the transmission bus based on the audio transceiving task; the voice parameters comprise first parameters under the condition that the audio receiving and sending task is an audio receiving task, and the voice parameters comprise second parameters under the condition that the audio receiving and sending task is an audio sending task, wherein the first parameters and the second parameters are not completely the same.

Therefore, the voice parameters of the audio transceiving module are configured based on the audio transceiving task, and the first parameters under the audio receiving task and the second parameters under the audio sending task are not completely the same, so that the voice parameters can be configured in a self-defined manner according to the specific task, and the accuracy and the flexibility of the voice parameters are improved.

In some disclosed embodiments, the first parameter includes at least one of: the input channel selection parameter, the input channel effective number, the input data length, the sampling frequency, and/or the second parameter comprises at least one of: output channel selection parameters, output data length and transmission bus permission state.

Thus, by configuring the first parameter includes at least one of: the input channel selection parameters, the effective number of the input channels, the input data length and the sampling frequency can be beneficial to improving the configuration flexibility of the audio transceiving module, and the configuration of the second parameter comprises at least one of the following parameters: the selection parameters of the output channel, the length of the output data and the permission state of the transmission bus can be beneficial to improving the configuration flexibility of the audio receiving and transmitting module.

In some disclosed embodiments, the data transmission module 62 includes an audio receiving sub-module, specifically configured to obtain first audio data received by each audio transceiver module through the transmission bus, where the audio receiving sub-module includes a determining unit configured to determine whether an interrupt signal is detected at an interrupt interface; the audio receiving submodule comprises a first circulation unit, a reading unit and a second circulation unit, wherein the first circulation unit is used for combining the judging unit to execute the step of judging whether the interrupt signal is detected at the interrupt interface again under the condition that the interrupt signal is not detected, the reading unit is used for determining that each audio receiving and sending module passes through a transmission bus, caching first audio data to a nonvolatile storage medium and taking the first audio data from the nonvolatile storage medium through the transmission bus under the condition that the interrupt signal is detected, and the second circulation unit is used for combining the judging unit, the first circulation unit and the reading unit to execute the step of judging whether the interrupt signal is detected at the interrupt interface again and the subsequent steps.

Therefore, under the condition that the audio receiving and sending task is the audio receiving task, whether the first audio data are transmitted to the volatile storage medium through the transmission bus is determined by detecting whether the interrupt signal is detected at the interrupt interface, robustness and orderliness for receiving the audio are improved, and the audio receiving efficiency is improved.

In some disclosed embodiments, the data transmission module 62 includes an audio sending sub-module, specifically configured to prepare second audio data, and each audio transceiver module takes away and sends the second audio data through the transmission bus, where the audio sending sub-module includes a buffer unit configured to buffer the second audio data to a volatile storage medium through the transmission bus; the audio emission submodule comprises a setting unit, a processing unit and a processing unit, wherein the setting unit is used for setting a preparation completion field to be a first numerical value; and under the condition that each audio transceiver module detects that the preparation completion field is the first numerical value, taking the second audio data from the volatile storage medium through the transmission bus, sending the second audio data out, and resetting the preparation completion field to be the second numerical value.

Therefore, under the condition that the audio transceiving task is an audio sending task, the second audio data are cached to the volatile storage medium through the transmission bus, the preparation completion field is set to be a first numerical value, and each audio transceiving module takes away and sends the second audio data from the volatile storage medium through the transmission bus and resets the preparation completion field to be a second numerical value under the condition that the preparation completion field is detected to be the first numerical value, so that the robustness and the orderliness of audio sending are improved, and the audio sending efficiency is improved.

Referring to fig. 7, fig. 7 is a block diagram illustrating an embodiment of a computer readable storage medium 70 according to the present application. The computer readable storage medium 70 stores program instructions 71 capable of being executed by the processor, the program instructions 71 being configured to implement the steps in any of the above-described embodiments of the audio transceiving method.

According to the scheme, on one hand, unified data receiving and dispatching of the plurality of audio receiving and dispatching modules can be achieved beneficially through the main control interface and the data interface of the transmission bus, on the other hand, clock parameters of the audio receiving and dispatching modules can be synchronized through the main control interface and the first configuration interface of the transmission bus, and therefore synchronization and alignment of all channel data can be achieved.

In some embodiments, functions of or modules included in the apparatus provided in the embodiments of the present disclosure may be used to execute the method described in the above method embodiments, and specific implementation thereof may refer to the description of the above method embodiments, and for brevity, will not be described again here.

The foregoing description of the various embodiments is intended to highlight various differences between the embodiments, and the same or similar parts may be referred to each other, and for brevity, will not be described again herein.

In the several embodiments provided in the present application, it should be understood that the disclosed method and apparatus may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, a division of a module or a unit is merely a logical division, and an actual implementation may have another division, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some interfaces, and may be in an electrical, mechanical or other form.

Units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be substantially implemented or contributed to by the prior art, or all or part of the technical solution may be embodied in a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, a network device, or the like) or a processor (processor) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

Claims

1. An audio transceiving circuit, comprising:

the data transceiving module comprises a clock management module and a plurality of audio transceiving modules arranged in parallel, the audio transceiving modules are coupled to the pickup circuit and/or the loudspeaker circuit through an audio bus, and the output end of the clock management module is connected to each audio transceiving module so as to synchronize the clock parameters of each audio transceiving module;

the transmission bus comprises a master control interface, a data interface and a first configuration interface, the plurality of audio receiving and transmitting modules are coupled to the data interface, and the configuration end of the clock management module is connected to the first configuration interface;

and the main control module is connected to the main control interface so as to realize data intercommunication with the data transceiving module through the main control interface.

2. The circuit according to claim 1, wherein the transmission bus further includes a second configuration interface, the data transceiver module further includes a signal splitting module, the signal splitting module includes a signal gathering terminal and a plurality of signal splitting terminals, the signal gathering terminal is connected to the second configuration interface, and the plurality of signal splitting terminals are respectively connected to different audio transceiver modules to configure the voice parameters of the audio transceiver modules.

3. The circuit of claim 1, wherein the data transceiver module further comprises a data scheduling module, the data scheduling module comprises a data gathering terminal and a plurality of data splitting terminals, the data gathering terminal is connected to the data interface, and the data splitting terminals are respectively connected to different audio transceiver modules to schedule data transceiving operations of the audio transceiver modules.

4. The circuit of claim 1, wherein the data interface is further coupled to an interrupt interface of the main control module, and after the plurality of audio transceiver modules complete data transmission, an interrupt signal is generated at the data interface to notify the main control module of executing a data processing operation through the interrupt interface.

5. The circuit of claim 1, wherein the audio transceiver module comprises:

the clock generation unit comprises a clock input end and a clock output end, and the clock input end is connected with the output end of the clock management module;

the serial-parallel conversion unit comprises a first input end, a first output end and a first clock configuration end, wherein the first input end is used for being coupled to the pickup circuit, the first output end is coupled to the data interface, and the first clock configuration end is connected with the clock output end;

and the parallel-serial conversion unit comprises a second input end, a second output end and a second clock configuration end, wherein the second output end is used for being coupled to the loudspeaker circuit, the second input end is coupled to the data interface, and the second clock configuration end is connected with the clock output end.

6. The circuit of claim 1, wherein the clock management module further comprises an input for connection to an external crystal oscillator.

7. The circuit of claim 1, wherein the data transceiver module is an IP core.

8. The circuit of claim 1, wherein the audio transceiver circuit further comprises a volatile storage medium, the volatile storage medium being coupled to the transmission bus;

when receiving first audio data, the audio transceiver module caches the first audio data in the volatile storage medium through the data interface, the main control module takes the first audio data away from the volatile storage medium, and/or when sending second audio data, the main control module caches the second audio data in the volatile storage medium through the main control interface, and the audio transceiver module takes the second audio data away from the volatile storage medium through the data interface and sends the second audio data.

9. The circuit of claim 8, wherein each of the audio transceiver modules is provided with a different sequence bit, and a storage address is respectively corresponding to the volatile storage medium, the storage address is determined based on a base address, an address offset and the sequence bit of the audio transceiver module, and the address offset is related to the voice parameter configured by the audio transceiver module.

10. The circuit according to any one of claims 1 to 9, wherein the audio transceiver circuit is implemented by a system-on-programmable chip, the data transceiver module is implemented by a programmable logic portion of the system-on-programmable chip, the main control module is implemented by a processing system portion of the system-on-programmable chip, and the transmission bus is implemented by an on-chip bus of the system-on-programmable chip.

11. A multimedia device, comprising: a sound pickup circuit, a speaker circuit, and an audio transceiving circuit according to any one of claims 1 to 10;

the sound pickup circuit and the loudspeaker circuit are coupled to the audio transceiving circuit through an audio bus.

12. An audio transceiving method applied to the audio transceiving circuit according to any one of claims 1 to 10, the audio transceiving method comprising:

the master control module synchronizes clock parameters of each audio transceiving module through a transmission bus;

based on an audio receiving and sending task, first audio data received by each audio receiving and sending module is obtained through the transmission bus, and/or second audio data is prepared, and each audio receiving and sending module takes away and sends the second audio data through the transmission bus.

13. The method according to claim 12, wherein before the audio transceiving task acquires the first audio data received by each of the audio transceiving modules through the transmission bus and/or prepares second audio data, and the audio transceiving modules take and send out the second audio data through the transmission bus, the method further comprises:

configuring voice parameters of each audio transceiving module through the transmission bus based on the audio transceiving task;

the voice parameters comprise first parameters under the condition that the audio receiving and sending task is an audio receiving task, and the voice parameters comprise second parameters under the condition that the audio receiving and sending task is an audio sending task, wherein the first parameters and the second parameters are not completely the same.

14. The method of claim 13, wherein the first parameter comprises at least one of: input channel selection parameters, effective number of input channels, input data length and sampling frequency,

and/or, the second parameter comprises at least one of: output channel selection parameters, output data length and transmission bus permission state.

15. The method according to claim 12, wherein said obtaining the first audio data collected by each of the audio transceiver modules via the transmission bus comprises:

judging whether an interrupt signal is detected at an interrupt interface;

if not, re-executing the step of judging whether the interrupt signal is detected at the interrupt interface;

if the first audio data is detected, determining that each audio transceiver module passes through the transmission bus, caching the first audio data to a nonvolatile storage medium, taking the first audio data from the nonvolatile storage medium through the transmission bus, and re-executing the step of judging whether an interrupt signal is detected at an interrupt interface and the subsequent steps.

16. The method of claim 12, wherein the preparing second audio data comprises:

buffering the second audio data to a volatile storage medium via the transmission bus;

the taking away and sending out the second audio data by each audio transceiver module through the transmission bus comprises:

setting the preparation completion field to a first value; and under the condition that each audio transceiver module detects that the preparation completion field is a first numerical value, taking away and sending out the second audio data from the volatile storage medium through the transmission bus, and resetting the preparation completion field to be a second numerical value.

17. An audio transceiving apparatus integrated with the audio transceiving circuit according to any one of claims 1 to 10, the audio transceiving apparatus comprising:

the clock synchronization module is used for driving the main control module to synchronize the clock parameters of the audio receiving and transmitting modules through the transmission bus;

and the data transmission module is used for driving the main control module to acquire the first audio data received by each audio transceiver module through the transmission bus based on the audio transceiving task and/or prepare second audio data, and each audio transceiver module takes away and sends the second audio data through the transmission bus.

18. A computer-readable storage medium, in which program instructions executable by a processor are stored, the program instructions being for implementing the audio transceiving method according to any one of claims 12 to 16.