CN114204523B - Chip protection circuit, system and method - Google Patents
Chip protection circuit, system and method Download PDFInfo
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- CN114204523B CN114204523B CN202111501518.XA CN202111501518A CN114204523B CN 114204523 B CN114204523 B CN 114204523B CN 202111501518 A CN202111501518 A CN 202111501518A CN 114204523 B CN114204523 B CN 114204523B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
- H02H7/20—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for electronic equipment
- H02H7/205—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for electronic equipment for controlled semi-conductors which are not included in a specific circuit arrangement
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
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Abstract
The embodiment of the application provides a protection circuit, a system and a method of a chip. The protection circuit of this chip includes: a switch unit and a control switch unit; the first end of the switch unit is electrically connected with a pin of the chip; the second end and the third end of the switch unit are respectively and electrically connected with the first floating voltage end and the second floating voltage end; the control switch unit is used for conducting a first end of the switch unit with a second end or a third end of the switch unit when the pin receives an electric signal, and the pin is conducted with a first voltage end and/or a second voltage end through at least one control switch module so as to discharge the electric signal; the first electrical signal is received by the pin, the second electrical signal is received by both the pin and the first voltage terminal, and the third electrical signal is received by both the pin and the second voltage terminal. The embodiment of the application can have the protection function of EOS and ESD, so that pins and a protection circuit can be better protected, and the protection of a chip is realized.
Description
Technical Field
The present application relates to the field of chip protection circuits, and in particular, to a chip protection circuit, system and method.
Background
For decades, EOS (ELectrical Over Stress) has been a problem in electronic devices, circuits and systems, and has been a problem to be solved as early as the 20 th century, 70 s and continuing to date. Various fields of consumption, industry, aerospace, military and medical care are affected by this problem. Equipment manufacturers, suppliers, assembly and field engineers all experience EOS failures.
In recent years, electrostatic protection has been widely applied to display devices, power management devices, driving devices, automotive electronics, and the like, and plays an important role in our daily life.
However, when the pin of the chip has an EOS protection requirement, because the duration of the EOS event is too long, generally microsecond, it will have a fatal influence on a nanosecond ESD (Electro-Static Discharge) protection circuit, and the ESD protection of the protection circuit will be damaged under such a large amount of energy. Therefore, the protection circuit of the conventional chip cannot protect both EOS and ESD.
Disclosure of Invention
The application provides a protection circuit, a system and a method of a chip aiming at the defects of the existing mode, and aims to solve the technical problem that the existing protection circuit of the chip cannot simultaneously have EOS and ESD protection.
In a first aspect, an embodiment of the present application provides a protection circuit for a chip, including: a switch unit and a control switch unit;
the first end of the switch unit is electrically connected with a pin of the chip; the second end and the third end of the switch unit are respectively and electrically connected with the first floating voltage end and the second floating voltage end;
the control switch unit comprises at least three control switch modules, at least one control switch module is electrically connected with the first floating voltage end, and at least one control switch module is electrically connected with the second floating end;
the control switch unit is used for conducting a first end of the switch unit with a second end or a third end of the switch unit when the pin receives an electric signal, and the pin is conducted with a first voltage end and/or a second voltage end through at least one control switch module so as to discharge the electric signal; the electrical signal comprises at least one of: a first electrical signal, a second electrical signal, a third electrical signal; the first electrical signal is received by the pin, the second electrical signal is received by both the pin and the first voltage terminal, and the third electrical signal is received by both the pin and the second voltage terminal.
In one possible implementation manner, in the at least three control switch modules, a first end and a second end of at least one control switch module are respectively and electrically connected with the first floating voltage end and the second voltage end; the first end and the second end of the at least one control switch module are respectively and electrically connected with the first voltage end and the second floating voltage end; and the first end and the second end of the at least one control switch module are respectively and electrically connected with the first voltage end and the second voltage end.
In one possible implementation, the control switch unit includes a first control switch module, a second control switch module, and a third control switch module;
the first control switch module, the second control switch module and the third control switch module are respectively a control switch unit.
In one possible implementation manner, the first end and the second end of the first control switch module are respectively electrically connected with the first floating voltage end and the second voltage end;
the first end and the second end of the second control switch module are respectively and electrically connected with the first voltage end and the second floating voltage end;
the first end and the second end of the third control switch module are respectively and electrically connected with the first voltage end and the second voltage end.
In one possible implementation, the switching unit includes a first switching module and a second switching module;
the first end of the first switch module and the first end of the second switch module are jointly used as the first end of the switch unit;
the second end of the first switch module is used as the second end of the switch unit;
and the second end of the second switch module is used as the third end of the switch unit.
In one possible implementation manner, the control switch module comprises a silicon controlled module, and a first end and a second end of the silicon controlled module are respectively used as a first end and a second end of the control switch module; or the like, or, alternatively,
the control switch module comprises a first parasitic switch device; a first end of the first parasitic switching device is used as a first end of the control switch module; and the second end and the control end of the first parasitic switching device are jointly used as the second end of the control switch module.
In one possible implementation, the control switch module includes a first switch device, an inversion module, and a second parasitic switch device;
the control end of the first switch device, the second end of the reverse module and the first end of the second parasitic switch device are jointly used as the first end of the control switch module;
the first end and the second end of the first switch device, the third end of the reverse module and the second end of the second parasitic switch device are jointly used as the second end of the control switch module;
and the first end and the fourth end of the reverse module are respectively and electrically connected with the control end of the first switching device and the control end of the second parasitic switching device.
In a second aspect, an embodiment of the present application provides a chip protection system, including: a chip and a guard circuit of the chip of the first aspect;
the chip comprises a plurality of pins;
each pin is electrically connected with a first end of a switch unit of the protection circuit of one chip.
In a third aspect, an embodiment of the present application provides a chip protection method, which is applied to the chip protection circuit of the first aspect, and includes:
when the pin of the chip receives an electric signal, the first end of the switch unit is conducted with the second end or the third end of the switch unit, and the pin is conducted with the first voltage end and/or the second voltage end through at least one control switch module so as to discharge the electric signal; the electrical signal comprises at least one of: a first electrical signal, a second electrical signal, a third electrical signal; the first electrical signal is received by the pin, the second electrical signal is received by both the pin and the first voltage terminal, and the third electrical signal is received by both the pin and the second voltage terminal.
In one possible implementation manner, when the pin receives an electrical signal, the first terminal of the switching unit is conducted with the second terminal or the third terminal of the switching unit, and the pin is conducted with the first voltage terminal and/or the second voltage terminal through at least one control switch module to discharge the electrical signal, where the method includes at least one of:
when the pin receives a first electric signal, the first end of the switch unit is conducted with the second end or the third end of the switch unit, and the pin is conducted with the first voltage end or the second voltage end through at least one control switch module so as to discharge the first electric signal;
when the pin and the first voltage end both receive the second electric signal, the first end of the switch unit is conducted with the second end or the third end of the switch unit, and the pin is conducted with the first voltage end through at least one control switch module so as to discharge the second electric signal;
when the pin and the second voltage end both receive the third electric signal, the first end of the switch unit is conducted with the second end or the third end of the switch unit, and the pin is conducted with the second voltage end through at least one control switch module so as to discharge the third electric signal.
In a possible implementation manner, when the pin receives the first electrical signal, the first end of the switch unit is conducted with the second end or the third end of the switch unit, and the pin is conducted with the first voltage end or the second voltage end through at least one control switch module to discharge the first electrical signal, including:
when the pin receives the first positive voltage signal, the first end and the second end of the switch unit are conducted, and the pin is conducted with the second voltage end through the first control switch module so as to discharge the first positive voltage signal; the first electrical signal is a first positive voltage signal; and/or the presence of a gas in the gas,
when the pin receives the first negative voltage signal, the first end and the third end of the switch unit are conducted, and the pin is conducted with the first voltage end through the second control switch module so as to discharge the first negative voltage signal; the first electrical signal is a first negative voltage signal.
In a possible implementation manner, when the pin and the first voltage end both receive the second electrical signal, the first end of the switch unit is conducted with the second end or the third end of the switch unit, and the pin is conducted with the first voltage end through at least one control switch module to discharge the second electrical signal, including:
when the pin and the first voltage end receive the second positive voltage signal, the first end and the second end of the switch unit are conducted, and the pin is conducted with the first voltage end through the first control switch module and the third control switch module so as to discharge the second positive voltage signal; the second electric signal is a second positive voltage signal; and/or the presence of a gas in the gas,
when the pin and the first voltage end receive the second negative voltage signal, the first end and the third end of the switch unit are conducted, and the pin is conducted with the first voltage end through the second control switch module so as to discharge the second negative voltage signal; the second electrical signal is a second negative pressure signal.
In one possible implementation manner, when the pin and the second voltage end both receive the third electrical signal, the first end of the switch unit is conducted with the second end or the third end of the switch unit, and the pin is conducted with the second voltage end through at least one control switch module to discharge the third electrical signal, including:
when the pin and the second voltage end receive the third positive voltage signal, the first end and the second end of the switch unit are conducted, and the pin is conducted with the second voltage end through the first control switch module so as to discharge the third positive voltage signal; the third electrical signal is a third positive voltage signal; and/or the presence of a gas in the gas,
when the pin and the second voltage end receive the third negative voltage signal, the first end and the third end of the switch unit are conducted, and the pin is conducted with the second voltage end through the second control switch module and the third control switch module so as to discharge the third negative voltage signal; the third electrical signal is a third negative pressure signal.
The beneficial technical effects brought by the technical scheme provided by the embodiment of the application comprise:
the second end of the switch unit of the protection circuit of chip of this application embodiment, the third end, respectively with first floating voltage end, the second floating voltage end is electric to be connected, the control switch unit includes at least three control switch module, at least one control switch module is connected with first floating voltage end electricity, thereby be connected the pin through floating voltage end and control switch module electricity, the first end and the switch unit second end or the third end of switch unit switch on, the pin switches on through at least one control switch module and first voltage end and/or second voltage end, can realize the bleeding of signal of telecommunication through the circuit structure that forms to switch on, thereby realize the safeguard function of chip.
Furthermore, the pin of the embodiment of the present application receives an electrical signal of at least one of: the protection circuit of the chip based on the embodiment of the application can realize the release of the EOS, thereby realizing the protection of the EOS, the second electric signal is received by the receiving pin and the first voltage end, the third electric signal is received by the receiving pin and the second voltage end, namely the electric signal of the ESD, the protection circuit of the chip based on the embodiment of the application can realize the release of the ESD, thereby realizing the protection of the ESD. Therefore, the protection circuit of the chip in the embodiment of the application can have the protection function of both EOS and ESD, so that the pin and the protection circuit can be better protected, and the protection of the chip is realized.
Additional aspects and advantages of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the present application.
Drawings
The foregoing and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
fig. 1 is a schematic structural diagram of an electrical connection between a protection circuit of a chip and a pin according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of an electrical connection between a protection circuit and a pin of another chip according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of an electrical connection between a protection circuit and a pin of another chip according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram illustrating an electrical connection between a protection circuit and a pin of another chip according to an embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of an electrical connection between a protection circuit of a chip and a pin according to an embodiment of the present disclosure.
Fig. 6 is a schematic structural diagram of an electrical connection of a chip protection system according to an embodiment of the present disclosure.
Reference numerals:
1-protection system of the chip;
10-protective circuit of chip, 20-chip.
100-switch unit, 110-first switch module, 120-second switch module;
200-control switch unit, 210-first control switch module, 220-second control switch module, 230-third control switch module, 240-first switch device, 250-reverse module, 260-second parasitic switch device;
300-pin.
Detailed Description
Reference will now be made in detail to the present application, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar parts or parts having the same or similar functions throughout. In addition, if a detailed description of the known art is not necessary for illustrating the features of the present application, it is omitted. The embodiments described below with reference to the drawings are exemplary only for the purpose of explaining the present application and are not to be construed as limiting the present application.
It will be understood by those within the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. Further, "connected" or "coupled" as used herein may include wirelessly connected or wirelessly coupled. As used herein, the term "and/or" includes all or any element and all combinations of one or more of the associated listed items.
The following describes the technical solutions of the present application and how to solve the above technical problems with specific embodiments.
An embodiment of the present application provides a protection circuit of a chip, as shown in fig. 1, the protection circuit of the chip includes: a switching unit 100 and a control switching unit 200.
The first end of the switch unit 100 is used for electrically connecting with the pin 300 of the chip; the second terminal and the third terminal of the switch unit 100 are electrically connected to the first floating voltage terminal and the second floating voltage terminal, respectively.
The control switch unit 200 includes at least three control switch modules, at least one of which is electrically connected to the first floating voltage terminal and at least one of which is electrically connected to the second floating terminal.
Optionally, referring to fig. 1, CLAMP2, and CLAMP3 represent three control switch modules, a connection between the Floating VDDIO BUS and the control switch module represents a first Floating voltage terminal, a connection between the Floating VSSIO BUS and the control switch module represents a second Floating voltage terminal, a connection between the VDDIO BUS and the control switch module represents a first voltage terminal, a connection between the VSSIO BUS and the control switch module represents a second voltage terminal, and IO (Input/Output) Pin represents a Pin 300, and corresponding representation relationships of the first Floating voltage terminal, the second Floating voltage terminal, the first voltage terminal, the second voltage terminal, and the Pin 300 in other figures in this application are the same as those in the embodiment shown in fig. 1, and will not be described again.
Referring to fig. 1, the control switch unit 200 is configured to, when the pin 300 receives an electrical signal, conduct a first end of the switch unit 100 with a second end or a third end of the switch unit 100, and conduct the pin 300 with a first voltage end and/or a second voltage end through at least one control switch module to discharge the electrical signal; the electrical signal comprises at least one of: a first electrical signal, a second electrical signal, a third electrical signal; a first electrical signal is received by pin 300, a second electrical signal is received by both pin 300 and the first voltage terminal, and a third electrical signal is received by both pin 300 and the second voltage terminal.
Optionally, the at least one control switch module is electrically connected to the first voltage terminal and the at least one control switch module is electrically connected to the two floating terminals.
Optionally, the first electrical signal is received by the pin 300, that is, an electrical signal of the EOS is received, so that the EOS can be discharged, thereby achieving protection of the EOS, the second electrical signal is received by the receiving pin 300 and the first voltage end, and the third electrical signal is received by the receiving pin 300 and the second voltage end, that is, an electrical signal of the ESD is received, thereby achieving discharge of the ESD, and thereby achieving protection of the ESD.
The inventor of the present application found through research that when the EOS discharges the first voltage terminal VDDIO BUS and the second voltage terminal VSSIO BUS, the duration is long, which may cause the diode to burn out, for example, when the EOS performs a positive voltage test on the first voltage terminal VDDIO BUS, the VDDIO BUS becomes 0V (volt), the EOS of the pin 300 is 8V, and the on-resistance of the first diode D1 is 1ohm (ohm), so that a large current of 8A (ampere) may be formed on the path to damage the whole path in a moment, and the protection structure of the existing circuit cannot prevent the EOS. Therefore, a new protection circuit for a chip capable of protecting against both EOS and ESD is needed.
The second end of the switch unit 100 of the protection circuit of the chip of the embodiment of the application, the third end, respectively with first floating voltage end, the second floating voltage end is electrically connected, the control switch unit 200 includes at least three control switch modules, at least one control switch module is electrically connected with first floating voltage end, thereby electrically connecting the pin with the control switch module through floating voltage end, the control switch unit 200 is used for when the pin 300 receives the electric signal like this, the first end of the switch unit 100 is conducted with the second end or the third end of the switch unit 100, the pin 300 is conducted with the first voltage end and/or the second voltage end through at least one control switch module, the discharge of the electric signal can be realized through the circuit structure that forms the conduction, thereby the protection function of the chip is realized. The protection circuit of the chip of the embodiment of the application can have the protection function of EOS and ESD at the same time, so that the pin 300 and the protection circuit can be better protected, and the chip can be protected.
Optionally, the first voltage terminal is connected to the power supply, and the second voltage terminal is connected to ground.
Optionally, the first floating voltage terminal and the second floating voltage terminal are used as buffer regions of the EOS, which are equivalent to wires, the first floating voltage terminal and the second floating voltage terminal are both floating voltage terminals, the voltage can be changed in a floating manner, and the addition of the first floating voltage terminal and the second floating voltage terminal facilitates EOS protection and better ESD protection.
Optionally, the electrical signal is a voltage or current signal.
In some embodiments, the first terminal and the second terminal of at least one of the at least three control switch modules are electrically connected to the first floating voltage terminal and the second voltage terminal, respectively. The first end and the second end of the at least one control switch module are respectively and electrically connected with the first voltage end and the second floating voltage end; and the first end and the second end of the at least one control switch module are respectively and electrically connected with the first voltage end and the second voltage end.
In the electrical connection relationship of the at least three control switch modules in the embodiment of the present application, the first floating voltage terminal or the second floating voltage terminal may be connected to the first voltage terminal or the second voltage terminal, respectively, so that the pin 300 may be electrically connected to the first voltage terminal or the second voltage terminal through the floating voltage terminal, and the electrical signal may be released through the control switch module.
In some embodiments, referring to fig. 1, the control switch unit 200 includes a first control switch module 210, a second control switch module 220, and a third control switch module 230.
The first end and the second end of the first control switch module 210 are electrically connected to the first floating voltage end and the second voltage end, respectively.
The first end and the second end of the second control switch module 220 are electrically connected to the first voltage end and the second floating voltage end, respectively.
The first terminal and the second terminal of the third control switch module 230 are electrically connected to the first voltage terminal and the second voltage terminal, respectively.
Optionally, referring to fig. 1, the first control switch module 210 is a first control switch module, i.e., CLAMP1; the second control switch module 220 is a second control switch module, i.e., CLAMP2; the third control switch module 230 is a third control switch module, i.e., CLAMP3.
In some embodiments, referring to fig. 2, the control switch module includes a thyristor module, and a first end and a second end of the thyristor module are respectively used as a first end and a second end of the control switch module.
Alternatively, as an example, referring to fig. 2, the embodiment shown in fig. 2 is different from the embodiment shown in fig. 1 in that: the silicon controlled modules include Silicon Controlled Rectifiers (SCR), the control switch unit 200 includes three Silicon Controlled Rectifiers (SCR) which are respectively a first SCR1, a second SCR2 and a third SCR3.
In some embodiments, the switching unit 100 includes a first switching module 110 and a second switching module 120.
The first terminal of the first switch module 110 and the first terminal of the second switch module 120 collectively serve as a first terminal of the switch unit 100.
The second terminal of the first switch module 110 serves as a second terminal of the switch unit 100.
And a second terminal of the second switch module 120 is used as a third terminal of the switch unit 100.
Alternatively, referring to fig. 1, the first switch module 110 includes a first diode D1, and the second switch module 120 includes a second diode D2; the anode and the cathode of the first diode D1 are the first end and the second end of the first switch module 110, respectively; the anode and the cathode of the second diode D2 are the second end and the first end of the second switch module 120, respectively.
Alternatively, referring to fig. 2, the embodiment shown in fig. 2 is the same as the first switch module 110 and the second switch module 120 of the embodiment shown in fig. 1, where the first switch module 110 includes a third diode D3, and the second switch module 120 includes a fourth diode D4. The anode and the cathode of the third diode D3 are the first end and the second end of the first switch module 110, respectively; the anode and the cathode of the fourth diode D4 are the second end and the first end of the second switch module 120, respectively.
Alternatively, referring to fig. 3, the embodiment shown in fig. 3 differs from the embodiment shown in fig. 1 in that: the first switch module 110 includes a third register switch device GDPMOS, and the second switch module 120 includes a fourth register switch device GGNMOS. The first end and the second end of the third register switch device GDPMOS are respectively used as the first end and the second end of the first switch module 110; the first terminal and the second terminal of the fourth register switch device GGNMOS are respectively used as the first terminal and the second terminal of the second switch module 120. The first switch module 110 further includes a first resistor R1, and the second switch module 120 further includes a second resistor R2.
Alternatively, referring to fig. 3, two ends of the first resistor R1 are electrically connected to the first floating voltage terminal and the control terminal of the third register switch device GDPMOS, respectively, and two ends of the second resistor R2 are electrically connected to the second floating voltage terminal and the control terminal of the fourth register switch device GGNMOS, respectively. The resistance values of the first resistor R1 and the second resistor R2 are determined according to the actual requirement of the circuit. The drain electrode and the source electrode of the third register switch device GDPMOS are respectively used as the first end and the second end of the third register switch device GDPMOS; and the drain electrode and the source electrode of the fourth registering switch device GGNMOS are respectively used as the first end and the second end of the fourth registering switch device GGNMOS.
Optionally, the third register switch device GDPMOS and the fourth register switch device GGNMOS are both parasitic structures, and the current direction is opposite to the current direction of the PMOS transistor and the current direction of the NMOS transistor.
In some embodiments, referring to fig. 4, the control switch module includes a first parasitic switching device; the first end of the first parasitic switching device is used as the first end of the control switching module; and the second end and the control end of the first parasitic switching device are jointly used as the second end of the control switch module.
Alternatively, as an example, referring to fig. 4, the embodiment shown in fig. 4 differs from the embodiment shown in fig. 1 in that: the first parasitic switching device includes a mos transistor, which is a metal-oxide-semiconductor (semiconductor) field effect transistor or referred to as a metal-insulator-semiconductor (insulator) transistor. In the embodiment of the present application, taking nmos as an example, the control switch unit 200 includes three first parasitic switch devices, which are respectively the first parasitic switch devices, i.e., GGNMOS2; a second first parasitic switching device, i.e., GGNMOS3; the third first parasitic switching device, GGNMOS4.
Optionally, the three first parasitic switching devices are all parasitic structures, and after being turned on, the three first parasitic switching devices are equivalent to wires, and current can flow in the forward direction and the reverse direction.
Optionally, referring to fig. 4, the control switch module further includes a resistor, and a resistance value of the resistor is designed according to actual circuit requirements. The first control switch module comprises a third resistor R3, and two ends of the third resistor R3 are respectively and electrically connected with the grid electrode and the second voltage end of the first parasitic switch device GGNMOS2; the second control switch module comprises a fourth resistor R4, and two ends of the fourth resistor R4 are respectively and electrically connected with the grid electrode of the second parasitic switch device GGNMOS3 and the second floating voltage end; the second control switch module comprises a fifth resistor R5, and two ends of the fifth resistor R5 are respectively and electrically connected with the grid electrode and the second voltage end of the third first parasitic switch device GGNMOS4.
Alternatively, referring to fig. 4, the drain and the source of the first parasitic switching device GGNMOS2 are respectively used as the first end and the second end of the first parasitic switching device; the drain electrode and the source electrode of the second first parasitic switching device GGNMOS3 are respectively used as the first end and the second end of the first parasitic switching device; and the drain and the source of the third first parasitic switching device GGNMOS4 are respectively used as the first end and the second end of the first parasitic switching device.
Alternatively, referring to fig. 4, the embodiment shown in fig. 4 is the same as the first switch module 110 and the second switch module 120 of the embodiment shown in fig. 1, where the first switch module 110 includes a fifth diode D5 and the second switch module 120 includes a sixth diode D6. An anode and a cathode of the fifth diode D5 are a first end and a second end of the first switch module 110, respectively; the anode and the cathode of the sixth diode D6 are the second end and the first end of the second switch module 120, respectively.
In some embodiments, referring to fig. 5, the control switch module includes a first switching device 240, an inversion module 250, and a second parasitic switching device 260.
The control terminal of the first switching device 240, the second terminal of the inversion module 250, and the first terminal of the second parasitic switching device 260 collectively serve as a first terminal of the control switching module.
The first terminal and the second terminal of the first switching device 240, the third terminal of the inversion module 250, and the second terminal of the second parasitic switching device 260 collectively serve as a second terminal of the control switching module.
The first terminal and the fourth terminal of the inversion module 250 are electrically connected to the control terminal of the first switching device 240 and the control terminal of the second parasitic switching device 260, respectively.
Optionally, referring to fig. 5, specific structures shown in the first control switch module 210, the second control switch module 220, and the third control switch module 230 correspond to CLAMP1, CLAMP2, and CLAMP3 in fig. 1 of the embodiment of the present application.
Optionally, referring to fig. 5, the first control switch module further includes a sixth resistor R6, the second control switch module further includes a seventh resistor R7, and the third control switch module further includes an eighth resistor R8. The sixth resistor R6, the seventh resistor R7 and the eighth resistor R8 are the same in electric connection principle, and the resistance values are determined according to actual requirements of the circuit. Two ends of the sixth resistor R6 are electrically connected to the first floating voltage end and the control end of the first switching device 240 of the first control switch module, two ends of the seventh resistor R7 are electrically connected to the first voltage end and the control end of the first switching device 240 of the second control switch module, and two ends of the eighth resistor R8 are electrically connected to the first voltage end and the control end of the first switching device 240 of the second control switch module, respectively.
Alternatively, referring to fig. 5, the first switching device 240 of the first control switching module is a switching device M1, the second parasitic switching device 260 of the first control switching module is a switching device M4, and the inverting module 250 of the first control switching module includes a switching device M2 and a switching device M3. The first switching device 240 of the second control switching module is switching device M5, the second parasitic switching device 260 of the second control switching module is switching device M8, and the inverting module 250 of the second control switching module includes switching device M6 and switching device M7. The first switching device 240 of the third control switching module is a switching device M9, the second parasitic switching device 260 of the third control switching module is a switching device M12, and the inverting module 250 of the third control switching module includes a switching device M10 and a switching device M11.
Optionally, the switching device M1, the switching device M4, the switching device M5, the switching device M8, the switching device M9, and the switching device M12 are nmos transistors, and a direction indicated by an arrow is a source. The switching device M4, the switching device M8 and the switching device M12 are all parasitic structures, are equivalent to wires after being conducted, and walk parasitic npn and diode respectively, so that current can flow in the forward direction and the reverse direction.
Optionally, the inverting module 250 includes an nmos transistor and a pmos transistor, taking the switching device M2 and the switching device M3 of the inverting module 250 of the first control switching module as an example, the switching device M2 is a pmos transistor, the switching device M3 is an nmos transistor, a control terminal of the switching device M2 is electrically connected to a control terminal of the switching device M3 and collectively serves as a first terminal of the inverting module 250, a first terminal of the switching device M2 is electrically connected to a first terminal of the switching device M3 and collectively serves as a third terminal of the inverting module 250; a second terminal of the switching device M2 as a second terminal of the inversion module 250; and a second terminal of the switching device M2 as a third terminal of the inverting module 250. The grid electrode of the switching device M2 is used as the control end of the switching device M2; the grid electrode of the switching device M3 is used as a control end of the switching device M3; the drain electrode and the source electrode of the switching device M3 are respectively used as a first end and a second end of the switching device M3; the drain and the source of the switching device M4 are respectively used as the first end and the second end of the switching device M4. The electrical connection relationship between the switching devices of the inversion module 250 of the second control switch module and the inversion module 250 of the third control switch module is the same as the electrical connection relationship between the inversion module 250 of the first control switch module in principle, and is not described herein again.
Optionally, the inverting module 250 is configured to invert the first level received by the first terminal of the inverting module 250 to a second level output by the fourth terminal of the inverting module 250. For example, the first terminal of the inversion module 250 receives a high level, and the fourth terminal of the inversion module 250 outputs a low level; the first terminal of the inversion block 250 receives a low level and the fourth terminal of the inversion block 250 outputs a high level.
Alternatively, referring to fig. 5, the embodiment shown in fig. 5 is the same as the first switch module 110 and the second switch module 120 of the embodiment shown in fig. 1, where the first switch module 110 includes a seventh diode D7, and the second switch module 120 includes an eighth diode D8. An anode and a cathode of the seventh diode D7 are a first end and a second end of the first switch module 110, respectively; the anode and the cathode of the eighth diode D8 are the second end and the first end of the second switch module 120, respectively.
Based on the same inventive concept, the embodiment of the present application provides a protection system for a chip, and referring to fig. 6, the protection system 1 for the chip includes: chip and guard circuit 10 of a chip of any embodiment of the present application.
The chip 20 includes a plurality of pins 300.
Each pin 300 is electrically connected to a first terminal of the switching unit 100 of the protection circuit of one chip 20.
Optionally, pins 300 include input pins and/or output pins of chip 20.
Alternatively, the pin 300 of the plurality of pins 300 of the chip 20, which receives the electrical signal of the EOS, is electrically connected to the first end of the switching unit 100 of the protection circuit of the chip 20.
Based on the same inventive concept, an embodiment of the present application provides a chip protection method, which is applied to a protection circuit of a chip 20 according to any embodiment of the present application, and as shown in fig. 6, the chip 20 protection method includes:
when the pin 300 of the chip 20 receives an electrical signal, the first terminal of the switching unit 100 is conducted with the second terminal or the third terminal of the switching unit 100, and the pin 300 is conducted with the first voltage terminal and/or the second voltage terminal through at least one control switch module to discharge the electrical signal; the electrical signal includes at least one of: a first electrical signal, a second electrical signal, a third electrical signal; a first electrical signal is received by pin 300, a second electrical signal is received by both pin 300 and the first voltage terminal, and a third electrical signal is received by both pin 300 and the second voltage terminal.
In some embodiments, when the pin 300 receives an electrical signal, the first terminal of the switching unit 100 is conducted with the second terminal or the third terminal of the switching unit 100, and the pin 300 is conducted with the first voltage terminal and/or the second voltage terminal through at least one control switch module to discharge the electrical signal, including at least one of:
when the pin 300 receives the first electrical signal, the first end of the switch unit 100 is conducted with the second end or the third end of the switch unit 100, and the pin 300 is conducted with the first voltage end or the second voltage end through at least one control switch module to discharge the first electrical signal;
when the pin 300 and the first voltage end both receive the second electrical signal, the first end of the switch unit 100 is conducted with the second end or the third end of the switch unit 100, and the pin 300 is conducted with the first voltage end through at least one control switch module to discharge the second electrical signal;
when the pin 300 and the second voltage terminal both receive the third electrical signal, the first terminal of the switch unit 100 is conducted with the second terminal or the third terminal of the switch unit 100, and the pin 300 is conducted with the second voltage terminal through at least one control switch module to discharge the third electrical signal.
In some embodiments, when the pin 300 receives the first electrical signal, the first terminal of the switch unit 100 is conducted with the second terminal or the third terminal of the switch unit 100, and the pin 300 is conducted with the first voltage terminal or the second voltage terminal through at least one control switch module to bleed off the first electrical signal, including:
when the pin 300 receives the first positive voltage signal, the first end and the second end of the switch unit 100 are conducted, and the pin 300 is conducted with the second voltage end through the first control switch module 210 to release the first positive voltage signal; the first electrical signal is a first positive voltage signal; and/or the presence of a gas in the atmosphere,
when the pin 300 receives the first negative voltage signal, the first terminal and the third terminal of the switching unit 100 are conducted, and the pin 300 is conducted with the first voltage terminal through the second control switch module 220 to discharge the first negative voltage signal; the first electrical signal is a first negative voltage signal.
In some embodiments, when the pin 300 and the first voltage terminal both receive the second electrical signal, the first terminal of the switching unit 100 is conducted with the second terminal or the third terminal of the switching unit 100, and the pin 300 is conducted with the first voltage terminal through at least one control switch module to discharge the second electrical signal, including:
when the pin 300 and the first voltage terminal receive the second positive voltage signal, the first terminal and the second terminal of the switching unit 100 are conducted, and the pin 300 is conducted with the first voltage terminal through the first control switch module 210 and the third control switch module 230 to discharge the second positive voltage signal; the second electric signal is a second positive voltage signal; and/or the presence of a gas in the gas,
when the pin 300 and the first voltage terminal receive the second negative voltage signal, the first terminal and the third terminal of the switching unit 100 are conducted, and the pin 300 is conducted with the first voltage terminal through the second control switch module 220 to discharge the second negative voltage signal; the second electrical signal is a second negative pressure signal.
In some embodiments, when the pin 300 and the second voltage terminal both receive the third electrical signal, the first terminal of the switch unit 100 is conducted with the second terminal or the third terminal of the switch unit 100, and the pin 300 is conducted with the second voltage terminal through at least one control switch module to discharge the third electrical signal, including:
when the pin 300 and the second voltage terminal receive the third positive voltage signal, the first terminal and the second terminal of the switch unit 100 are conducted, and the pin 300 is conducted with the second voltage terminal through the first control switch module 210 to discharge the third positive voltage signal; the third electrical signal is a third positive voltage signal; and/or the presence of a gas in the gas,
when the pin 300 and the second voltage terminal receive the third negative voltage signal, the first terminal and the third terminal of the switching unit 100 are conducted, and the pin 300 is conducted with the second voltage terminal through the second control switch module 220 and the third control switch module 230 to discharge the third negative voltage signal; the third electrical signal is a third negative pressure signal.
Alternatively, referring to fig. 1, since CLAMP is a frequency triggered ESD structure, when an EOS event occurs, CLAMP1, CLAMP2, and CLAMP3 do not work and do not damage first diode D1 and second diode D2, and when an ESD event occurs, at least one CLAMP among CLAMP1, CLAMP2, or CLAMP3 works to effectively discharge ESD current due to the excessively fast ESD frequency. Similarly, CLAMP1, CLAMP2, and CLAMP3 in fig. 1 are replaced with GGNMOS1, GGNMOS2, and GGNMOS3 in fig. 4, because GGNMOS is an ESD device triggered by voltage, but the turn-on voltage is generally above 8V, so that the protection effect of EOS can also be achieved. Similarly, referring to fig. 2, SCR1, SCR2 and SCR3 can achieve the same protection effect.
Optionally, as an example, taking the structure of the protection circuit of the chip shown in fig. 1 in the embodiment of the present application as an example, a protection method of the chip in which the protection circuit of the chip has both EOS and ESD protection is described in detail, and the protection method of the chip in the embodiments of the protection circuit of the chip shown in fig. 2 to 4 is the same as the protection method of the chip of the protection circuit of the chip shown in fig. 1 in principle, and is not described again here.
Optionally, referring to fig. 1, the chip protection method includes:
when the EOS positive voltage event occurs, that is, the pin 300 receives the first positive voltage signal EOS1, the first terminal and the second terminal of the switch unit 100 are turned on, the EOS1 reaches the first floating voltage terminal floating vddiobus line from the first diode D1, and then the first control switch module 210 (corresponding to CLAMP 1) performs bleeding.
When the EOS negative voltage event occurs, the pin 300 receives the first negative voltage signal EOS2, the first terminal and the third terminal of the switch unit 100 are turned on, and the EOS2 reaches the floating voltage terminal floating voltage signal on-line from the second diode D2, and then is discharged through the second control switch module 220 (corresponding to CLAMP 2).
When the IO → VDDIO ESD positive voltage event occurs, the pin 300 and the first voltage terminal VDDIOBUS receive the second positive voltage signal ESD1, the first terminal and the second terminal of the switch unit 100 are turned on, the ESD1 current reaches the first control switch module 210 (corresponding to CLAMP 1) from the first diode D1, and then the ESD current is discharged to the first voltage terminal VDDIOBUS through the third control switch module 230 (corresponding to CLAMP 3).
When IO → VDDIO ESD negative event occurs, the pin 300 and the first voltage terminal VDDIOBUS receive the second negative signal ESD2, ESD2 current flows from the first voltage terminal VDDIO BUS through the second control switch module 220 (corresponding to CLAMP 2), flows through the second Floating voltage terminal Floating VSSIO BUS, and is finally discharged through the second diode D2.
When the IO → VSSIO ESD positive voltage event occurs, that is, the pin 300 and the second voltage terminal flowing VSSIO BUS receive the third positive voltage signal ESD3, the first terminal and the second terminal of the switch unit 100 are turned on, the ESD3 current flows through the first Floating voltage terminal flowing VDDIO BUS through the first diode D1, and finally is discharged to the second voltage terminal VSSIO BUS through the first control switch module 210 (corresponding to CLAMP 1).
When the IO → VSSIO ESD negative voltage event occurs, that is, the pin 300 and the second voltage terminal flowing VSSIO BUS receive the third negative voltage signal ESD4, the ESD4 current flows to the first voltage terminal VDDIO BUS through the third control switch module 230 (corresponding to CLAMP 3), then flows to the second Floating voltage terminal flowing VSSIO BUS through the second control switch module 220 (corresponding to CLAMP 2), and finally the ESD current is discharged through the second diode D2.
Those of skill in the art will understand that various operations, methods, steps in the flow, measures, schemes discussed in this application can be alternated, modified, combined, or deleted. Further, other steps, measures, or schemes in various operations, methods, or flows that have been discussed in this application can be alternated, altered, rearranged, broken down, combined, or deleted. Further, steps, measures, schemes in the prior art having various operations, methods, procedures disclosed in the present application may also be alternated, modified, rearranged, decomposed, combined, or deleted.
The terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless otherwise specified.
In the description herein, particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.
It should be understood that, although the steps in the flowcharts of the figures are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and may be performed in other orders unless explicitly stated herein. Moreover, at least a portion of the steps in the flow chart of the figure may include multiple sub-steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of execution is not necessarily sequential, but may be performed alternately or alternately with other steps or at least a portion of the sub-steps or stages of other steps.
The foregoing is only a partial embodiment of the present application, and it should be noted that, for those skilled in the art, several modifications and decorations can be made without departing from the principle of the present application, and these modifications and decorations should also be regarded as the protection scope of the present application.
Claims (11)
1. A protection circuit for a chip, comprising: a switch unit and a control switch unit;
the first end of the switch unit is electrically connected with a pin of the chip; the second end and the third end of the switch unit are respectively and electrically connected with the first floating voltage end and the second floating voltage end;
the control switch unit comprises at least three control switch modules, at least one control switch module is electrically connected with the first floating voltage end, and at least one control switch module is electrically connected with the second floating end;
the control switch unit is used for conducting a first end of the switch unit with a second end or a third end of the switch unit when the pin receives an electric signal, and the pin is conducted with a first voltage end and/or a second voltage end through at least one control switch module so as to discharge the electric signal; the electrical signal comprises at least one of: a first electrical signal, a second electrical signal, a third electrical signal; the first electrical signal is received by the pin, the second electrical signal is received by both the pin and the first voltage terminal, and the third electrical signal is received by both the pin and the second voltage terminal;
in the at least three control switch modules, a first end and a second end of at least one control switch module are respectively and electrically connected with a first floating voltage end and a second voltage end; the first end and the second end of at least one control switch module are respectively and electrically connected with the first voltage end and the second floating voltage end; and the first end and the second end of at least one control switch module are respectively and electrically connected with the first voltage end and the second voltage end.
2. The protection circuit of chip of claim 1, wherein the control switch unit comprises a first control switch module, a second control switch module, and a third control switch module;
the first end and the second end of the first control switch module are respectively and electrically connected with the first floating voltage end and the second voltage end;
the first end and the second end of the second control switch module are respectively and electrically connected with the first voltage end and the second floating voltage end;
and the first end and the second end of the third control switch module are respectively and electrically connected with the first voltage end and the second voltage end.
3. The protection circuit of chip according to claim 1, wherein the switch unit comprises a first switch module and a second switch module;
the first end of the first switch module and the first end of the second switch module are used as the first end of the switch unit together;
a second terminal of the first switch module as a second terminal of the switch unit;
and the second end of the second switch module is used as the third end of the switch unit.
4. The chip protection circuit according to claim 1, wherein the control switch module comprises a thyristor module, and a first end and a second end of the thyristor module are respectively used as a first end and a second end of the control switch module; or the like, or, alternatively,
the control switch module comprises a first parasitic switch device; a first end of the first parasitic switching device is used as a first end of the control switching module; and the second end and the control end of the first parasitic switch device are jointly used as the second end of the control switch module.
5. The protection circuit of chip of claim 1, wherein the control switch module comprises a first switch device, an inverting module and a second parasitic switch device;
the control end of the first switch device, the second end of the inversion module and the first end of the second parasitic switch device are jointly used as the first end of the control switch module;
the first end and the second end of the first switch device, the third end of the inversion module and the second end of the second parasitic switch device are used as the second end of the control switch module together;
and the first end and the fourth end of the reverse module are respectively and electrically connected with the control end of the first switching device and the control end of the second parasitic switching device.
6. A system for protecting a chip, comprising: a chip and a protection circuit of the chip of any one of claims 1-5;
the chip comprises a plurality of pins;
each pin is electrically connected with the first end of the switch unit of the protection circuit of one chip.
7. A method for protecting a chip, applied to a protection circuit of the chip according to any one of claims 1 to 5, comprising:
when a pin of the chip receives an electric signal, a first end of the switch unit is conducted with a second end or a third end of the switch unit, and the pin is conducted with a first voltage end and/or a second voltage end through at least one control switch module so as to discharge the electric signal; the electrical signal comprises at least one of: a first electrical signal, a second electrical signal, a third electrical signal; the first electrical signal is received by the pin, the second electrical signal is received by both the pin and the first voltage terminal, and the third electrical signal is received by both the pin and the second voltage terminal.
8. The method for protecting the chip according to claim 7, wherein when a pin of the chip receives an electrical signal, the first terminal of the switch unit is conducted with the second terminal or the third terminal of the switch unit, and the pin is conducted with the first voltage terminal and/or the second voltage terminal through at least one control switch module to drain the electrical signal, the method comprising at least one of:
when the pin receives a first electric signal, the first end of the switch unit is conducted with the second end or the third end of the switch unit, and the pin is conducted with the first voltage end or the second voltage end through at least one control switch module so as to discharge the first electric signal;
when the pin and the first voltage end both receive a second electric signal, the first end of the switch unit is conducted with the second end or the third end of the switch unit, and the pin is conducted with the first voltage end through at least one control switch module so as to discharge the second electric signal;
when the pin and the second voltage end both receive a third electric signal, the first end of the switch unit is conducted with the second end or the third end of the switch unit, and the pin is conducted with the second voltage end through at least one control switch module so as to discharge the third electric signal.
9. The method for protecting a chip according to claim 8, wherein when a pin of the chip receives a first electrical signal, the first terminal of the switching unit is conducted with the second terminal or the third terminal of the switching unit, and the pin is conducted with the first voltage terminal or the second voltage terminal through at least one control switch module to bleed off the first electrical signal, the method comprising:
when the pin receives a first positive voltage signal, the first end and the second end of the switch unit are conducted, and the pin is conducted with the second voltage end through the first control switch module so as to discharge the first positive voltage signal; the first electric signal is a first positive voltage signal; and/or the presence of a gas in the gas,
when the pin receives a first negative voltage signal, the first end and the third end of the switch unit are conducted, and the pin is conducted with the first voltage end through the second control switch module so as to discharge the first negative voltage signal; the first electrical signal is a first negative voltage signal.
10. The method for protecting the chip according to claim 8, wherein when the pin and the first voltage terminal both receive the second electrical signal, the first terminal of the switch unit is conducted with the second terminal or the third terminal of the switch unit, and the pin is conducted with the first voltage terminal through at least one control switch module to discharge the second electrical signal, comprising:
when the pin and the first voltage end receive a second positive voltage signal, the first end and the second end of the switch unit are conducted, and the pin is conducted with the first voltage end through the first control switch module and the third control switch module so as to discharge the second positive voltage signal; the second electric signal is a second positive voltage signal; and/or the presence of a gas in the gas,
when the pin and the first voltage end receive a second negative voltage signal, the first end and the third end of the switch unit are conducted, and the pin is conducted with the first voltage end through a second control switch module so as to discharge the second negative voltage signal; the second electrical signal is a second negative pressure signal.
11. The method for protecting the chip according to claim 8, wherein when the pin and the second voltage terminal both receive a third electrical signal, the first terminal of the switching unit is conducted with the second terminal or the third terminal of the switching unit, and the pin is conducted with the second voltage terminal through at least one control switch module to discharge the third electrical signal, comprising:
when the pin and the second voltage end receive a third positive voltage signal, the first end and the second end of the switch unit are conducted, and the pin is conducted with the second voltage end through the first control switch module so as to discharge the third positive voltage signal; the third electrical signal is a third positive voltage signal; and/or the presence of a gas in the gas,
when the pin and the second voltage end receive a third negative voltage signal, the first end and the third end of the switch unit are conducted, and the pin is conducted with the second voltage end through a second control switch module and a third control switch module so as to discharge the third negative voltage signal; the third electrical signal is a third negative pressure signal.
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| CN107204611A (en) * | 2016-03-16 | 2017-09-26 | 帝奥微电子有限公司 | Overvoltage protection structure |
| US10903646B2 (en) * | 2016-07-26 | 2021-01-26 | Huawei Technologies Co., Ltd. | Electrostatic protection circuit |
| CN211981493U (en) * | 2020-05-15 | 2020-11-20 | 苏州浪潮智能科技有限公司 | Device for preventing external interconnection interface power supply from damaging protective device |
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