CN114203704A - Memory cell structure of static random access memory and memory - Google Patents

Abstract

The invention provides a storage unit structure of a static random access memory, which comprises a transistor unit, wherein the transistor unit comprises a first common-gate complementary field effect transistor, a transmission unit and a second common-gate complementary field effect transistor which are sequentially arranged along a first direction, the transmission unit comprises a first transmission pipe and a second transmission pipe which are arranged in a stacking manner, the channel direction of the first common-gate complementary field effect transistor, the channel direction of the transmission pipe unit and the channel direction of the second common-gate complementary field effect transistor are all parallel to the first direction, and the first transmission pipe and the second transmission pipe which are arranged in the stacking manner can greatly reduce the occupied area of a single first transmission pipe and a single second transmission pipe, greatly reduce the occupied area, improve the circuit integration level and further reduce the cost. The invention also provides a memory.

Description

Memory cell structure of static random access memory and memory

Technical Field

The present invention relates to the field of semiconductor technologies, and in particular, to a memory cell structure of a static random access memory and a memory.

Background

Static Random-Access Memory (SRAM) is one type of Random Access Memory. A memory cell of a static random access memory generally includes a pull-up transistor (PU), a pull-down transistor (PD), and a pass-gate transistor (PG). In practical applications, the circuit area occupied by the SRAM is large, and the low integration level significantly increases the chip cost.

Therefore, there is a need to provide a new sram cell structure and memory to solve the above-mentioned problems in the prior art.

Disclosure of Invention

The invention aims to provide a memory cell structure of a static random access memory and the memory, which can improve the integration level of a circuit and reduce the manufacturing cost.

In order to achieve the above object, the memory cell structure of the sram according to the present invention includes a transistor unit, where the transistor unit includes a first common-gate complementary field effect transistor, a transmission unit, and a second common-gate complementary field effect transistor sequentially arranged along a first direction, the transmission unit includes a first transmission tube and a second transmission tube arranged in a stacked manner, and a channel direction of the first common-gate complementary field effect transistor, a channel direction of the transmission tube unit, and a channel direction of the second common-gate complementary field effect transistor are all parallel to the first direction.

The memory cell structure of the static random access memory has the advantages that: the first transmission pipe and the second transmission pipe which are arranged in a stacked mode can greatly reduce the occupied area of the single first transmission pipe and the single second transmission pipe, greatly reduce the occupied area, improve the circuit integration level and further reduce the cost.

Optionally, the first common-gate complementary field effect transistor includes a first N-type field effect transistor and a first P-type field effect transistor which are stacked, and the second common-gate complementary field effect transistor includes a second N-type field effect transistor and a second P-type field effect transistor which are stacked. The beneficial effects are that: and the shared grid electrode reduces the process difficulty and the occupied area, and greatly improves the integration level.

Optionally, the drain of the first N-type field effect transistor and the drain of the first P-type field effect transistor are both disposed on one side of the gate of the first common-gate complementary field effect transistor, and the source of the first N-type field effect transistor and the source of the first P-type field effect transistor are both disposed on the other side of the gate of the first common-gate complementary field effect transistor.

Optionally, the drain of the first N-type field effect transistor and the drain of the first P-type field effect transistor are both disposed on a side of the gate of the first common-gate complementary field effect transistor facing the transmission unit. The beneficial effects are that: the drain electrode of the first N-type field effect transistor and the drain electrode of the first P-type field effect transistor are connected with the transmission unit, so that the circuit integration level is greatly improved, and the process difficulty is reduced.

Optionally, the drain of the second N-type field effect transistor and the drain of the second P-type field effect transistor are both disposed on one side of the gate of the second common-gate complementary field effect transistor, and the source of the second N-type field effect transistor and the source of the second P-type field effect transistor are both disposed on the other side of the gate of the second common-gate complementary field effect transistor.

Optionally, the drain of the second N-type field effect transistor and the drain of the second P-type field effect transistor are both disposed on a side of the gate of the second common-gate complementary field effect transistor facing the transmission unit. The beneficial effects are that: the drain electrode of the second N-type field effect transistor and the drain electrode of the second P-type field effect transistor are connected with the transmission unit, so that the circuit integration level is greatly improved, and the process difficulty is reduced.

Optionally, the number of channels of the first transmission tube, the second transmission tube, the first N-type field effect transistor, the second N-type field effect transistor, the first P-type field effect transistor, and the second P-type field effect transistor is greater than or equal to 1. The beneficial effects are that: facilitating low power consumption or high speed. .

Optionally, the first transmission tube and the second transmission tube are both field effect transistors.

Optionally, the first transmission tube and the second transmission tube are both N-type field effect transistors or P-type field effect transistors.

Optionally, the memory cell structure of the sram further includes a connection unit, where the connection unit is configured to implement internal connection and external connection of the transistor unit.

Optionally, the connection unit includes a word line, a first bit line, a second bit line, a first interconnection line, a second interconnection line, a first power line, and a second power line, the word line is used to control the first pass transistor and the second pass transistor, the first bit line and the second bit line are used to implement signal transmission of the transistor unit, the first interconnection line and the second interconnection line are used to implement internal connection of the transistor unit, the first power line and the second power line are used to supply power or ground to the transistor unit, the first bit line and the second bit line are perpendicular to the first direction, and the word line, the first interconnection line, the second interconnection line, the first power line, and the second power line are parallel to the first direction.

Optionally, the word lines, the first interconnect lines and the second interconnect lines are device top metal interconnect lines.

Optionally, the word lines, the first interconnect lines and the second interconnect lines are located on the same or different metal interconnect layers on top of the device.

Optionally, the first power line and the second power line are device top metal interconnection lines or metal buried lines in a substrate.

The invention also provides a memory which comprises at least one memory cell structure of the static random access memory.

The storage unit has the advantages that: the memory cell structure of the static random access memory is applied, so that the integration level of a circuit is improved, and the cost is reduced.

Drawings

FIG. 1 is a cross-sectional view of a memory cell structure of an SRAM in accordance with some embodiments of the present invention;

FIG. 2 is a top view of the SRAM cell structure shown in FIG. 1;

FIG. 3 is a top view of a memory in some embodiments of the invention;

FIG. 4 is a schematic circuit diagram of a SRAM cell structure in accordance with some embodiments of the present invention;

fig. 5 is a schematic diagram of a two channel field effect transistor in some embodiments of the invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. As used herein, the word "comprising" and similar words are intended to mean that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items.

In view of the problems in the prior art, embodiments of the present invention provide a memory including at least one sram cell structure.

In some embodiments, the memory cell structure of the SRAM includes a transistor cell and a connection cell.

FIG. 1 is a cross-sectional view of a memory cell structure of an SRAM in some embodiments of the present invention. Referring to fig. 1, the memory cell structure of the sram includes a transistor unit, where the transistor unit includes a first common-gate complementary field effect transistor 101, a transmission unit 102, and a second common-gate complementary field effect transistor 103 sequentially arranged along a first direction, the transmission unit 102 includes a first transmission transistor 1021 and a second transmission transistor 1022 arranged in a stacked manner, and a channel direction of the first common-gate complementary field effect transistor 101, a channel direction of the transmission transistor unit 102, and a channel direction of the second common-gate complementary field effect transistor 103 are all parallel to the first direction.

In some embodiments, the first and second pass transistors are field effect transistors. In still other embodiments, the first and second transmission transistors are both N-type field effect transistors or P-type field effect transistors.

In some embodiments, the memory cell structure of the sram further includes a connection unit, and the connection unit is configured to implement internal connection and external connection of the transistor unit.

Referring to fig. 1, the connection unit includes a word line 201, a first bit line 202, a second bit line 203, a first interconnection line 204, a second interconnection line (not shown), a first power supply line (not shown), and a second power supply line 205, the word line 201 is used to control the first pass transistor 1021 and the second pass transistor 1022, the first bit line 202 and the second bit line 203 are used for signal transmission, the first interconnection line 204 and the second interconnection line are used for internal connection of the transistor unit, the first power line and the second power line 205 are used to supply power or ground to the transistor unit, the first bit line 202 and the second bit line 203 are perpendicular to the first direction, and the word line 201, the first interconnection line 204, the second interconnection line, the first power supply line, and the second power supply line 205 are parallel to the first direction. The first power line is grounded, and the second power line 205 is connected to a working voltage.

Referring to fig. 1, the first bit line 202 is connected to a first end of the first pass transistor 1021, the second bit line 203 is connected to a first end of the second pass transistor 1022, the word line 201 is connected to a gate of the first pass transistor 1021 and a gate of the second pass transistor 1022 through metal vias, the first interconnection line 204 is connected to a second end of the first pass transistor 1021, two drains of the first common gate complementary field effect transistor 101, and a gate of the second common gate complementary field effect transistor 103 through metal vias, the second interconnection line is connected to a second end of the second pass transistor 1022, two drains of the second common gate complementary field effect transistor 103, and a gate of the first common gate complementary field effect transistor 101 through metal vias, and the second power line 205 is connected to a source of the P-type field effect transistor of the first common gate complementary field effect transistor 101 and a source of the P-type field effect transistor of the second common gate complementary field effect transistor 103 through metal vias The source of the transistor is connected, and the first power line is connected with the source of the N-type field effect transistor of the first common-gate complementary field effect transistor 101 and the source of the N-type transistor of the second common-gate complementary field effect transistor 103 through metal through holes.

In some embodiments, the first transmission tube and the second transmission tube are both N-type field effect transistors. In still other embodiments, the first and second pass transistors are both P-type field effect transistors.

In some embodiments, the first end of the first transmission tube is a drain, and the second end of the first transmission tube is a source.

In some embodiments, the first end of the first transmission tube is a source electrode, and the second end of the first transmission tube is a drain electrode.

In some embodiments, the first end of the second pass transistor is a drain and the second end of the second pass transistor is a source.

In some embodiments, the first end of the second pass transistor is a source and the second end of the second pass transistor is a drain.

In some embodiments, the word lines, the first interconnect lines, and the second interconnect lines are device top metal interconnect lines.

In some embodiments, the word lines, the first interconnect lines and the second interconnect lines are located in the same or different metal interconnect layers on top of the device.

In some embodiments, the first power line and the second power line are device top metal interconnect lines or metal buried lines in a substrate. When the first power line and the second power line are metal interconnection lines on the top of the device, the first power line and the word line, the first interconnection line and the second interconnection line are located on the same or different metal interconnection layers on the top of the device, and the second power line and the word line, the first interconnection line and the second interconnection line are located on the same or different metal interconnection layers on the top of the device. Optionally, when the first power line and the second power line are metal interconnection lines on the top of the device, the first power line, the second power line, the word line, the first interconnection line and the second interconnection line are located on the same metal interconnection layer on the top of the device.

Referring to fig. 1, the word lines 201, the first interconnect lines 204, and the second interconnect lines (not shown) are located in the same metal interconnect layer on the top of the device, for example, the first metal interconnect layer on the top of the device, and the first power lines and the second power lines 205 are all buried metal lines in the substrate.

In some embodiments, the first common-gate complementary field effect transistor comprises a first N-type field effect transistor and a first P-type field effect transistor arranged in a stack, and the second common-gate complementary field effect transistor comprises a second N-type field effect transistor and a second P-type field effect transistor arranged in a stack.

In some embodiments, the first N-type field effect transistor of the first common gate complementary field effect transistor is stacked above the first P-type field effect transistor. In still other embodiments, a first P-type field effect transistor of the first common-gate complementary field effect transistor is stacked over a first N-type field effect transistor.

In some embodiments, a second N-type field effect transistor of the second common gate complementary field effect transistor is stacked over a second P-type field effect transistor. In still other embodiments, a second P-type field effect transistor of the second common-gate complementary field effect transistor is stacked over a second N-type field effect transistor.

Referring to fig. 1, the first P-type field effect transistor 1012 is stacked over the first N-type field effect transistor 1011, the second P-type field effect transistor 1032 is stacked over the second N-type field effect transistor 1031, and the second pass transistor 1022 is stacked on the upper side of the first pass transistor 1021.

Referring to fig. 1, channels of all transistors are formed by the same fin structure.

In some embodiments, the drain of the first N-type field effect transistor and the drain of the first P-type field effect transistor are both disposed on one side of the gate of the first common-gate complementary field effect transistor, and the source of the first N-type field effect transistor and the source of the first P-type field effect transistor are both disposed on the other side of the gate of the first common-gate complementary field effect transistor.

In some embodiments, the drain of the first N-type field effect transistor and the drain of the first P-type field effect transistor are both disposed on a side of the gate of the first common-gate complementary field effect transistor facing the transmission unit.

In some embodiments, the drain of the second N-type field effect transistor and the drain of the second P-type field effect transistor are both disposed on one side of the gate of the second common-gate complementary field effect transistor, and the source of the second N-type field effect transistor and the source of the second P-type field effect transistor are both disposed on the other side of the gate of the second common-gate complementary field effect transistor.

In some embodiments, the drain of the second N-type field effect transistor and the drain of the second P-type field effect transistor are both disposed on a side of the gate of the second common-gate complementary field effect transistor facing the transmission unit.

Referring to fig. 1, a gate dielectric layer 105 is disposed between channels and gates of the first pass transistor, the second pass transistor, the first N-type field effect transistor, the first P-type field effect transistor, the second N-type field effect transistor 1031, and the second P-type field effect transistor 1032.

FIG. 2 is a top view of the SRAM cell structure shown in FIG. 1. Referring to fig. 2, the word lines are located between the first interconnection lines 204 and the second interconnection lines 206, and the first bit lines 202 and the second bit lines 203 are perpendicular to the word lines 201.

FIG. 3 is a top view of a memory in some embodiments of the invention. Referring to fig. 2 and 3, a word line 201 is common to the memory cell structures of one row of the sram, and a first bit line 202 and a second bit line 203 are common to the memory cell structures of one column of the sram.

FIG. 4 is a schematic circuit diagram of a SRAM cell structure in some embodiments of the present invention. Referring to fig. 4, the fet PD1 corresponds to the first nfet, the fet PD2 corresponds to the second nfet, the fet PG1 corresponds to the first pass transistor, the fet PG2 corresponds to the second pass transistor, the fet PU1 corresponds to the first pfet, the pfet PU2 corresponds to the second pfet, the bit line BL corresponds to the first bit line, and the bit line BLB corresponds to the second bit line.

In some embodiments, the number of channels of the first pass transistor, the second pass transistor, the first N-type field effect transistor, the second N-type field effect transistor, the first P-type field effect transistor, and the second P-type field effect transistor is greater than or equal to 1.

In some embodiments, the first pass transistor, the second pass transistor, the first N-type field effect transistor, the second N-type field effect transistor, the first P-type field effect transistor, and the second P-type field effect transistor may all be referred to as field effect transistors, and when the number of channels of one field effect transistor is greater than or equal to 2, the sources of all channels are epitaxially grown together to form the source of the transistor, and the drains of all channels are epitaxially grown together to form the drain of the field effect transistor.

In still other embodiments, when the number of channels of a field effect transistor is greater than or equal to 2, the sub-sources of all the channels are interconnected through metal to form the source of the transistor, and the sub-drains of all the channels are interconnected through metal to form the drain of the field effect transistor.

Fig. 5 is a schematic diagram of a two channel field effect transistor in some embodiments of the invention. Referring to fig. 5, the field effect transistor includes two channels 301, a gate 302, a source 303, a drain 304, a gate dielectric layer 105 and a substrate (not shown in the figure), a sub-source 3031 of the two channels is interconnected by a first metal 3032 to form the source 303 of the field effect transistor, a sub-drain 3041 of the two channels is interconnected by a second metal 3042 to form the drain 304 of the field effect transistor, and the gate dielectric layer 105 is disposed between the channel 301 and the gate.

In some embodiments, the shape of the metal via is not limited at all, and the source, the drain, the gate, the word line, the first bit line, the second bit line, the first interconnection line, the second interconnection line, and the connection between the first power line and the second power line may be implemented.

Although the embodiments of the present invention have been described in detail hereinabove, it is apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it is to be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the following claims. Moreover, the invention as described herein is capable of other embodiments and of being practiced or of being carried out in various ways.

Claims (15)

1. The memory cell structure of the static random access memory is characterized by comprising a transistor unit, wherein the transistor unit comprises a first common-gate complementary field effect transistor, a transmission unit and a second common-gate complementary field effect transistor which are sequentially arranged along a first direction, the transmission unit comprises a first transmission tube and a second transmission tube which are arranged in a stacked mode, and the channel direction of the first common-gate complementary field effect transistor, the channel direction of the transmission tube unit and the channel direction of the second common-gate complementary field effect transistor are all parallel to the first direction.

2. The memory cell structure of claim 1, wherein the first common-gate complementary field effect transistor comprises a first N-type field effect transistor and a first P-type field effect transistor in a stacked arrangement, and the second common-gate complementary field effect transistor comprises a second N-type field effect transistor and a second P-type field effect transistor in a stacked arrangement.

3. The SRAM cell structure of claim 2, wherein the drain of the first NFET and the drain of the first PFET are both disposed on one side of the gate of the first common gate complementary FET, and the source of the first NFET and the source of the first PFET are both disposed on the other side of the gate of the first common gate complementary FET.

4. The SRAM cell structure of claim 3, wherein the drain of the first NFET and the drain of the first PFET are both disposed on a side of the gate of the first common-gate complementary FET facing the transmission unit.

5. The SRAM cell structure as claimed in claim 2, wherein the drain of the second NFET and the drain of the second PFET are both disposed on one side of the gate of the second common gate complementary FET, and the source of the second NFET and the source of the second PFET are both disposed on the other side of the gate of the second common gate complementary FET.

6. The SRAM cell structure of claim 5, wherein the drain of the second NFET and the drain of the second PFET are both disposed on a side of the gate of the second common-gate complementary FET facing the transmission unit.

7. The SRAM cell structure of claim 2, wherein the number of channels of the first pass transistor, the second pass transistor, the first NFET, the second NFET, the first PFET, and the second PFET is greater than or equal to 1.

8. The SRAM cell structure of claim 1, wherein the first pass transistor and the second pass transistor are both field effect transistors.

9. The SRAM cell structure of claim 8, wherein the first pass transistor and the second pass transistor are both NFETs or PFETs.

10. The SRAM cell structure of claim 1, further comprising a connection unit for enabling internal and external connections of the transistor cells.

11. The memory cell structure of static random access memory according to claim 10, wherein the connection unit includes a word line, a first bit line, a second bit line, a first interconnection line, a second interconnection line, a first power supply line, and a second power supply line, the word line is used for controlling the first transmission tube and the second transmission tube, the first bit line and the second bit line are used for realizing signal transmission of the transistor unit, the first interconnect lines and the second interconnect lines are for enabling internal connection of the transistor cells, the first power line and the second power line are used for supplying power or grounding to the transistor unit, the first bit line and the second bit line are perpendicular to the first direction, and the word line, the first interconnection line, the second interconnection line, the first power line and the second power line are parallel to the first direction.

12. The memory cell structure of the static random access memory according to claim 11, wherein the word lines, the first interconnect lines and the second interconnect lines are device top metal interconnect lines.

13. The memory cell structure of the SRAM of claim 12, wherein the word line, the first interconnect line and the second interconnect line are located at the same or different metal interconnect layers on top of a device.

14. The memory cell structure of claim 11, wherein the first power line and the second power line are a device top metal interconnect line or a metal buried line in a substrate.

15. A memory comprising at least one sram cell structure according to any one of claims 1 to 14.

Images