CN114203691A - Multi-chip high-density interconnection packaging structure and manufacturing method thereof - Google Patents

Multi-chip high-density interconnection packaging structure and manufacturing method thereof Download PDF

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Publication number
CN114203691A
CN114203691A CN202111525572.8A CN202111525572A CN114203691A CN 114203691 A CN114203691 A CN 114203691A CN 202111525572 A CN202111525572 A CN 202111525572A CN 114203691 A CN114203691 A CN 114203691A
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substrate
layer
chip
electrically connected
manufacturing
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CN202111525572.8A
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Chinese (zh)
Inventor
侯峰泽
尤祥安
李君�
王启东
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National Center for Advanced Packaging Co Ltd
Shanghai Xianfang Semiconductor Co Ltd
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National Center for Advanced Packaging Co Ltd
Shanghai Xianfang Semiconductor Co Ltd
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Priority to CN202111525572.8A priority Critical patent/CN114203691A/en
Publication of CN114203691A publication Critical patent/CN114203691A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

The invention relates to a multi-chip high-density interconnection packaging structure, comprising: a first package comprising: a first chip; a chip pad on a front side of the first chip; an insulating layer covering the first chip; a first rewiring layer located in the insulating layer and electrically connected to the chip pad; a substrate dielectric layer disposed around the first package body; a substrate through hole penetrating through the substrate dielectric layer; the second rewiring layers are arranged on the front surface and the back surface of the substrate dielectric layer and the back surface of the first packaging body; the substrate accumulation layer wraps the first packaging body and the substrate dielectric layer and comprises an upper substrate accumulation layer and a lower substrate accumulation layer; blind holes in the upper and lower substrate buildup layers; a substrate pad; salient points; and one or more functional chips. The invention also relates to a manufacturing method of the multi-chip high-density interconnection packaging structure.

Description

Multi-chip high-density interconnection packaging structure and manufacturing method thereof
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a multi-chip high-density interconnection packaging structure and a manufacturing method thereof.
Background
Driven by the small, light and thin electronic products, the market has higher and higher requirements on the functions of a single chip, and high-performance chips are developed to a higher I/O number, and have ultra-fine I/O port sizes and intervals. When the functionality of a single chip is not sufficient, multiple chip interconnects are required. At present, for the multi-chip interconnection package of the ultra-high density chip, because the process precision of the package substrate is low, the extraction and interconnection between I/O ports with the distance of only a few microns cannot be realized, or the defect of long interconnection path exists. How to integrate and encapsulate a plurality of different kinds of high-density chips together, realize a plurality of high-density chips interconnect, constitute a powerful and volume consumption is than little module again, is a difficult problem in the advanced encapsulation field of chip.
Disclosure of Invention
Starting from the prior art, the task of the invention is to provide a multi-chip high-density interconnection packaging structure and a manufacturing method thereof, wherein a wafer-level rewiring layer process is adopted to expand fine-pitch and micro-size bonding pads of a high-density I/O chip into wide-pitch and large-size bonding pads, the high-density I/O chip is packaged at one time and then embedded into a substrate to serve as a local high-density interconnection structure in the substrate, and multiple chips on the substrate are bridged to realize multi-chip interconnection.
In a first aspect of the present invention, which is directed to the problems in the prior art, the present invention provides a multi-chip high-density interconnect package structure, comprising:
a first package comprising:
a first chip;
a chip pad on a front side of the first chip;
an insulating layer covering the first chip;
a first rewiring layer located in the insulating layer and electrically connected to the chip pad;
a substrate dielectric layer disposed around the first package body;
a substrate through hole penetrating through the substrate dielectric layer;
the second rewiring layers are arranged on the front surface and the back surface of the substrate dielectric layer and the back surface of the first packaging body;
the substrate accumulation layer wraps the first packaging body and the substrate dielectric layer and comprises an upper substrate accumulation layer and a lower substrate accumulation layer;
blind holes in the upper and lower substrate buildup layers;
a substrate pad positioned on an upper surface of the upper substrate buildup layer and a lower surface of the lower substrate buildup layer;
the salient point is electrically connected with the blind hole in the upper substrate accumulation layer and the pad on the upper surface of the upper substrate accumulation layer; and
one or more functional chips electrically connected with the bumps.
In a preferred embodiment of the present invention, it is provided that the first package further includes a molding layer disposed around the first chip.
In a further preferred embodiment of the present invention, it is provided that the second redistribution layers arranged on the front and back sides of the substrate dielectric layer are electrically connected to the substrate via.
In still another preferred embodiment of the present invention, it is provided that the blind via in the upper substrate buildup layer is electrically connected to the first rewiring layer, and the blind via in the lower substrate buildup layer is electrically connected to the second rewiring layer.
In another preferred embodiment of the present invention, a portion of the substrate pad located on the lower surface of the lower substrate buildup layer is electrically connected to the blind via.
In still another preferred embodiment of the present invention, the semiconductor device further includes BGA solder balls electrically connected to the pads on the lower surface of the lower substrate stack layer.
In another preferred embodiment of the present invention, the bump is made of a tin-silver-copper alloy, a tin-silver alloy, or a copper pillar + tin-silver alloy.
In a second aspect of the present invention, in order to solve the problems in the prior art, the present invention provides a method for manufacturing a multi-chip high-density interconnect package structure, including:
forming a plastic packaging layer on the periphery of the chip to form a reconstructed wafer;
manufacturing an insulating layer on the front surface of the wafer, and then removing the insulating layer at a position corresponding to the chip bonding pad through photoetching to form a through hole and photoetching to form a first circuit pattern;
manufacturing a first rewiring layer which is positioned in the insulating layer and penetrates through the through hole to be electrically connected with the chip bonding pad;
cutting the wafer into single chips to form a first packaging body;
forming a substrate dielectric layer around the first packaging body;
manufacturing a substrate through hole penetrating through a substrate medium;
manufacturing a second rewiring layer electrically connected to the through hole of the substrate;
forming substrate accumulation layers on the front and back surfaces of the first packaging body and the substrate dielectric layer through a vacuum lamination process;
manufacturing blind holes in the substrate accumulation layer;
manufacturing welding pads on the upper surface and the lower surface of the substrate accumulation layer;
forming salient points on the bonding pads and the blind holes on the upper surface of the substrate accumulation layer;
welding the chip and the bump; and
and implanting BGA solder balls on the bonding pads on the lower surface of the substrate accumulation layer.
In a preferred embodiment of the invention, it is provided that the substrate through-holes and blind-holes are produced by laser drilling and then by chemical or galvanic metal plating in the holes.
The invention has at least the following beneficial effects: the invention provides a multi-chip high-density interconnection packaging structure and a manufacturing method thereof.
Drawings
Fig. 1 illustrates a cross-sectional schematic view of a multi-chip high density interconnect package structure 100, in accordance with one embodiment of the present invention.
Fig. 2A to 2I are schematic cross-sectional views illustrating a process of fabricating a multi-chip high-density interconnect package structure according to an embodiment of the invention.
Detailed Description
It should be noted that the components in the figures may be exaggerated and not necessarily to scale for illustrative purposes. In the figures, identical or functionally identical components are provided with the same reference symbols.
In the present invention, the embodiments are only intended to illustrate the aspects of the present invention, and should not be construed as limiting.
In the present invention, the terms "a" and "an" do not exclude the presence of a plurality of elements, unless otherwise specified.
It is further noted herein that in embodiments of the present invention, only a portion of the components or assemblies may be shown for clarity and simplicity, but those of ordinary skill in the art will appreciate that, given the teachings of the present invention, required components or assemblies may be added as needed in a particular scenario.
It is also noted herein that, within the scope of the present invention, the terms "same", "equal", and the like do not mean that the two values are absolutely equal, but allow some reasonable error, that is, the terms also encompass "substantially the same", "substantially equal".
It should also be noted herein that in the description of the present invention, the terms "central", "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In addition, the embodiments of the present invention describe the process steps in a specific order, however, this is only for convenience of distinguishing the steps, and does not limit the order of the steps.
In the embodiment of the invention, the primary high-density package formed by the wafer-level rewiring packaging process is embedded in the organic substrate and serves as a bridge with the electrical and heat dissipation interconnection functions, and two or more chips on the substrate are connected through the blind holes, the (micro) bumps, the rewiring layer and the like, so that the multi-chip interconnection on the substrate is realized, and the problem that the chips are damaged by laser drilling in the chip embedding technology is solved.
Fig. 1 illustrates a cross-sectional schematic view of a multi-chip high density interconnect package structure 100, in accordance with one embodiment of the present invention.
As shown in fig. 1, the multi-chip high-density interconnection package structure includes a first package body, a substrate dielectric layer 106, a substrate via 107, a second re-wiring layer 108, a substrate stacking layer 109, a blind via 110, a substrate pad 111, a bump 112, a functional chip 113a, a functional chip 113b, and a BGA ball 114. The first package includes a first chip 101, a chip pad 102, a molding layer 103, an insulating layer 104, and a first redistribution layer 105.
The material of the chip 101 includes silicon, silicon carbide, gallium nitride, and the like. The chip 101 serves to bridge a plurality of functional chips, and also can supply power to the plurality of functional chips, and can be used for heat dissipation.
Chip pad 102 is on the front side of chip 101.
The molding layer 103 is disposed around the chip 101. The material of the molding layer 103 may be a conventional molding material such as resin, or a molding material that has been specially modified so as to have a specific stress with respect to the chip 101.
The insulating layer 104 covers the chip 101 and the molding layer 103.
The first rewiring layer 105 is located in the insulating layer 104, and an upper surface of the first rewiring layer 105 is not covered with the insulating layer 104. The first redistribution layer 105 is electrically connected to the chip pad 102.
A substrate dielectric layer 106 is disposed around the first package.
The substrate via 107 penetrates the substrate dielectric layer 106.
A second re-routing layer 108 is disposed on the front and back sides of the substrate dielectric layer 106 and the back side of the first package. The second re-wiring layers 108 disposed on the front and back surfaces of the substrate dielectric layer 106 are electrically connected to the substrate via 107.
A substrate stack layer 109 encapsulates the first encapsulant and the substrate dielectric layer 106. Wherein the substrate stack layer 109 includes an upper substrate stack layer and a lower substrate stack layer.
The blind vias 110 are located in the substrate stack layer 109, wherein the blind vias 110 in the upper substrate stack layer are electrically connected to the first redistribution layer 105, and the blind vias 110 in the lower substrate stack layer are electrically connected to the second redistribution layer 108.
The substrate pads 111 are located on the upper surface of the upper substrate stack layer and the lower surface of the lower substrate stack layer. Wherein a portion of the substrate pad located on the lower surface of the lower substrate buildup layer is electrically connected to the blind via 110.
Bumps 112 are arranged on the blind vias 110 in the upper substrate buildup layer and on the pads 111 on the upper surface of the upper substrate buildup layer, and are electrically connected to the blind vias 110 and the pads 111. The bump 112 is made of tin-silver-copper alloy, tin-silver alloy, or copper pillar + tin-silver alloy.
The functional chips 113a and 113b are electrically connected to the bumps 112. The functional chips 113a and 113b may be the same chip or different chips. The material of the functional chips 113a and 113b includes silicon, silicon carbide, gallium nitride, and the like. In other embodiments of the invention, a greater or lesser number of chips may be disposed over bumps 112.
The BGA balls 114 are electrically connected to the pads 111 on the lower surface of the substrate stack layer 109, and serve to electrically connect the package structure to an external system.
Fig. 2A to 2I are schematic cross-sectional views illustrating a process of fabricating a multi-chip high-density interconnect package structure according to an embodiment of the invention.
In step 1, as shown in fig. 2A, a molding layer 203 is formed around the chip, thereby forming a reconstituted wafer. The material of the plastic sealing layer is usually thermosetting or thermoplastic resin material, and the variety of polymer materials which can be used includes: polyimide PI, bis-benzocyclobutene resin BCB or phenyl benzobisoxazole resin PBO, epoxy resin, organic silicon, acrylic acid derivative and the like.
In step 2, as shown in fig. 2A, an insulating layer 204 is formed on the front surface of the chip wafer, and then the insulating layer is removed by photolithography at a position corresponding to the chip pad 202 to form a through hole and a first circuit pattern is formed by photolithography. For example, the insulating layer may be an inorganic material such as silicon oxide, silicon oxynitride, borosilicate glass, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated glass silicate glass (FSG), or a low-K dielectric; the material may be an organic material such as polyimide, photosensitive epoxy resin, solder resist ink, green paint, dry film, photosensitive build-up material, BCB (bis-benzocyclobutene resin) or PBO (phenyl benzobisoxazole resin). The insulating layer can be manufactured by rolling, spin coating, spraying, printing, non-rotary coating, hot pressing, vacuum pressing, soaking, pressure fitting and the like.
In step 3, as shown in fig. 2A, a first redistribution layer 205 located in the insulating layer 204 and electrically connected to the chip pad 202 through the via is fabricated. In one embodiment of the present invention, the first rewiring layer may be formed by plating a metal on the first line pattern.
In step 4, as shown in fig. 2A, the chip wafer is diced into individual chips to form the first package 02. The cutting method of the chip wafer comprises mechanical cutting, laser cutting and plasma cutting. The first package body 02 includes a first chip 101, a chip pad 102, a molding layer 103, an insulating layer 104, and a first rewiring layer 105.
In step 5, as shown in fig. 2B, a substrate dielectric layer 206 is formed around the first package body 02. In one embodiment of the present invention, the first package 02 may be embedded within an FCBGA substrate as a local high-density interconnect structure within the substrate for bridging two or more chips subsequently mounted on the FCBGA substrate.
In step 6, as shown in fig. 2C, a substrate via 207 is made through the substrate dielectric. In one embodiment of the present invention, the substrate via is formed by laser drilling and then electroless or electrolytic plating of metal in the via.
Step 7, as shown in fig. 2D, a second redistribution layer 208 electrically connected to the substrate via 207 is fabricated. In one embodiment of the present invention, when the second rewiring layer 208 is fabricated, an exposure paste is applied, a circuit pattern is formed by exposure and development, and a metal is plated on the circuit pattern to form the second rewiring layer.
At step 8, as shown in fig. 2E, substrate buildup layers 209 are formed on the front and back surfaces of the first package body 02 and the substrate dielectric layer 206 by a vacuum lamination process. Wherein the substrate stack layer 109 includes an upper substrate stack layer and a lower substrate stack layer.
In step 9, blind vias 210 are fabricated in the substrate build-up layer, as shown in fig. 2F. The blind holes in the upper substrate accumulation layer are electrically connected with the first rewiring layer, and the blind holes in the lower substrate accumulation layer are electrically connected with part of the second rewiring layer. When the blind holes are manufactured, laser drilling is firstly carried out, and then chemical plating or metal plating is carried out in the holes to form the blind holes.
In step 10, as shown in fig. 2G, conductive lines and pads 211 are formed on the upper and lower surfaces of the substrate stack layer. Wherein a portion of the bonding pads are electrically connected to the blind vias 210.
At step 11, bumps 212 are formed on the pads and blind vias on the upper surface of the substrate build-up layer, as shown in fig. 2H.
At step 12, the functional chip is soldered to bumps 212 as shown in fig. 2H. The functional chips 213a and 213b are soldered to the bumps 212.
In step 13, as shown in fig. 2I, the BGA solder balls 214 are implanted on the pads on the lower surface of the substrate build-up layer.
The invention has at least the following beneficial effects: the invention provides a multi-chip high-density interconnection packaging structure and a manufacturing method thereof.
Although some embodiments of the present invention have been described herein, those skilled in the art will appreciate that they have been presented by way of example only. Numerous variations, substitutions and modifications will occur to those skilled in the art in light of the teachings of the present invention without departing from the scope thereof. It is intended that the following claims define the scope of the invention and that methods and structures within the scope of these claims and their equivalents be covered thereby.

Claims (9)

1. A multi-chip high density interconnect package structure comprising:
a first package comprising:
a first chip;
a chip pad on a front side of the first chip;
an insulating layer covering the first chip;
a first rewiring layer located in the insulating layer and electrically connected to the chip pad; a substrate dielectric layer disposed around the first package body;
a substrate through hole penetrating through the substrate dielectric layer;
the second rewiring layers are arranged on the front surface and the back surface of the substrate dielectric layer and the back surface of the first packaging body;
the substrate accumulation layer wraps the first packaging body and the substrate dielectric layer and comprises an upper substrate accumulation layer and a lower substrate accumulation layer;
blind holes in the upper and lower substrate buildup layers;
a substrate pad positioned on an upper surface of the upper substrate buildup layer and a lower surface of the lower substrate buildup layer;
the salient point is electrically connected with the blind hole in the upper substrate accumulation layer and the pad on the upper surface of the upper substrate accumulation layer; and
one or more functional chips electrically connected with the bumps.
2. The multi-chip high density interconnect package structure of claim 1, wherein said first package body further comprises a molding layer disposed around said first chip.
3. The multi-chip high density interconnect package structure of claim 1, wherein the second re-routing layers disposed on the front and back sides of the substrate dielectric layer are electrically connected to the substrate vias.
4. The multi-chip high density interconnect package of claim 1, wherein the blind via in the upper substrate stack is electrically connected to a first redistribution layer and the blind via in the lower substrate stack is electrically connected to a second redistribution layer.
5. The multi-chip high density interconnect package structure of claim 1, wherein a portion of the substrate pads located on the lower surface of the lower substrate build-up layer are electrically connected to the blind vias.
6. The multi-chip high density interconnect package of claim 1 further comprising BGA solder balls electrically connected to pads on a lower surface of said lower substrate stack layer.
7. The multi-chip high density interconnect package structure of claim 1, wherein the bump material is a tin-silver-copper alloy, a tin-silver alloy, or a copper pillar + tin-silver alloy.
8. A manufacturing method of a multi-chip high-density interconnection packaging structure comprises the following steps:
forming a plastic packaging layer on the periphery of the chip to form a reconstructed wafer;
manufacturing an insulating layer on the front surface of the wafer, and then removing the insulating layer at a position corresponding to the chip bonding pad through photoetching to form a through hole and photoetching to form a first circuit pattern;
manufacturing a first rewiring layer which is positioned in the insulating layer and penetrates through the through hole to be electrically connected with the chip bonding pad;
cutting the wafer into single chips to form a first packaging body;
forming a substrate dielectric layer around the first packaging body;
manufacturing a substrate through hole penetrating through a substrate medium;
manufacturing a second rewiring layer electrically connected to the through hole of the substrate;
forming substrate accumulation layers on the front and back surfaces of the first packaging body and the substrate dielectric layer through a vacuum lamination process;
manufacturing blind holes in the substrate accumulation layer;
manufacturing welding pads on the upper surface and the lower surface of the substrate accumulation layer;
forming salient points on the bonding pads and the blind holes on the upper surface of the substrate accumulation layer;
welding the chip and the bump; and
and implanting BGA solder balls on the bonding pads on the lower surface of the substrate accumulation layer.
9. The method of claim 8, wherein the substrate via and the blind via are formed by laser drilling and then electroless or electrolytic plating of metal in the via.
CN202111525572.8A 2021-12-14 2021-12-14 Multi-chip high-density interconnection packaging structure and manufacturing method thereof Pending CN114203691A (en)

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Application Number Priority Date Filing Date Title
CN202111525572.8A CN114203691A (en) 2021-12-14 2021-12-14 Multi-chip high-density interconnection packaging structure and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111525572.8A CN114203691A (en) 2021-12-14 2021-12-14 Multi-chip high-density interconnection packaging structure and manufacturing method thereof

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CN114203691A true CN114203691A (en) 2022-03-18

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