CN114203639A - Gate dielectric repair for three node access device formation for vertical 3D memory - Google Patents

Gate dielectric repair for three node access device formation for vertical 3D memory Download PDF

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Publication number
CN114203639A
CN114203639A CN202110994278.5A CN202110994278A CN114203639A CN 114203639 A CN114203639 A CN 114203639A CN 202110994278 A CN202110994278 A CN 202110994278A CN 114203639 A CN114203639 A CN 114203639A
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vertical
gate dielectric
region
conductive material
source
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J·A·斯迈思三世
G·S·桑胡
A·赛伊迪·瓦赫达
李时雨
S·E·西里斯
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Micron Technology Inc
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Micron Technology Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/816—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout for an application-specific layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0403—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals during or with feedback to manufacture
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

A method for forming a vertically stacked memory cell array having horizontally oriented access devices and vertically oriented access lines includes depositing alternating layers of dielectric material and sacrificial material to form a vertical stack. A plurality of first vertical openings are formed to form elongated vertical pillars in the vertical stack. A gate dielectric is conformally deposited in the first plurality of vertical openings and a conductive material is formed thereon. Portions of the conductive material are removed to form a plurality of access lines. The first side of the gate dielectric is repaired. A second vertical opening is formed to expose sidewalls of the first region adjacent the sacrificial material. The sacrificial material in the first region is selectively removed to form a first horizontal opening. The second side of the gate dielectric is repaired. A first source/drain region, a channel region, and a second source/drain region are deposited in the first horizontal opening.

Description

Gate dielectric repair for three node access device formation for vertical 3D memory
Technical Field
The present disclosure relates generally to memory devices, and more particularly, to gate dielectric repair with respect to three-node access device formation for vertical three-dimensional (3D) memories.
Background
Memory is typically implemented in electronic systems such as computers, cell phones, handheld devices, and the like. There are many different types of memory, including volatile and non-volatile memory. Volatile memory requires power to maintain its data and may include Random Access Memory (RAM), Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), and Synchronous Dynamic Random Access Memory (SDRAM). Non-volatile memory may provide persistent data by preserving stored data when power is not supplied, and may include NAND flash memory, NOR flash memory, non-volatile read-only memory (NROM), phase change memory (e.g., phase change random access memory), resistive memory (e.g., resistive random access memory), cross-point memory, ferroelectric random access memory (FeRAM), or the like.
As design rules tighten, less semiconductor space is available for manufacturing memory, including DRAM arrays. Respective memory cells of a DRAM may include an access device, such as a transistor, having first and second source/drain regions separated by a channel region. A gate may be opposite the channel region and separated therefrom by a gate dielectric. An access line, such as a wordline, is electrically connected to the gate of the DRAM cell. The DRAM cell may include a storage node, such as a capacitor cell, coupled to a digit line through an access device. The access device may be activated (e.g., to select a cell) by an access line coupled to an access transistor. The capacitor may store a charge corresponding to a data value (e.g., a logical "1" or "0") of the respective cell.
Disclosure of Invention
In accordance with an embodiment of the present disclosure, a method is provided for forming a vertically stacked array of memory cells having horizontally oriented access devices and vertically oriented access lines, and the method comprises the steps of: depositing alternating layers of dielectric material (430-1, …, 430-N; 530-1, …, 530-N; 630-1, …, 630-N; 730-1, …, 730-N; 830-1, …, 830-N; 930-1, …, 930-N; 1030-1, 1030-2; 1130-1, 1130-2; 1230-1, 1230-2; 1330-1, 1330-2; 1430-1, 1430-2; 1530-1, 1530-2; 1630-1, 1630-2; 1730-1, 1730-2) and sacrificial material (432-1, …, 432-N; 532-1, …, 532-N; 632-1, …, 632-N; 732-1, …, 732-N) to form a vertical stack; forming a plurality of first vertical openings (500) having a first horizontal direction (109, 209, 309, 509, 609, 709, 809, 909, 1009, 1109, 1209, 1309, 1409, 1509, 1609) and a second horizontal direction (105, 205, 305, 505, 605, 705, 805, 905, 1005, 1105, 1205, 1305, 1405, 1505, 1605, 1705), through the vertical stack to a substrate, and extending primarily in the second horizontal direction to form elongated vertical pillars (513, 542-1, 542-2, 542-3) having sidewalls (514) in the vertical stack; conformally depositing a gate dielectric (304, 538, 638, 738, 838, 938, 1038, 1138, 1238, 1338, 1438, 1538, 1638) in the plurality of first vertical openings; forming a conductive material (540-1, 540-2, 540-3, 540-4) on the gate dielectric; removing portions of the conductive material to form a plurality of separate, vertical access lines (640-1, …, 640-N, 640- (N +1), …, 640- (Z-1), 640-Z; 740-1, …, 740-N, 740- (N +1), …, 740- (Z-1), 740-Z; 840-1, …, 840-N, 840- (N +1), …, 840- (Z-1), 840-Z; 940-1, …, 940-N, 940- (N +1), …, 940- (Z-1), 940-Z; 1040-2, 1040-3; 1140-2, 1140-3; 1240-2, 1240-3; 1340-2, 1340-3; 1340-1, 740-1), 740-Z, 840-1, 840-Z, 840-1, 1140-Z, 1140-1, and/or portions of the conductive material along the sidewalls of the elongated vertical pillars, 1340-3; 1440-2, 1440-3; 1540-2, 1540-3; 1640-2, 1640-3; 1740-3); repairing a first side of the gate dielectric exposed at the conductive material removal (645); forming second vertical openings (871-1, 871-2; 971-1, 971-2; 1071-1; 1171-1; 1271-1; 1371-1; 1471-1, 1571-1; 1671-1) through the vertical stack and extending primarily in the first horizontal direction to expose sidewalls of first regions (742; 842; 942; 1042, 1142; 1242; 1342; 1424; 1542; 1642; 1742) adjacent the sacrificial material; selectively removing the sacrificial material in the first region a first horizontal distance from the second vertical opening to form a first horizontal opening (833-1, …, 833-N); and depositing a first source/drain region (998-1A), a channel region (998-1B, …, 998-NB), and a second source/drain region (998-1C) in the first horizontal opening.
In accordance with an embodiment of the present disclosure, a method is provided for forming a vertically stacked array of memory cells having horizontally oriented access devices and vertically oriented access lines, and the method comprises the steps of: depositing alternating layers of dielectric material (430-1, …, 430-N; 530-1, …, 530-N; 630-1, …, 630-N; 730-1, …, 730-N; 830-1, …, 830-N; 930-1, …, 930-N; 1030-1, 1030-2; 1130-1, 1130-2; 1230-1, 1230-2; 1330-1, 1330-2; 1430-1, 1430-2; 1530-1, 1530-2; 1630-1, 1630-2; 1730-1, 1730-2) and sacrificial material (432-1, …, 432-N; 532-1, …, 532-N; 632-1, …, 632-N; 732-1, …, 732-N) to form a vertical stack; forming a plurality of first vertical openings (500) having a first horizontal direction (109, 209, 309, 509, 609, 709, 809, 909, 1009, 1109, 1209, 1309, 1409, 1509, 1609) and a second horizontal direction (105, 205, 305, 505, 605, 705, 805, 905, 1005, 1105, 1205, 1305, 1405, 1505, 1605, 1705), through the vertical stack, and extending primarily in the second horizontal direction to form elongated vertical pillars (513, 542-1, 542-2, 542-3) having sidewalls (514) in the vertical stack; conformally depositing a gate dielectric (304, 538, 638, 738, 838, 938, 1038, 1138, 1238, 1338, 1438, 1538, 1638) in the plurality of first vertical openings; forming a conductive material (540-1, 540-2, 540-3, 540-4) on the gate dielectric; removing portions of the conductive material to form a plurality of separate, vertical access lines (640-1, …, 640-N, 640- (N +1), …, 640- (Z-1), 640-Z; 740-1, …, 740-N, 740- (N +1), …, 740- (Z-1), 740-Z; 840-1, …, 840-N, 840- (N +1), …, 840- (Z-1), 840-Z; 940-1, …, 940-N, 940- (N +1), …, 940- (Z-1), 940-Z; 1040-2, 1040-3; 1140-2, 1140-3; 1240-2, 1240-3; 1340-2, 1340-3; 1440-2, 1440-3; 1540-2; 940-1, 940-3), 1540-3; 1640-2, 1640-3; 1740-3); repairing a first side of the gate dielectric exposed at the conductive material removal (645); forming second vertical openings (871-1, 871-2; 971-1, 971-2; 1071-1; 1171-1; 1271-1; 1371-1; 1471-1, 1571-1; 1671-1) through the vertical stack and extending primarily in the first horizontal direction to expose sidewalls of first regions (742; 842; 942; 1042, 1142; 1242; 1342; 1424; 1542; 1642; 1742) adjacent the sacrificial material; selectively removing the sacrificial material in the first region a first horizontal distance from the second vertical opening to form a first horizontal opening (833-1, …, 833-N); repairing a second side (846) of the gate dielectric exposed to removal of the sacrificial material in the first region; and sequentially depositing a first source/drain region (998-1A), a channel region (998-1B, …, 998-NB), and a second source/drain region (998-1C) in the first horizontal opening to form a horizontally oriented three node access device (938-1, …, 938-N; 1038; 1138; 1238; 1338; 1438; 1538; 1638).
In accordance with an embodiment of the present disclosure, a method is provided for forming a vertically stacked array of memory cells having horizontally oriented access devices and vertically oriented access lines, and the method comprises the steps of: depositing alternating layers of dielectric material (430-1, …, 430-N; 530-1, …, 530-N; 630-1, …, 630-N; 730-1, …, 730-N; 830-1, …, 830-N; 930-1, …, 930-N; 1030-1, 1030-2; 1130-1, 1130-2; 1230-1, 1230-2; 1330-1, 1330-2; 1430-1, 1430-2; 1530-1, 1530-2; 1630-1, 1630-2; 1730-1, 1730-2) and sacrificial material (432-1, …, 432-N; 532-1, …, 532-N; 632-1, …, 632-N; 732-1, …, 732-N) to form a vertical stack; forming a plurality of first vertical openings (500) having a first horizontal direction (109, 209, 309, 509, 609, 709, 809, 909, 1009, 1109, 1209, 1309, 1409, 1509, 1609) and a second horizontal direction (105, 205, 305, 505, 605, 705, 805, 905, 1005, 1105, 1205, 1305, 1405, 1505, 1605, 1705), through the vertical stack to a substrate, and extending primarily in the second horizontal direction to form elongated vertical pillars (513, 542-1, 542-2, 542-3) having sidewalls (514) in the vertical stack; conformally depositing a gate dielectric material (304, 538, 638, 738, 838, 938, 1038, 1138, 1238, 1338, 1438, 1538, 1638) in the plurality of first vertical openings; forming a conductive material (540-1, 540-2, 540-3, 540-4) on the gate dielectric; removing portions of the conductive material to form a plurality of separate, vertical access lines (640-1, …, 640-N, 640- (N +1), …, 640- (Z-1), 640-Z; 740-1, …, 740-N, 740- (N +1), …, 740- (Z-1), 740-Z; 840-1, …, 840-N, 840- (N +1), …, 840- (Z-1), 840-Z; 940-1, …, 940-N, 940- (N +1), …, 940- (Z-1), 940-Z; 1040-2, 1040-3; 1140-2, 1140-3; 1240-2, 1240-3; 1340-2, 1340-3; 1340-1, 740-1), 740-Z, 840-1, 840-Z, 840-1, 1140-Z, 1140-1, and/or portions of the conductive material along the sidewalls of the elongated vertical pillars, 1340-3; 1440-2, 1440-3; 1540-2, 1540-3; 1640-2, 1640-3; 1740-3); repairing a first side of the gate dielectric material exposed to the conductive material removal (645); forming second vertical openings (871-1, 871-2; 971-1, 971-2; 1071-1; 1171-1; 1271-1; 1371-1; 1471-1, 1571-1; 1671-1) through the vertical stack and extending primarily in the first horizontal direction to expose sidewalls of first regions (742; 842; 942; 1042, 1142; 1242; 1342; 1424; 1542; 1642; 1742) adjacent the sacrificial material; selectively removing the sacrificial material in the first region a first horizontal distance from the second vertical opening to form a first horizontal opening (833-1, …, 833-N) to a first electrode (761; 861; 961; 1061; 1161; 1261; 1361; 1461; 1561, 1661; 1761) in a second region (744; 844; 944; 1044, 1144; 1244; 1344; 1444; 1544; 1644; 1744) of the vertical stack; repairing a second side (846) of the gate dielectric exposed to removal of the sacrificial material in the first region; repairing a surface of the first electrode in the second region; and depositing a first source/drain region (998-1A), a channel region (998-1B, …, 998-NB), and a second source/drain region (998-1C) in the first horizontal opening.
Drawings
Fig. 1 is a schematic diagram of a vertical three-dimensional (3D) memory according to several embodiments of the present disclosure.
Figure 2 is a perspective view illustrating a portion of a three-node access device in a vertical three-dimensional (3D) memory array, according to several embodiments of the present disclosure.
Fig. 3 is a perspective view illustrating a portion of a three-node access device in a vertical three-dimensional (3D) memory cell, according to several embodiments of the present disclosure.
Figure 4 illustrates an example method for forming a vertically stacked array of memory cells in one stage of a semiconductor fabrication process to form a three-node access device, according to several embodiments of the present disclosure.
Fig. 5A-5B illustrate an example method for forming a vertically stacked array of memory cells with three-node horizontally oriented access devices and vertically oriented access lines in another stage of a semiconductor fabrication process, according to several embodiments of the present disclosure.
Fig. 6A-6E illustrate an example method for forming a vertically stacked array of memory cells having three-node horizontally oriented access devices and vertically oriented access lines in another stage of a semiconductor fabrication process, according to several embodiments of the present disclosure.
Fig. 7A-7E illustrate an example method for forming a vertically stacked array of memory cells with three-node horizontally oriented access devices and vertically oriented access lines in another stage of a semiconductor fabrication process, according to several embodiments of the present disclosure.
Fig. 8A-8E illustrate an example method for forming a vertically stacked array of memory cells with three-node horizontally oriented access devices and vertically oriented access lines in another stage of a semiconductor fabrication process, according to several embodiments of the present disclosure.
Fig. 9A-9E illustrate an example method for forming a vertically stacked array of memory cells with three-node horizontally oriented access devices and vertically oriented access lines in another stage of a semiconductor fabrication process, according to several embodiments of the present disclosure.
Fig. 10A-10D illustrate an example method for source/drain integration in a three-node horizontally oriented access device coupled to a horizontally oriented storage node at a particular point in time in a semiconductor fabrication process, according to several embodiments of the present disclosure.
Fig. 11A-11D illustrate an example method for source/drain integration in a three-node horizontally oriented access device at a particular point in time in a semiconductor fabrication process, according to several embodiments of the present disclosure.
Fig. 12A-12D illustrate an example method for source/drain integration in a three-node horizontally oriented access device at a particular point in time in a semiconductor fabrication process, according to several embodiments of the present disclosure.
Fig. 13A-13D illustrate an example method for source/drain integration in a three-node horizontally oriented access device at a particular point in time in a semiconductor fabrication process, according to several embodiments of the present disclosure.
Fig. 14A-14D illustrate an example method for source/drain integration in a three-node horizontally oriented access device at a particular point in time in a semiconductor fabrication process, according to several embodiments of the present disclosure.
Fig. 15A-15D illustrate an example method for source/drain integration in a three-node horizontally oriented access device at a particular point in time in a semiconductor fabrication process, according to several embodiments of the present disclosure.
Fig. 16A-16D illustrate an example method for source/drain integration in a three-node horizontally oriented access device at a particular point in time in a semiconductor fabrication process, according to several embodiments of the present disclosure.
FIG. 17 illustrates an example of a three-node horizontally oriented access device coupled to horizontally oriented storage nodes and coupled to vertically oriented access lines and horizontally oriented digit lines, in accordance with several fabrication techniques described herein.
Fig. 18 is a block diagram of an apparatus in the form of a computing system including a memory device, according to several embodiments of the present disclosure.
Detailed Description
Embodiments of the present disclosure describe a three-node access device for a vertical three-dimensional (3D) memory with gate dielectric repair. The three-node horizontal access device does not form a body region contact. As used herein, a three-node is intended to refer to an access device that includes: separated by a channel region (1) a first source/drain region and (2) a second source/drain region and (3) one or more gates opposite the channel region. In a three node access device, there is no direct electrical contact from the body contact line to the body region and/or channel of the access device that controls the body region or channel of the access device. Therefore, since it is not necessary to form this body contact, the semiconductor manufacturing process overhead is reduced.
Three-node horizontal access devices are integrated with vertical access lines and integrated with horizontal digit lines. According to an embodiment, a three node horizontal access device may be formed with gate dielectric repair to improve gate dielectric quality and horizontal three node access device performance. Furthermore, replacing the channel may provide a channel region with fewer minority carriers (e.g., may operate without minority carriers) thereby eliminating the need to control the body potential to the body region of the access device. The first and second source/drain regions may be formed using methods and material constructions such that contact with other nodes and replacement channel materials minimizes injection barriers, reduces contact resistance, and may increase output drive of an access device such as a Thin Film Transistor (TFT). The formation of dopant and silicide layers in the source/drain region formation process can also be avoided. Processes may be provided to repair and/or improve gate dielectric formation. Repair and/or improved gate dielectric formation may be performed in the current process flow of three-node access device formation for vertical three-dimensional (3D) memory. Advantages of the structures and processes described herein may include a lower off current (Ioff) for an access device than a silicon-based (Si-based) access device and/or an increased drive current and current drain-to-source (IDS) inductive input (IDS-Lin) under reduced gate/drain induced leakage (GIDL) and low applied drain-to-source gate potential (VDS) conditions for an access device.
In some embodiments, channel and/or source/drain region replacement manufacturing steps may be performed after the capacitor cell formation process, reducing the thermal budget. Digit line integration may be easier to implement in the manufacturing process because body contact to the body region of the access device is not used. In addition, the embodiments described herein may enable better lateral scaling paths than with doped polysilicon based channel regions due to smaller channel lengths and lower source/drain semiconductor manufacturing process overhead. Shorter access line (e.g., Word Line (WL)) lengths (L) may also be achieved due to lower off current (Ioff). Another benefit is the avoidance, e.g., non-use, of Gas Phase Doping (GPD) in the source/drain region formation.
The figures herein follow a numbering convention in which the first or first digit or digits correspond to the drawing figure number and the remaining digits identify an element or component in the drawing. Similar elements or components between different figures may be identified by the use of similar digits. For example, reference numeral 104 may refer to element "04" in FIG. 1, and a similar element may be referred to as 204 in FIG. 2. A number of similar elements within a figure may be referred to by a reference numeral followed by a succeeding character and another number or letter. For example, 302-1 may refer to element 302-1 in FIG. 3 and 302-2 may refer to element 302-2, which may be similar to element 302-1. Such similar elements may generally not require hyphenation and additional numeric or alphabetical designations. For example, elements 302-1 and 302-2 or other similar elements may be generally referred to as 302.
Fig. 1 is a block diagram of an apparatus according to several embodiments of the present disclosure. Fig. 1 illustrates a circuit diagram showing a cell array of a three-dimensional (3D) semiconductor memory device according to an embodiment of the present disclosure. FIG. 1 illustrates that a cell array may have multiple sub-cell arrays 101-1, 101-2, …, 101-N. The sub cell arrays 101-1, 101-2, …, 101-N may be arranged along a second direction (D2) 105. Each of the subcell arrays, such as subcell array 101-2, may include a plurality of access lines 103-1, 103-2, …, 103-Q (which may also be referred to as word lines). Also, each of the sub-cell arrays, such as sub-cell array 101-2, may include a plurality of digit lines 107-1, 107-2, …, 107-P (which may also be referred to as bit lines, data lines, or sense lines). In FIG. 1, digit lines 107-1, 107-2, …, 107-P are illustrated as extending in a first direction (D1)109 and access lines 103-1, 103-2, …, 103-Q are illustrated as extending in a third direction (D3) 111. According to an embodiment, the first direction (D1)109 and the second direction (D2)105 may be considered to be in a horizontal ("X-Y") plane. The third direction (D3)111 may be considered to be in the vertical ("Z") plane. Thus, according to embodiments described herein, the access lines 103-1, 103-2, …, 103-Q extend in a vertical direction (e.g., the third direction (D3) 111).
A memory cell, such as 110, may include an access device, such as an access transistor, and a storage node positioned at the intersection of each access line 103-1, 103-2, …, 103-Q and each digit line 107-1, 107-2, …, 107-P. Memory cells can be written to or read from using access lines 103-1, 103-2, …, 103-Q and digit lines 107-1, 107-2, …, 107-P. Digit lines 107-1, 107-2, …, 107-P may conductively interconnect memory cells along horizontal columns of each sub-cell array 101-1, 101-2, …, 101-N, and access lines 103-1, 103-2, …, 103-Q may conductively interconnect memory cells along vertical rows of each sub-cell array 101-1, 101-2, …, 101-N. One memory cell (e.g., 110) may be positioned between one access line (e.g., 103-2) and one digit line (e.g., 107-2). Each memory cell is uniquely addressable by a combination of an access line 103-1, 103-2, …, 103-Q and a digit line 107-1, 107-2, …, 107-P.
The digit lines 107-1, 107-2, …, 107-P may be or include conductive patterns (e.g., metal lines) disposed on and spaced apart from a substrate. Digit lines 107-1, 107-2, …, 107-P may extend in a first direction (D1) 109. Digit lines 107-1, 107-2, …, 107-P in one array of subcells (e.g., 101-2) may be spaced apart from each other in a vertical direction (e.g., in the third direction (D3) 111).
The access lines 103-1, 103-2, …, 103-Q may be or include conductive patterns (e.g., metal lines) extending in a vertical direction with respect to the substrate (e.g., in the third direction (D3) 111). The access lines in one array of subcells (e.g., 101-2) may be spaced apart from each other in a first direction (D1) 109.
The gate of a memory cell, such as memory cell 110, may be connected to an access line, such as 103-2, and a first conductive node, such as a first source/drain region, of an access device, such as a transistor, of memory cell 110 may be connected to a digit line, such as 107-2. Each of the memory cells, such as memory cell 110, may be connected to a storage node, such as a capacitor. A second conductive node (e.g., a second source/drain region) of an access device (e.g., a transistor) of the memory cell 110 may be connected to a storage node (e.g., a capacitor). Although first and second source/drain regions are referred to herein for identifying two separate and distinct source/drain regions, source/drain regions that are not referred to as "first" and/or "second" source/drain regions are not intended to have some unique meaning. It is only desirable that one of the source/drain regions be connected to a digit line (e.g., 107-2) and the other can be connected to a storage node.
Figure 2 illustrates a perspective view showing a three-dimensional (3D) semiconductor memory device, such as a portion of the sub-cell array 101-2 shown in figure 1 as a vertically oriented stack of memory cells in the array, in accordance with some embodiments of the present disclosure. Fig. 3 illustrates a perspective view showing a unit cell (such as the memory cell 110 shown in fig. 1) of the 3D semiconductor memory device shown in fig. 2.
As shown in fig. 2, the substrate 200 may have formed thereon one of the plurality of sub-cell arrays (e.g., 101-2) described with respect to fig. 1. For example, the substrate 200 may be or include a silicon substrate, a germanium substrate, a silicon-germanium substrate, or the like. However, embodiments are not limited to these examples.
As shown in the example embodiment of fig. 2, substrate 200 may have fabricated thereon a vertically oriented stack of memory cells (such as memory cell 110 in fig. 1) extending in a vertical direction (such as third direction (D3) 211). According to some embodiments, a vertically oriented stack of memory cells may be fabricated such that each memory cell, such as memory cell 110 in fig. 1, is formed on multiple vertical levels, such as a first level (L1), a second level (L2), and a third level (L3). The repeating vertical levels L1, L2, and L3 may be arranged (e.g., "stacked") in a vertical direction, such as the third direction (D3)211 shown in fig. 2. Each of the repeating vertical levels L1, L2, and L3 may include a plurality of discrete components (e.g., regions) to a laterally oriented access device 230 (e.g., a transistor) and a storage node (e.g., a capacitor) including access line 103-1, 103-2, …, 103-Q connections and digit line 107-1, 107-2, …, 107-P connections. A plurality of discrete components to a horizontally oriented three-node access device, such as transistor 110 in fig. 1, may be formed within each level in multiple iterations of a vertically repeating layer, as described in more detail below with respect to fig. 4 and below, and may extend horizontally in a second direction (D2)205, similar to the second direction (D2)105 shown in fig. 1.
A plurality of discrete components to a horizontally oriented three-node access device 230, such as a transistor, may include a first source/drain region 221 and a second source/drain region 223 extending laterally in the second direction (D2)205 separated by a channel region 225. In some embodiments, the channel region 225 may comprise silicon, germanium, silicon germanium, and/or Indium Gallium Zinc Oxide (IGZO). In some embodiments, the first and second source/ drain regions 221 and 223 may include an n-type dopant region (e.g., semiconductor material) formed adjacent to a p-type doped channel region (e.g., semiconductor material) of the access device to form an n-type conductivity transistor. In some embodiments, the first and second source/ drain regions 221 and 223 may comprise a p-type conductivity (e.g., doped semiconductor material) formed adjacent to an n-type conductivity channel region (e.g., doped semiconductor material) of the access device to form a p-type conductivity transistor. By way of example and not by way of limitation, the n-type dopant may comprise phosphorus (P) atoms and the P-type dopant may comprise boron (B) atoms formed in oppositely doped body regions of the polysilicon semiconductor material. However, embodiments are not limited to these examples.
Storage node 227, such as a capacitor, may be connected to one respective end of the access device. As shown in fig. 2, a storage node 227, such as a capacitor, may be connected to the second source/drain region 223 of the access device. A storage node may be or include a memory element capable of storing data. Each of the storage nodes may be a memory element using one of a capacitor including a phase change material or the like, a magnetic tunneling junction pattern, and/or a variable resistance body. However, embodiments are not limited to these examples. In some embodiments, the storage nodes associated with each access device of a unit cell, such as memory cell 110 in FIG. 1, may similarly extend in the second direction (D2)205 (similar to the second direction (D2)105 shown in FIG. 1).
As shown in FIG. 2, a plurality of horizontally oriented digit lines 207-1, 207-2, …, 207-P extend in a first direction (D1)209 (similar to first direction (D1)109 in FIG. 1). The plurality of horizontally oriented digit lines 207-1, 207-2, …, 207-P may be similar to the digit lines 107-1, 107-2, …, 107-P shown in fig. 1. A plurality of horizontally oriented digit lines 207-1, 207-2, …, 207-P may be arranged, e.g., "stacked," along a third direction (D3) 211. The plurality of horizontally oriented digit lines 207-1, 207-2, …, 207-P may comprise a conductive material. For example, the conductive material may include one or more of a doped semiconductor (e.g., doped silicon, doped germanium, etc.), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), a metal (e.g., tungsten (W), titanium (Ti), tantalum (Ta), etc.), and/or a metal semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.). However, embodiments are not limited to these examples.
In each of vertical levels (L1)213-1, (L2)213-2, and (L3)213-M, horizontally oriented memory cells, such as memory cell 110 in FIG. 1, may be horizontally spaced apart from one another in first direction (D1) 209. However, as described in more detail below with respect to fig. 4 and below, a plurality of discrete components, such as first and second source/ drain regions 221, 223 extending laterally in the second direction (D2)205 and a plurality of horizontally oriented digit lines 207-1, 207-2, …, 207-P extending laterally in the first direction (D1)209, separated by a channel region 225 to a laterally oriented access device 230 may be formed within different vertical layers within each level. For example, a plurality of horizontally oriented digit lines 207-1, 207-2, …, 207-P extending in the first direction (D1)209 may be disposed on and in electrical contact with a top surface of the first source/drain region 221 and orthogonal to a laterally oriented access device 230 (e.g., a transistor) extending laterally in the second direction (D2) 205. In some embodiments, a plurality of horizontally oriented digit lines 207-1, 207-2, …, 207-P extending in a first direction (D1)209 are formed within a level, such as within level (L1), in a vertical layer higher, farther from the substrate 200 than the layer in which the discrete components of the laterally oriented access device are formed, such as the first source/drain region 221 and the second source/drain region 223 separated by the channel region 225. In some embodiments, a plurality of horizontally oriented digit lines 207-1, 207-2, …, 207-P extending in the first direction (D1)209 may be connected to the top surface of the first source/drain region 221 directly and/or through additional contacts comprising metal silicide.
As shown in the example embodiment of FIG. 2, the access lines 203-1, 203-2, …, 203-Q extend in a vertical direction with respect to the substrate 200 (e.g., in a third direction (D3) 211). Furthermore, as shown in FIG. 2, access lines 203-1, 203-2, …, 203-Q in one sub-cell array (e.g., sub-cell array 101-2 in FIG. 1) may be spaced apart from each other in first direction (D1) 209. Access lines 203-1, 203-2, …, 203-Q may be provided extending vertically in a third direction (D3)211 relative to the substrate 200 between a pair of horizontally oriented three-node access devices 230 (e.g., transistors) that extend laterally in the second direction (D2)205 but are adjacent to each other in the first direction (D1)209 in a level, such as a first level (L1). Each of the access lines 203-1, 203-2, …, 203-Q may extend vertically in a third direction (D3) on sidewalls of a respective one of a vertically stacked plurality of horizontally oriented three-node access devices 230, such as transistors.
For example, and as shown in more detail in fig. 3, a first one of the vertically extending access lines (e.g., 203-1) may be adjacent to a sidewall of the channel region 225 of a first one of the horizontally oriented three-node access devices 230 (e.g., transistors) in the first level (L1)213-1, a sidewall of the channel region 225 of a first one of the horizontally oriented three-node access devices 230 (e.g., transistors) in the second level (L2)213-2, and a sidewall of the channel region 225 of a first one of the horizontally oriented three-node access devices 230 (e.g., transistors) in the third level (L3)213-M, and so on. Similarly, a second one of the vertically extending access lines (e.g., 203-2) may be adjacent a sidewall of the channel region 225 in the first level (L1)213-1 to a second one of the horizontally oriented three-node access devices 230 (e.g., transistors) that is spaced apart from a first one of the horizontally oriented three-node access devices 230 (e.g., transistors) in the first level (L1)213-1 in the first direction (D1) 209. And a second one of the vertically extending access lines (e.g., 203-2) may be adjacent to a sidewall of the channel region 225 of a second one of the horizontally oriented three-node access devices 230 (e.g., transistors) in the second level (L2)213-2 and a sidewall of the channel region 225 of a second one of the horizontally oriented three-node access devices 230 (e.g., transistors) in the third level (L3)213-M, and so on. Embodiments are not limited to a particular number of levels.
The vertically extending access lines 203-1, 203-2, …, 203-Q may comprise a conductive material, such as, for example, one of a doped semiconductor material, a conductive metal nitride, a metal, and/or a metal semiconductor compound. The access lines 203-1, 203-2, …, 203-Q may correspond to Word Lines (WLs) described with respect to FIG. 1.
As shown in the example embodiment of fig. 2, an Insulating Layer Dielectric (ILD)250 extending along the end faces of the horizontally oriented three-node access device 230, such as a transistor, in the first direction (D1)209 may be formed in each level (L1)213-1, (L2)213-2, and (L3)213-M above the substrate 200. The ILD 250 may isolate and separate the vertically stacked arrays of memory cells (e.g., 101-1, 101-2, …, 101-N) in FIG. 1 along the second direction (D2) 205. The ILD 250 may comprise an insulating material such as a dielectric material, such as, for example, an oxide material, silicon dioxide (SiO)2) A material, a silicon nitride (SiN) material, a silicon oxynitride material, combinations thereof, and/or the like.
Although not shown in fig. 2, the insulating material may fill other spaces in the vertically stacked array of memory cells. For example, the insulating material may include one or more of a silicon oxide material, a silicon nitride material, and/or a silicon oxynitride material, among others. However, embodiments are not limited to these examples.
Fig. 3 illustrates in more detail a unit cell (e.g., memory cell 110 in fig. 1) of a vertically stacked array of memory cells (e.g., within subcell array 101-2 in fig. 1) according to some embodiments of the present disclosure. As shown in fig. 3, the first and second source/ drain regions 321 and 323 may be impurity doped regions to a horizontally oriented three-node access device 330, such as a transistor. First and second source-The drain regions 321 and 323 may further include a metal and/or a metal composite containing ruthenium (Ru), molybdenum (Mo), nickel (Ni), titanium (Ti), copper (Cu), a highly doped degenerate semiconductor material, and/or indium oxide (In) formed using an atomic layer deposition process, etc2O3) Or indium tin oxide (In)2-xSnxO3) At least one of (a). However, embodiments are not limited to these examples. As used herein, degenerate semiconductor material is intended to mean a semiconductor material (e.g., polysilicon) that contains a high degree of doping and significant interactions between dopants (e.g., phosphorus (P), boron (B), etc.). In contrast, non-degenerate semiconductors contain moderate doping, where the dopant atoms are well separated from each other in the semiconductor host lattice and have negligible interactions. The first and second source/ drain regions 321 and 323 may be similar to the first and second source/ drain regions 221 and 223 shown in fig. 2.
The first and second source/drain regions may be separated by a channel 325 (e.g., a channel region) of a horizontally oriented three-node access device 330 (e.g., a transistor). The channel 325 may be a low-doped (p-) polysilicon material. In some embodiments, the channel 325 may be a low-doped (p-) polycrystalline germanium (Ge) material. In some embodiments, the channel 325 may be a low-doped (p-) polycrystalline silicon germanium (poly-SiGe) material. However, in some embodiments, the channel 325 may comprise a semiconductor oxide (also referred to herein as an "oxide semiconductor" or an "oxide semiconductor material"). The semiconductor oxide may comprise any suitable composition, and in some embodiments may comprise one or more of indium, zinc, tin, and gallium. As used herein, examples of oxide semiconductor materials and/or compositions comprising one or more of indium, zinc, tin, and gallium may include materials such as: ZnO (zinc oxide)x、InOx、SnO2、ZnxOyN、MgxZnyOz、InxZnyOz、InxZnyOz、InxGayZnzOa、InxGaySizOa、ZrxInyZnzOa、HfxInyZnzOa、SnxInyZnzOa、AlxSnyInzZnaOb、SixInyZnzOa、ZnxSnyOz、AlxZnySnzOa、GaxZnySnzOaAnd ZrxZnySnzOa。
In additional embodiments, the channel 325 may comprise a two-dimensional (2D) material. The 2D material may comprise any suitable composition, and in some embodiments may comprise one or more transition metal dichalcogenides comprising molybdenum disulfide (MoS)2) Molybdenum diselenide (MoSe)2) Molybdenum ditelluride (MoTe)2) Tungsten sulfide (WS)2) And tungsten selenide (WSe)2). However, embodiments are not limited to these examples.
In some embodiments, the channel 325 may comprise a composite material, such as indium gallium zinc oxide (In)2Ga2ZnO7) A material (also referred to herein as "IGZO"). In some embodiments, the channel 325 is a multilayer IGZO channel material enriched In indium (In) In a first layer that is closest to a surface of the channel opposite the gate dielectric relative to the plurality of layers. In some embodiments, the channel 325 is a multilayer IGZO channel material rich in gallium (Ga) in an outer layer that is furthest away from a surface opposite the gate dielectric relative to the layers. In some embodiments, the channel 325 is a multilayer IGZO channel material enriched in zinc (Zn) in an outer layer that is furthest away from a surface opposite the gate dielectric relative to the layers, and so on. However, embodiments are not limited to these examples.
Digit lines similar to digit lines 207-1, 207-2, …, 207-P in fig. 2 and digit lines 107-1, 107-2, …, 107-P shown in fig. 1 (e.g., 307-1) may be formed in electrical contact with the first source/drain region 321. As used herein, the "first" and "second" source/drain labels are intended only to be separate and distinct source/drain regions, one connected to the digit line and the other connected to the storage node. As shown in the example embodiment of fig. 3, an access line (e.g., 303-1) similar to access lines 203-1, 203-2, …, 203-Q in fig. 2 and access lines 103-1, 103-2, …, 103-Q in fig. 1 may extend vertically in a third direction (D3)311 adjacent to sidewalls of a channel region 325 of a horizontally oriented three-node access device 330, such as a transistor that conducts horizontally between first and second source/ drain regions 321 and 323 along a second direction (D2) 305. Gate dielectric material 304 may be interposed between access line 303-1, a portion of which forms a gate to a horizontally oriented three-node access device 330, such as a transistor, and channel region 325. The gate dielectric material 304 may include, for example, a high-k dielectric material, a silicon oxide material, a silicon nitride material, a silicon oxynitride material, the like, or combinations thereof. In some embodiments, examples of high-k dielectric materials for the gate dielectric material 304 may include one or more of: hafnium, aluminum, scandium, lanthanum, zirconium, bismuth, niobium, which have a metal oxide structure. The gate dielectric material 304 can be formed by atomic layer deposition with a distinct metal-oxidant cycle that can sequence the metal-oxidant at temperatures ranging from about 25 degrees celsius (° c) to about 500 ℃ (preferably from about 200 ℃ to about 350 ℃). The embodiments are not limited thereto. For example, in the high-k dielectric material example, the gate dielectric material 304 may include one or more of: hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobite, and the like.
Fig. 4 illustrates an example method for forming a vertically stacked memory cell array having horizontally oriented access devices and vertically oriented access lines (such as illustrated in fig. 1-3) in one stage of a semiconductor fabrication process and in accordance with several embodiments of the present disclosure. In the example embodiment shown in the example of fig. 4, the method includes depositing alternating layers of dielectric material 430-1, 430-2, …, 430-N (also individually and/or collectively referred to herein as "430") and sacrificial material 432-1, 432-2, …, 432-N (also individually and/or collectively referred to herein as "432") in repeated iterations to form a vertical stack 401 on a working surface of a semiconductor substrate 400. In one embodiment, the dielectric material 430 may be deposited to have a thickness ranging from twenty (20) nanometers (nm) to sixty (60) nm, such as a vertical height in the third direction (D3). In one embodiment, the sacrificial material 432 may be deposited to have a thickness, such as a vertical height, ranging from twenty (20) nm to one hundred (100) nm. However, embodiments are not limited to these examples.
In one example, the sacrificial material 432-1, 432-2, …, 432-N may comprise a sacrificial semiconductor material, such as polysilicon (Si), silicon nitride (SiN), or even an oxide-based semiconductor composition. Although the discussion herein will refer to a sacrificial semiconductor material example, embodiments are not limited to this example. It is desirable that the sacrificial material be selectively etchable relative to the alternating layers of dielectric material 430-1, 430-2, …, 430-N.
As shown in fig. 4, the vertical direction 411 is illustrated as a third direction (D3), such as the z direction in an x-y-z coordinate system, similar to the third direction (D3) of the first, second, and third directions shown in fig. 1-3. In the example of fig. 4, four levels numbered 1, 2, 3, and 4 of repeated iterations of vertical stack 401 are shown. However, embodiments are not limited to this example and may include more or fewer iterations. A lithographic Hard Mask (HM) layer 435 may be deposited as a top layer on repeated iterations of the vertical stack 401.
In some embodiments, the dielectric materials 430-1, 430-2, …, 430-N may be interlayer dielectrics (ILD). By way of example, and not by way of limitation, the dielectric materials 430-1, 430-2, …, 430-N may include silicon dioxide (SiO)2) A material. In another example, the dielectric materials 430-1, 430-2, …, 430-N can include silicon nitride (Si)3N4) A material (also referred to herein as "SiN"). In another example, the dielectric materials 430-1, 430-2, …, 430-N can include silicon oxycarbide (SiO)xCy) A material (also referred to herein as "SiOC"). In another example, the dielectric materials 430-1, 430-2, …, 430-N can include silicon oxynitride (SiO)xNy) Materials (also referred to herein as "SiON") and/or combinations thereof. Embodiments are not limited to these examples. In some embodiments, the sacrificial semiconductor material 432-1, 432-2, …, 432-N may comprise silicon (Si) material in a polycrystalline and/or amorphous state. In another example, the sacrificeSemiconductor material 432-1, 432-2, …, 432-N may comprise a silicon nitride (SiN) material. However, embodiments are not limited to these examples.
Repeated iterations of alternating layers of dielectric material 430-1, 430-2, …, 430-N and sacrificial semiconductor material 432-1, 432-2, …, 432-N may be deposited in a semiconductor manufacturing apparatus according to a semiconductor manufacturing process, such as Chemical Vapor Deposition (CVD). However, embodiments are not limited to this example, but alternating layers of dielectric material 430-1, 430-2, …, 430-N and sacrificial semiconductor material 432-1, 432-2, …, 432-N may be deposited in repeated iterations using other suitable semiconductor fabrication techniques to form the vertical stack 401, as shown in FIG. 4.
Fig. 5A illustrates an example method for forming a vertically stacked memory cell array having horizontally oriented access devices and vertically oriented access lines (such as illustrated in fig. 1-3) in another stage of a semiconductor fabrication process and in accordance with several embodiments of the present disclosure. Fig. 5A illustrates a top view of a semiconductor structure at a particular point in time in a semiconductor fabrication process, in accordance with one or more embodiments. In the example embodiment shown in the example of fig. 5A, the method includes forming a plurality of access line vertical openings 500 (also referred to herein as "first" vertical openings) through the vertical stack to the substrate having a first horizontal direction (D1)509 and a second horizontal direction (D2)505 using an etchant process. In one example, as shown in fig. 5A, the plurality of first vertical openings 500 extend primarily in the second horizontal direction (D2)505 and may form elongated vertical pillars 513 having sidewalls 514 in the vertical stack. The plurality of first vertical openings 500 may be formed using a photolithographic technique to pattern a photolithographic mask 535 on the vertical stack prior to etching the plurality of first vertical openings 500, for example to form a Hard Mask (HM).
Figure 5B is a cross-sectional view of another view of the semiconductor structure showing a particular time in the semiconductor fabrication process, taken along cut line a-a' in figure 5A. Fig. 5B illustrates that conductive material 540-1, 540-2, …, 540-4 may be formed on the gate dielectric material 538 in the plurality of first vertical openings 500, as shown in fig. 5A. By way of example, and not by way of limitation, the gate dielectric material 538 may use chemical vapor depositionA (CVD) process, plasma enhanced CVD (pecvd), Atomic Layer Deposition (ALD), or other suitable deposition process is conformally deposited in the plurality of first vertical openings 500 to cover the bottom surfaces and vertical sidewalls of the plurality of first vertical openings. The gate dielectric 538 may be deposited to a particular thickness (t1) suitable for particular design rules, such as a gate dielectric thickness of about 10 nanometers (nm). However, embodiments are not limited to this example. By way of example, and not by way of limitation, gate dielectric 538 can include silicon dioxide (SiO)2) Material, alumina (Al)2O3) Materials, high dielectric constant (k) (e.g., high k) dielectric materials, and/or combinations thereof, as also depicted in fig. 3.
Furthermore, as shown in fig. 5B, conductive material 540-1, 540-2, …, 540-4 may be conformally deposited on the surface of gate dielectric material 538 in the plurality of first vertical openings 500. By way of example and not by way of limitation, the conductive material 540-1, 540-2, …, 540-4 may be conformally deposited on the surface of the gate dielectric material 538 in the plurality of first vertical openings 500 using a chemical vapor deposition process (CVD), plasma enhanced CVD (pecvd), Atomic Layer Deposition (ALD), or other suitable deposition process to cover the bottom surfaces and vertical sidewalls of the plurality of first vertical openings over the gate dielectric 538. The conductive material 540-1, 540-2, …, 540-4 may be conformally deposited to a particular thickness (t2) to form vertically oriented access lines, such as access lines 103-1, 103-2, …, 103-Q (which may also be referred to as word lines) shown in fig. 1 and below and adapted to particular design rules. For example, the conductive material 540-1, 540-2, …, 540-4 may be conformally deposited to a thickness of about 20 nanometers (nm). However, embodiments are not limited to this example. By way of example, and not by way of limitation, conductive materials 540-1, 540-2, …, 540-4 may comprise a metal such as tungsten (W), a metal composition, titanium nitride (TiN), doped polysilicon, and/or some other combination thereof, as also depicted in FIG. 3.
As shown in fig. 5B, the conductive material 540-1, 540-2, …, 540-4 may be recessed back to remain only along the vertical sidewalls of the elongated vertical pillars now shown as 542-1, 542-2, and 542-3 in the cross-sectional view of fig. 5B. The plurality of separate, vertical access lines formed from the conductive material 540-1, 540-2, …, 540-4 may be recessed back by removing the conductive material 540-1, 540-2, …, 540-4 from the bottom surface of the first vertical opening (e.g., 500 in fig. 5A) using a suitable selective anisotropic etch process, thereby exposing the gate dielectric 538 on the bottom surface to form separate, vertical access lines 540-1, 540-2, …, 540-4. As shown in fig. 5B, a dielectric material 539, such as an oxide or other suitable spin-on dielectric (SOD), may then be deposited in the first vertical opening 500 using a process such as CVD to fill the first vertical opening 500. The dielectric may be planarized to the top surface of the hard mask 535 of the vertical semiconductor stack (e.g., 401 shown in figure 4) using Chemical Mechanical Planarization (CMP) or other suitable semiconductor fabrication techniques. Subsequent photolithographic material 536 (e.g., a hard mask) may be deposited using CVD and planarized using CMP to cover and close the first vertical openings 500 over the separate, vertical access lines 540-1, 540-2, …, 540-4. Similar semiconductor process techniques may be used at other points of the semiconductor fabrication process described herein.
Fig. 6A illustrates an example method for forming a vertically stacked memory cell array having horizontally oriented access devices and vertically oriented access lines (such as illustrated in fig. 1-3) in another stage of a semiconductor fabrication process and in accordance with several embodiments of the present disclosure. Fig. 6A illustrates a top view of a semiconductor structure at a particular point in time in a semiconductor fabrication process, in accordance with one or more embodiments. In the example embodiment of fig. 6A, the method includes patterning the photolithographic mask 636 (536 in fig. 5B) using a photolithographic process. The method in FIG. 6A further illustrates removing portions of the exposed conductive material 540-1, 540-2, …, 540-4 in FIG. 5B using a selective isotropic etchant process to separate and individually form a plurality of separate, vertical access lines 640-1, 640-2, …, 640-N, 640- (N +1), …, 640- (Z-1), and 640-Z, such as access lines 103-1, 103-2, …, 103-Q in FIG. 1 and below. Thus, a plurality of separate, vertical access lines 640-1, 640-2, …, 640-N, 640- (N +1), …, 640- (Z-1), and 640-Z are shown along the sidewalls of elongated vertical pillars, such as along the sidewalls of elongated vertical pillars 542-1, 542-2, and 542-3 in the cross-sectional view of FIG. 5B.
As shown in the example of fig. 6A, the exposed conductive material 540-1, 540-2, …, 540-4 in fig. 5B may be removed back into the gate dielectric material 638 in the first vertical opening (e.g., 500 in fig. 5A) using a suitable selective isotropic etch process. As shown in fig. 6A, a subsequent dielectric material 641, such as an oxide or other suitable spin-on dielectric (SOD), can then be deposited to fill the remaining openings from where the exposed conductive material 540-1, 540-2, …, 540-4 in fig. 5B was removed using a process such as CVD or other suitable technique. The dielectric material 641 may be planarized to a top surface of a previous hard mask 635 of a vertical semiconductor stack (such as 401 shown in fig. 4) using a process such as CMP or other suitable technique. In some embodiments, a subsequent photolithographic material 537 (e.g., a hard mask) may be deposited using CVD and planarized using CMP to cover and close the plurality of separation, vertical access lines 640-1, 640-2, …, 640-N, 640- (N +1), …, 640- (Z-1), and 640-Z over the working surface of the vertical semiconductor stack 401 in FIG. 4, thereby protecting the plurality of separation, vertical access lines 640-1, 640-2, …, 640-N, 640- (N +1), …, 640- (Z-1), and 640-Z along the sidewalls of the elongated vertical pillars. However, the embodiments are not limited to these process examples.
In some embodiments, damage to the gate dielectric 638 may occur when portions of the exposed conductive material 540-1, 540-2, …, 540-4 in fig. 5B are removed. For example, the gate dielectric 638 may be exposed to the same selective isotropic etchant process used to remove the conductive materials 540-1, 540-2, …, 540-4 in FIG. 5B. Exposing gate dielectric 638 to a selective isotropic etchant process may damage gate dielectric 638 on first side 645, such as the regions in vertical access line trenches 500 in FIG. 5B that form the plurality of separate, vertical access lines 640-1, 640-2, …, 640-N, 640- (N +1), …, 640- (Z-1), and 640-Z. In some embodiments, the damage caused to the gate dielectric 638 may be repaired by providing a process to repair the damaged portion of the gate dielectric 638 and restore the insulating properties of the gate dielectric 638.
In some embodiments, Atomic Layer Deposition (ALD) of the liner 651 can be used to initiate repair of the gate dielectric 638. However, embodiments are not limited to these examples. For example, deposition of the dielectric liner 651 can include using remote ionization, oxygen or oxygen-containing species or a mixed-gas-in-ratio repair, which preferentially repairs the gate dielectric 638 while minimizing oxidation of the multiple detached, vertical access lines 640-1, 640-2, …, 640-N, 640- (N +1), …, 640- (Z-1), and 640-Z. Combinations that provide mixtures of molecular oxygen and ionized species may be most efficiently formed at temperatures ranging from about 150 degrees celsius (° c) to 600 ℃. Short pulses of metal atoms, such as hafnium (Hf), aluminum (Al), scandium (Sc), lanthanum (La), zirconium (Zr), etc., in precursor form of the gate dielectric 638 may be included to return the first side 645 (e.g., region) of the gate dielectric 638 to a desired stoichiometry. For example, ozone may be a process limited by the degree of interaction with a plurality of separate, vertical access lines 640-1, 640-2, …, 640-N, 640- (N +1), …, 640- (Z-1), and 640-Z gate electrode materials such as tantalum (Ta), titanium (Ti), tungsten (W), molybdenum (Mo), hafnium (Hf), ruthenium (Ru), and the like. The pulse of water vapor may also be used to return the structure of the gate dielectric 638, region 651 to the desired stoichiometry and surface bond termination.
In some embodiments, annealing or doping may be used to initiate repair of the gate dielectric 638. In some embodiments, a post-deposition anneal may be performed after Atomic Layer Deposition (ALD) of the liner 651, or doping may be used to flow a precursor to contact the first side 645 of the gate dielectric 638. The precursor may comprise a compound such as silane, hydroxy, ethyl, methyl or oxysilane. Subsequently, the first side 645 of the gate dielectric 638 may be exposed to thermal energy, plasma energy, microwaves, or other energy source to generate hydrogen gas (H)2) Oxygen (O)2) Nitrogen (N)2) Helium (He), silane, carbonyl, metallo-organic, peroxide, hydrazine form, ammonia (NH)3) And/or at least one of a halide. Contacting the first side 645 of the gate dielectric 638 with a precursor and a gas mixture generated by thermal energy, plasma energy, microwaves, or other energy sources, according to some embodiments, may repair the etching process used to remove the conductive materials 540-1, 540-2, …, 540-4 in FIG. 5B and form a plurality of separate, vertical access lines 640-1, 640-2, …, 640-N, 640- (N +1), …, 640- (Z-1), and 640-ZDamage on the first side 645 of the gate dielectric 638 caused by the selective isotropic etchant process.
Figure 6B illustrates a cross-sectional view of another view of the semiconductor structure taken along cut line a-a' in figure 6A showing this particular point in one example semiconductor fabrication process of an embodiment of the present disclosure. The cross-sectional view shown in FIG. 6B is away from the plurality of separate, vertical access lines 640-1, 640-2, …, 640-N, 640- (N +1), …, 640- (Z-1) and shows repeated iterations of alternating layers of dielectric material 630-1, 630-2, …, 630-N and sacrificial semiconductor material 632-1, 632-2, …, 632-N forming a vertical stack (such as 401 shown in FIG. 4) on the semiconductor substrate 400. As shown in fig. 6B, the vertical direction 611 is illustrated as a third direction (D3), such as the z-direction in an x-y-z coordinate system, similar to the third direction (D3)111 of the first, second, and third directions shown in fig. 1-3. The plane of the drawing sheet extends left and right in a first direction (D1) 609. In the example embodiment of fig. 6B, a dielectric material 641 is shown filling the vertical opening over the residual gate dielectric 638 deposition. The hard mask 637 described above covers the illustrated structure.
Figure 6C illustrates a cross-sectional view of another view of the semiconductor structure taken along cut line B-B' in figure 6A showing this particular point in one example semiconductor fabrication process of an embodiment of the present disclosure. The cross-sectional view shown in FIG. 6C is illustrated as extending in a second direction (D2)605 along an axis of repeated iterations of alternating layers of dielectric material 630-1, 630-2, …, 630-N and sacrificial semiconductor material 632-1, 632-2, …, 632-N along and on which horizontally oriented access devices and horizontally oriented storage nodes (e.g., capacitor cells) may be formed within the layers of sacrificial semiconductor material 632-1, 632-2, …, 632-N. In FIG. 6C, adjacent, opposing vertical access lines 640-3 are illustrated by dashed lines indicating a set of locations inward from the plane and orientation of the drawing sheet.
Figure 6D illustrates a cross-sectional view of another view of the semiconductor structure taken along cut line C-C in figure 6A showing this particular point in one example semiconductor fabrication process of an embodiment of the present disclosure. The cross-sectional view shown in fig. 6D is illustrated as extending outside of the region formed within the layer of sacrificial semiconductor material 632-1, 632-2, …, 632-N along the axis of repeated iterations of alternating layers of dielectric material 630-1, 630-2, …, 630-N and sacrificial semiconductor material 632-1, 632-2, …, 632-N in a second direction (D2) 605. In fig. 6C, dielectric material 641 is shown filling the space between the horizontally oriented access devices and the horizontally oriented storage nodes, which may be spaced along a first direction (D1) extending into and out of the plane of the drawing sheet for a three-dimensional array of vertically oriented memory cells. Repeated iterations of alternating layers of dielectric material 630-1, 630-2, …, 630- (N +1) and sacrificial semiconductor material 632-1, 632-2, …, 632-N are shown at the left end of the drawing sheet where horizontally oriented digit lines (such as digit lines 107-1, 107-2, …, 107-P shown in fig. 1 and below) may be integrated to make electrical contact with the second source/drain regions, as described in more detail below.
Figure 6E illustrates a cross-sectional view of another view of the semiconductor structure taken along cut line D-D' in figure 6A showing this particular point in one example semiconductor fabrication process of an embodiment of the present disclosure. The cross-sectional view shown in FIG. 6E is illustrated as extending left and right along the axis of repeated iterations of alternating layers of dielectric material 630-1, 630-2, …, 630-N and sacrificial semiconductor material 632-1, 632-2, …, 632-N, intersecting across a plurality of separate, perpendicular access lines 640-1, 640-2, …, 640-N, 640- (N +1), …, 640- (Z-1) in a first direction (D1)609 in the plane of the drawing, and intersect regions of sacrificial semiconductor material 632-1, 632-2, …, 632-N, where channel regions separated from a plurality of separate, vertical access lines 640-1, 640-2, …, 640-N, 640- (N +1), …, 640- (Z-1) by gate dielectric 638 may be formed. In fig. 6E, a first dielectric fill material 639 is shown separating the spaces between neighboring horizontally oriented access devices and horizontally oriented storage nodes, which may be formed to extend into and out of the plane of the drawing sheet (as described in more detail below) and may be spaced along the first direction (D1)609 and vertically stacked in an array extending in a third direction (D3)611 in a three-dimensional (3D) memory.
Fig. 7A illustrates an example method for forming a vertically stacked memory cell array having horizontally oriented access devices and vertically oriented access lines (such as illustrated in fig. 1-3) in another stage of a semiconductor fabrication process and in accordance with several embodiments of the present disclosure. Fig. 7A illustrates a top view of a semiconductor structure at a particular point in time in a semiconductor fabrication process, in accordance with one or more embodiments. In the example embodiment of fig. 7A, the method includes patterning the lithography masks 735, 736, and/or 737, such as 635, 636, and/or 637 in fig. 6A-6E, using a lithography process. The method in fig. 7A further illustrates forming a vertical opening 751 extending through the vertical stack and primarily in the first horizontal direction (D1)709 in the storage node region 750 (and 744 in fig. 7A and 7C) using one or more etchant processes. One or more etchant processes form the vertical openings 751 to expose a third sidewall in repeated iterations of alternating layers of dielectric material 730-1, 730-2, …, 730-N and sacrificial semiconductor material 732-1, 732-2, …, 732-N adjacent to the second region of sacrificial semiconductor material in the vertical stack shown in fig. 7B-7E. Other numbered components may be similar to those shown and discussed with respect to fig. 6.
According to an embodiment, the second region of sacrificial semiconductor material 732-1, 732-2, …, 732-N may be removed from repeated iterations of alternating layers of dielectric material 730-1, 730-2, …, 730-N and sacrificial semiconductor material 732-1, 732-2, …, 732-N in the vertical stack to form a storage node. In some embodiments, this process is performed prior to selectively removing the access device regions (e.g., transistor regions) of sacrificial semiconductor material in which the first source/drain region, channel region, and second source/drain region of the horizontally oriented access device are to be formed. In other embodiments, this process is performed after selectively removing the access device regions of sacrificial semiconductor material in which the first source/drain region, the channel region, and the second source/drain region of the horizontally oriented access device are to be formed. According to the example embodiment shown in fig. 7B-7E, the method includes selectively etching the second region of sacrificial semiconductor material 732-1, 732-2, …, 732-N to form a second horizontal opening in the vertical stack a second horizontal distance back from the vertical opening 751. In some embodiments of the present invention, the,as shown in fig. 7B-7E, the method includes forming a capacitor cell as a storage node in the second horizontal opening. By way of example and not by way of limitation, forming the capacitor includes sequentially depositing the first electrode 761 and the second electrode 756 separated by the cell dielectric 763 in the second horizontal opening using an Atomic Layer Deposition (ALD) process, chemical vapor deposition, and combinations thereof. Other suitable semiconductor fabrication techniques and/or storage node structures may be used. In some embodiments, the first and second electrodes 761, 756 can include one or more of the following: tantalum (Ta), titanium (Ti), tungsten (W), molybdenum (Mo), hafnium (Hf), ruthenium (Ru), platinum (Pt), palladium (Pd), germanium (Ge), silicon (Si), nitrogen (N)2) Oxygen (O)2) And/or carbon (C). The first electrode 761 and the second electrode 756 may be formed at a temperature ranging from about 25 ℃ to about 700 ℃, preferably ranging from about 180 ℃ to about 400 ℃.
Figure 7B illustrates a cross-sectional view of another view of the semiconductor structure taken along cut line a-a' in figure 7A showing this particular point in one example semiconductor fabrication process of an embodiment of the present disclosure. The cross-sectional view shown in FIG. 7B is away from the plurality of separate, vertical access lines 740-1, 740-2, …, 740-N, 740- (N +1), …, 740- (Z-1) and shows repeated iterations of alternating layers of dielectric material 730-1, 730-2, …, 730- (N +1) separated by horizontally oriented capacitor cells with first electrodes 761 (e.g., bottom cell contact electrodes), cell dielectrics 763, and second electrodes 756 (e.g., top common node electrodes) for forming a vertical stack on semiconductor substrate 700. As shown in fig. 7B, the vertical direction 711 is illustrated as a third direction (D3), such as the z-direction in an x-y-z coordinate system, similar to the third direction (D3)111 of the first, second, and third directions shown in fig. 1-3. The plane of the drawing sheet extends left and right in a first direction (D1) 709. In the example embodiment of fig. 7B, a first electrode 761 (e.g., a bottom electrode coupled to a source/drain region of a horizontal access device) and a second electrode 756 are illustrated as being separated by a cell dielectric material 763 that extends into and out of the plane of the drawing sheet in a second direction (D2) and along the orientation axes of the horizontal access devices and horizontal storage nodes of a vertically stacked memory cell array of a three-dimensional (3D) memory.
Figure 7C illustrates a cross-sectional view of another view of the semiconductor structure taken along cut line B-B' in figure 7A showing this particular point in one example semiconductor fabrication process of an embodiment of the present disclosure. The cross-sectional view shown in fig. 7C is illustrated as extending left and right along the plane of the drawing sheet in the second direction (D2)705 along an axis of repeated iterations of alternating layers of dielectric material 730-1, 730-2, …, 730- (N +1) and sacrificial semiconductor material 732-1, 732-2, …, 732-N along and on which horizontally oriented access devices and horizontally oriented storage nodes (e.g., capacitor cells) may be formed within the layers of sacrificial semiconductor material 732-1, 732-2, …, 732-N. In the example embodiment of fig. 7C, a horizontally oriented storage node, such as a capacitor cell, is illustrated as having been formed in such a semiconductor fabrication process, and a first electrode 761, such as a bottom electrode coupled to a source/drain region of a horizontal access device, and a second electrode 756, such as a top electrode coupled to a common electrode plane, such as a ground plane, are shown separated by a cell dielectric 763. However, embodiments are not limited to this example. In other embodiments, the first electrode 761 (e.g., a bottom electrode coupled to a source/drain region of a horizontal access device) and the second electrode 756 (e.g., a top electrode coupled to a common electrode plane (e.g., a ground plane)) separated by the cell dielectric 763 may be formed after forming the first source/drain region, the channel region, and the second source/drain region in the region of the sacrificial semiconductor material 732-1, 732-2, …, 732-N, desirably for positioning (e.g., placement formation) of a horizontally oriented access device, as described next.
In the example embodiment of fig. 7C, horizontally oriented storage nodes having a first electrode 761 (e.g., a bottom electrode coupled to a source/drain region of a horizontal access device) and a second electrode 756 (e.g., a top electrode coupled to a common electrode plane (e.g., a ground plane)) are shown formed in a second horizontal opening extending left and right in the plane of the drawing in a second direction (D2) at a second distance from the vertical opening formed in the vertical stack and along the orientation axis of the horizontal access device and the horizontal storage node of the vertically stacked memory cell array of the three-dimensional (3D) memory. In FIG. 7C, adjacent opposing vertical access lines 740-3 are illustrated by dashed lines indicating a set of locations inward from the plane and orientation of the drawing sheet.
Figure 7D illustrates a cross-sectional view of another view of the semiconductor structure taken along cut line C-C in figure 7A showing this particular point in one example semiconductor fabrication process of an embodiment of the present disclosure. The cross-sectional view shown in fig. 7D is illustrated as extending left and right in the second direction (D2)705, along the axis of repeated iterations of alternating layers of dielectric material 730-1, 730-2, …, 730-N, 730- (N +1) and sacrificial semiconductor material 732-1, 732-2, …, 732-N in the plane of the drawing, outside the region where the horizontally oriented access devices and horizontally oriented storage nodes (e.g., capacitor cells) will be formed within the layers of sacrificial semiconductor material 732-1, 732-2, …, 732-N. In fig. 7C, dielectric material 741 is shown filling the space between horizontally oriented access devices, which may be spaced along a first direction (D1) extending into and out of the plane of the drawing sheet for a three-dimensional array of vertically oriented memory cells. However, in the cross-sectional view of fig. 7D, second electrodes 756 (e.g., to the top common electrode of the capacitor cell structure) present in the spaces between horizontally adjacent devices are additionally shown. Repeated iterations of alternating layers of dielectric materials 730-1, 730-2, …, 730- (N +1) and sacrificial semiconductor materials 732-1, 732-2, …, 732-N are shown at the left end of the drawing sheet where horizontally oriented digit lines (such as digit lines 107-1, 107-2, …, 107-P shown in fig. 1 and below) may be integrated to make electrical contact with the second source/drain regions, as described in more detail below.
Figure 7E illustrates a cross-sectional view of another view of the semiconductor structure taken along cut line D-D' in figure 7A showing this particular point in one example semiconductor fabrication process of an embodiment of the present disclosure. The cross-sectional view shown in fig. 7E is illustrated as extending left and right in the plane of the drawing along the axis of repeated iterations of alternating layers of dielectric material 730-1, 730-2, …, 730- (N +1) and sacrificial semiconductor material 732-1, 732-2, …, 732-N in a first direction (D1)709, intersecting across a plurality of separate, vertical access lines 740-1, 740-2, …, 740-4, and intersecting regions of sacrificial semiconductor material 732-1, 732-2, …, 732-N (where channel regions separated from the plurality of separate, vertical access lines 740-1, 740-2, …, 740-4 by gate dielectric 738 may be formed). In fig. 7E, a first dielectric fill material 739 is shown separating the spaces between neighboring horizontally oriented access devices and horizontally oriented storage nodes, which may be formed to extend into and out of the plane of the drawing sheet (as described in more detail below) and may be spaced along a first direction (D1)709 and vertically stacked in an array extending in a third direction (D3)711 in a three-dimensional (3D) memory.
Fig. 8A illustrates an example method for forming a vertically stacked memory cell array having horizontally oriented access devices and vertically oriented access lines (such as illustrated in fig. 1-3) in another stage of a semiconductor fabrication process and in accordance with several embodiments of the present disclosure. Fig. 8A illustrates a top view of a semiconductor structure at a particular point in time in a semiconductor fabrication process, in accordance with one or more embodiments. In the example embodiment of fig. 8A, the method includes patterning the photolithographic masks 835, 836, and/or 837, etc. using a photolithographic process, as described in fig. 6 and 7. The method of fig. 8A further illustrates the formation of vertical openings 871-1 and 871-2 through the vertical stack for replacement of the channel and source/drain transistor regions in the access device region (e.g., 742 in fig. 7C and 842 in fig. 8C) using one or more etchant processes. Vertical openings 871-1 and 871-2 are illustrated as extending primarily in a first horizontal direction (D1) 709. One or more etchant processes form the vertical openings 871-1 and 871-2 to expose a third sidewall in repeated iterations of alternating layers of dielectric material 830-1, 830-2, …, 830- (N +1) and sacrificial semiconductor material (e.g., sacrificial materials 732-1, 732-2, …, 732-N described with respect to fig. 7) adjacent to the first region of sacrificial semiconductor material in the vertical stack shown in fig. 8B-8E. Other numbered components may be similar to those shown and discussed with respect to fig. 6 and 7.
According to an embodiment, the access device region (842 in fig. 8A and 8C), such as a transistor region, of the sacrificial semiconductor material 732-1, 732-2, …, 732-N may be removed from repeated iterations of alternating layers of dielectric material 830-1, 830-2, …, 830- (N +1) and sacrificial semiconductor material 732-1, 732-2, …, 732-N in the vertical stack used to form the access device, such as a transistor. In some embodiments, this process is performed prior to selectively removing the storage node regions of the sacrificial semiconductor material in which the capacitor cells are to be formed. In other embodiments, this process is performed after selectively removing the storage node regions of the sacrificial semiconductor material in which the capacitor cells are to be formed. According to an example embodiment shown in fig. 8B-8E, a method includes selectively etching access device regions of sacrificial semiconductor material 732-1, 732-2, …, 732-N to form a first horizontal opening in the vertical stack a first horizontal distance back from the vertical openings 871-1 and 871-2. In some embodiments, as shown in fig. 8B-8E, the method includes forming a transistor having a first source/drain region, a channel region, and a second source/drain region in the first horizontal opening as an access device. By way of example and not by way of limitation, forming the first source/drain region, the channel region, and the second source/drain region includes sequentially depositing the first source/drain region, the channel region, and the second source/drain region in the first horizontal opening using an Atomic Layer Deposition (ALD) process. Other suitable semiconductor fabrication techniques and/or storage node structures may be used.
Figure 8B illustrates a cross-sectional view of another view of the semiconductor structure taken along cut line a-a' in figure 8A showing this particular point in one example semiconductor fabrication process of an embodiment of the present disclosure. The cross-sectional view shown in FIG. 8B is away from the plurality of separate, vertical access lines 840-1, 840-2, …, 840-N, 840- (N +1), …, 840- (Z-1) and shows repeated iterations of alternating layers of dielectric material 830-1, 830-2, …, 830- (N +1) separated by capacitor cells having a first electrode 861 (e.g., a bottom cell contact electrode), a cell dielectric 863, and a second electrode 856 (e.g., a top common node electrode) forming a vertical stack on the semiconductor substrate 800. As shown in fig. 8B, the vertical direction 811 is illustrated as a third direction (D3), such as the z-direction in an x-y-z coordinate system, similar to the third direction (D3)111 of the first, second, and third directions shown in fig. 1-3. The plane of the drawing sheet extends left and right in a first direction (D1) 809. In the example embodiment of fig. 8B, a first electrode 861 (e.g., a bottom electrode coupled to a source/drain region of a horizontal access device) and a second electrode 856 are illustrated as being separated by cell dielectric material 863 extending into and out of the plane of the drawing sheet in a second direction (D2) and along the orientation axis of the horizontal access devices and horizontal storage nodes of a vertically stacked memory cell array of a three-dimensional (3D) memory.
Figure 8C illustrates a cross-sectional view of another view of the semiconductor structure taken along cut line B-B' in figure 8A showing this particular point in one example semiconductor fabrication process of an embodiment of the present disclosure. The cross-sectional view shown in fig. 8C is illustrated as extending left and right along the axis of repeated iterations of alternating layers of dielectric material 830-1, 830-2, …, 830- (N +1) along the plane of the drawing sheet in the second direction (D2) 805. However, it is now shown that sacrificial semiconductor material has been removed in the access device regions 842 of the vertically stacked alternating layers to form horizontal openings 833-1, 833-2, …, 833-N, wherein horizontally oriented access devices having first source/drain regions, channel regions, and second source/drain regions can be formed between the vertically alternating layers of dielectric material 830-1, 830-2, …, 830- (N + 1). In the example embodiment of fig. 8C, a horizontally oriented storage node, such as a capacitor cell, is illustrated as having been formed in the memory node region 844 in this semiconductor fabrication process, and a first electrode 861, such as a bottom electrode coupled to a source/drain region of a horizontal access device, and a second electrode 856, such as a top electrode coupled to a common electrode plane, such as a ground plane, are shown separated by a cell dielectric 863. However, embodiments are not limited to this example. In other embodiments, a first electrode 861 (e.g., a bottom electrode coupled to a source/drain region of a horizontal access device) and a second electrode 856 (e.g., a top electrode coupled to a common electrode plane (e.g., a ground plane)) separated by a cell dielectric 863 may be formed after forming first, channel, and second source/drain regions in the access device region 842 in which the sacrificial semiconductor material 732-1, 732-2, …, 732-N has been removed.
In the example embodiment of fig. 8C, the horizontal openings 833-1, 833-2, …, 833-N, in which the access device having the first source/drain region, the channel region, and the second source/drain region is to be formed, are shown extending left and right in the plane of the drawing in the second direction 805(D2), at a distance from the vertical openings 871-1 and 871-2 formed in the vertical stack and along the orientation axes of the horizontal access device and the horizontal storage node of the vertically stacked memory cell array of the three-dimensional (3D) memory. In fig. 8C, adjacent opposing vertical access lines 840-3 are illustrated by dashed lines indicating a set of locations inward from the plane and orientation of the drawing sheet, and the gate dielectric 838 is visible.
According to an embodiment, the removal of sacrificial semiconductor material in the access device regions 842 of the vertically stacked alternating layers used to form the horizontal openings 833-1, 833-2, …, 833-N (where horizontally oriented access devices having first source/drain regions, channel regions, and second source/drain regions may be formed between vertically alternating layers of dielectric material 830-1, 830-2, …, 830- (N + 1)) presents another point in the semiconductor fabrication process that may damage the gate dielectric 838 on the second side 846 (region) of the horizontal openings 833-1, 833-2, …, 833-N. For example, the second side 846 of the gate dielectric 838 may have reduced insulating properties due to potential damage caused by the selective etch process used to remove the sacrificial semiconductor materials 732-1, 732-2, …, 732-N to form the horizontal openings 833-1, 833-2, 833-N. Similar to potential damage to the first side (e.g., side 645) of the gate dielectric 838 shown in fig. 6A, the second side 846 of the gate dielectric 838 within the horizontal openings 833-1, 833-2, …, 833-N may be repaired to improve dielectric properties and performance on the second side 846 of the gate dielectric 838. According to an embodiment, the process of repairing potential damage to the second side 846 of the gate dielectric may be performed prior to potential repair and/or processing of the first electrode 861 (e.g., the bottom electrode) and prior to forming the first source/drain region, the channel region, and the second source/drain region, as described below with respect to fig. 9C.
For example, prior to forming the first source/drain region, the channel region, and the second source/drain region, the second side 846 of the gate dielectric 838 may be treated to repair and/or improve the dielectric quality and/or surface bond termination on the second side 846 of the gate dielectric 838. In one example embodiment, the second side 846 of the gate dielectric 838 may be repaired using Atomic Layer Deposition (ALD). However, embodiments are not limited to this example. In one example embodiment, the repair and/or improvement of the second side 846 of the gate dielectric 838 may consist of: remote ionization of a gas or precursor, oxygen or oxygen-containing species, or a mixture of gases in a ratio that preferentially repairs the gate dielectric 838 while minimizing oxidation of the materials forming the first electrode 861 (e.g., the metallic materials tantalum (Ta), titanium (Ti), tungsten (W), molybdenum (Mo), hafnium (Hf), ruthenium (Ru), platinum (Pt), palladium (Pd), etc.). Combinations that provide mixtures of molecular oxygen and ionized species may be most efficiently formed at temperatures ranging from 150 ℃ to 600 ℃. As with the processing of the first side 645 in fig. 6A, a short pulse of metal atoms, such as hafnium (Hf), aluminum (Al), scandium (Sc), lanthanum (La), zirconium (Zr), etc., in precursor form of the gate dielectric 638 may be included to return the second side 846 of the gate dielectric to a desired stoichiometry and/or surface bond termination. Such processing may be performed ex situ with the formation of the first source/drain regions, channel regions, and second source/drain regions described with respect to fig. 9A-9E, an in situ frame, or an in situ chamber.
In some embodiments, Atomic Layer Deposition (ALD), post-deposition anneal, or doping may be used to flow the precursor to contact the second side 846 of the gate dielectric 838 to initiate a repair process of the second side 846. The precursor may comprise a compound such as silane, hydroxy, ethyl, methyl or oxysilane. However, embodiments are not limited to these examples. Subsequently, the second side 846 of the dielectric 838 can be exposed to thermal energy, plasma energy, microwaves, or other energy sources to generate hydrogen gas (H)2) Oxygen (O)2) Nitrogen (N)2) Helium (He), silane, carbonyl, metallo-organic, peroxide, hydrazine form, ammonia (NH)3) And/or at least one of a halide. Accordingly, the processes described herein may repair and/or improve the dielectric properties and/or quality of the second side 646 of the gate dielectric 838 within the process flow for forming a three-node access device for a vertical three-dimensional (3D) memory.
Figure 8D illustrates a cross-sectional view of another view of the semiconductor structure taken along cut line C-C in figure 8A showing this particular point in one example semiconductor fabrication process of an embodiment of the present disclosure. The cross-sectional view shown in fig. 8D is illustrated as extending left and right in a second direction (D2)805 outside of the region where horizontally oriented access devices and horizontally oriented storage nodes (e.g., capacitor cells) are to be formed along the axis of repeated iterations of alternating layers of dielectric materials 830-1, 830-2, …, 830-N, 830- (N +1) and horizontal openings 833-1, 833-2, …, 833-N in the plane of the drawing. In fig. 8D, dielectric material 841 is shown filling the space between horizontally oriented access devices, which may be spaced along a first direction (D1) extending into and out of the plane of the drawing sheet for a three-dimensional array of vertically oriented memory cells. However, in the cross-sectional view of fig. 8D, a second electrode 856 is additionally shown present in the space between horizontally adjacent devices (e.g., to the top common electrode of the capacitor cell structure). Repeated iterations of alternating layers of dielectric materials 830-1, 830-2, …, 830- (N +1) and horizontal openings 833-1, 833-2, …, 833-N are shown at the left end of the drawing where horizontally oriented digit lines, such as digit lines 107-1, 107-2, …, 107-P shown in fig. 1 and below, may be integrated to form electrical contacts to the second source/drain regions of the formed horizontal access device.
Figure 8E illustrates a cross-sectional view of another view of the semiconductor structure taken along cut line D-D' in figure 8A showing this particular point in one example semiconductor fabrication process of an embodiment of the present disclosure. The cross-sectional view shown in FIG. 8E is illustrated as extending left and right along the axis of repeated iterations of alternating layers of dielectric material 830-1, 830-2, …, 830- (N +1) and horizontal openings 833-1, 833-2, …, 833-N in a first direction (D1)809 in the plane of the drawing, where channel regions separated from a plurality of separate, vertical access lines 840-1, 840-2, …, 840-4 by gate dielectric 838 will be formed. In fig. 8E, a first dielectric fill material 839 is shown separating the space between adjacent horizontally oriented access devices and horizontally oriented storage nodes, which may be formed to extend into and out of the plane of the drawing (as described in more detail below) and may be spaced along the first direction (D1)809 and vertically stacked in an array extending in a third direction (D3)811 in a three-dimensional (3D) memory.
Fig. 9A illustrates an example method for forming a vertically stacked memory cell array having horizontally oriented access devices and vertically oriented access lines (such as illustrated in fig. 1-3) in another stage of a semiconductor fabrication process and in accordance with several embodiments of the present disclosure. Fig. 9A illustrates a top view of a semiconductor structure at a particular point in time in a semiconductor fabrication process, in accordance with one or more embodiments. In the example embodiment of FIG. 9A, vertical openings 971-1 and 971-2 remain present from FIGS. 8A-8E. However, in FIGS. 9A-9E, horizontal access devices 998-1, 998-2, …, 998-N having first, channel, and second source/drain regions, shown in FIG. 9C as 998-1A, 998-1B, and 998-1C, respectively, have been formed in the horizontal openings 833-1, 833-2, …, 833-N shown in FIGS. 8C and 8D. Horizontal access devices 998-1, 998-2, 998-N extending in the second direction 905(D2) are formed in a vertically stacked horizontal access device region 942. Additionally, horizontal digit lines 999-1, 999-2, 999-N have been formed and make integral contact with second source/drain regions (e.g., 998-1C) as shown in FIGS. 9C and 9D. Other numbered components may be similar to the components shown and discussed with respect to fig. 6, 7, and 8.
In an access device region 942 (e.g., a transistor region), the sacrificial semiconductor material 732-1, 732-2, …, 732-N in fig. 8A-8E has been removed to leave repeated iterations of alternating layers of dielectric material 830-1, 830-2, …, 830- (N +1) and horizontal openings 833-1, 833-2, …, 833-N used to form access devices (e.g., transistors) in the vertical stack of fig. 8, according to an embodiment. In some embodiments, this process is performed prior to selectively removing the storage node region 944 of sacrificial semiconductor material in which the capacitor cells are to be formed. In other embodiments, this process is performed after selectively removing the storage node region 944 of sacrificial semiconductor material in which the capacitor cells are to be formed. According to an example embodiment shown in fig. 9B-9E, a method includes selectively depositing a first source/drain region 938-1A, a channel region 938-1B, and a second source/drain region 938-1C in each of the horizontal openings 833-1, 833-2, …, 833-N in fig. 8A-8E using an Atomic Layer Deposition (ALD) process or other suitable deposition technique. By way of example and not by way of limitation, forming the first source/drain region, the channel region, and the second source/drain region includes sequentially depositing the first source/drain region, the channel region, and the second source/drain region in the first horizontal opening using an Atomic Layer Deposition (ALD) process in accordance with the processes and techniques described herein. Other suitable semiconductor fabrication techniques and/or storage node structures may be used.
Figure 9B illustrates a cross-sectional view of another view of the semiconductor structure taken along cut line a-a' in figure 9A showing this particular point in one example semiconductor fabrication process of an embodiment of the present disclosure. The cross-sectional view shown in FIG. 9B is remote from a plurality of separate, vertical access lines 940-1, 940-2, …, 940-N, 940- (N +1), …, 940- (Z-1) and shows repeated iterations of alternating layers of dielectric material 930-1, 930-2, …, 930- (N +1) separated by capacitor cells with a first electrode 961 (e.g., a bottom cell contact electrode), a cell dielectric 963, and a second electrode 956 (e.g., a top common node electrode) for forming a vertical stack on a semiconductor substrate 900. As shown in fig. 9B, the vertical direction 911 is illustrated as a third direction (D3), such as the z-direction in an x-y-z coordinate system, similar to the third direction (D3)111 of the first, second, and third directions shown in fig. 1-3. The plane of the drawing sheet extends left and right in a first direction (D1) 909. In the example embodiment of fig. 9B, a first electrode 961 (e.g., a bottom electrode coupled to a source/drain region of a horizontal access device) and a second electrode 956 are illustrated as being separated by cell dielectric material 963 extending into and out of the plane of the drawing sheet in a second direction (D2) and along the orientation axis of the horizontal access devices and horizontal storage nodes of a vertically stacked memory cell array of a three-dimensional (3D) memory.
Figure 9C illustrates a cross-sectional view of another view of the semiconductor structure taken along cut line B-B' in figure 9A showing this particular point in one example semiconductor fabrication process of an embodiment of the present disclosure. The cross-sectional view shown in fig. 9C is illustrated as extending left and right along the axis of repeated iterations of alternating layers of dielectric material 930-1, 930-2, …, 930- (N +1) along the plane of the drawing sheet in the second direction (D2) 905. However, it is now shown that first, channel, and second source/drain region materials 998-1, 998-2, 998-N have been deposited in horizontal openings 833-1, 833-2, …, 833-N extending in the second direction 905(D2) in FIGS. 8A-8E. As one example, the first source/drain region 998-1, the channel regions 998-1B and 998-1C are illustrated differently. Furthermore, the horizontal digit lines 999-1, 999-2, …, 999-N are integrated to make contact with a second source/drain region (e.g., 998-1C) that extends in a first direction (D1) (e.g., extends into and out of the plane of the drawing in direction (D3)911 perpendicular to the dielectric materials 930-1, 930-2, …, 930- (N +1) in alternating layers).
Thus, three node horizontal access devices 938-1, 938-2, …, 938-N have been formed and integrated into vertical access lines 940-1, 940-2, …, 940- (Z +1) and into digit lines 999-1, 999-2, …, 999-N without body contact. Advantages of the structures and processes described herein may include a lower off current (Ioff) for the access device than a silicon-based (Si-based) access device. The channel region, such as 938-1B, may be devoid of minority carriers for the access device and thus may not require control of the body potential to the body region of the access device and/or reduction of gate/drain induced leakage (GIDL) of the access device. In some embodiments, channel and/or source/drain region replacement manufacturing steps may be performed after the capacitor cell formation process, reducing the thermal budget. Digit line integration may be easier to implement in the manufacturing process because body contact to the body region of the access device is not used. In addition, the embodiments described herein may enable better lateral scaling paths than with doped polysilicon based channel regions due to smaller channel lengths and lower source/drain semiconductor fabrication process formation overhead.
In one example, a first source/drain region (e.g., 998-1C) of a horizontal access device 998-1, 998-2, …, 998-N, integration of the Channel region (e.g., 998-1B) and the second source/drain region (e.g., 998-1A) with the horizontal digit lines 999-1, 999-2, …, 999-N can be performed in accordance with the processes and techniques described in co-pending U.S. patent application No. 16/986,466, having at least one co-inventor herein and filed on 8/6/2020 and incorporated herein by reference, entitled Channel Integration in a Three-Node Access Device for Vertical Three-Dimensional (3D) Memory, attorney docket No. 1013.0560001. Other suitable semiconductor fabrication techniques may be used.
In the example embodiment of fig. 9C, horizontal access devices 998-1, 998-2, … 998-N having first, channel, and second source/drain regions are shown extending left and right in the plane of the drawing in a second direction 905(D2) at a distance from vertical openings 971-1 and 971-2 formed in the vertical stack and along the directional axes of the horizontal access devices and horizontal storage nodes of a vertically stacked array of memory cells of a three-dimensional (3D) memory. As shown in fig. 10, since dielectric material may be deposited to fill the vertical openings 971-1 and 971-3. In FIG. 9C, adjacent opposing vertical access lines 940-3 are illustrated by dashed lines indicating a set of locations inward from the plane and orientation of the drawing sheet.
As noted above, in some embodiments, the first electrode 961 to a storage node in storage node region 944 may be formed prior to forming the first source/drain region, the channel region, and the second source drain region. Thus, the surface 947 of the first electrode 961 may be damaged by removing the sacrificial semiconductor material (e.g., 732-1, 732-2, …, 732-N in FIG. 7C) (as described in FIGS. 8A-8E) to form the horizontal openings 833-1, 833-2, …, 833-N. The surface 947 of the first electrode 961 inside the horizontal openings 833-1, 833-2, …, 833-N depicted in fig. 8A through 8E may serve as an electrical contact to a first source/drain region (e.g., 998-1C).
Thus, according to embodiments, prior to depositing the first source/drain region (e.g., 998-1C), the channel region (e.g., 998-1B), and the second source/drain region (e.g., 998-1A) of the horizontal access devices 998-1, 998-2, …, 998-N, the surface 947 of the first electrode 961 (e.g., the bottom electrode) may be treated to repair and/or improve its conductive properties and performance of electrical contact thereto to the first source/drain region (e.g., 998-1C). As noted, the first electrode 961 may be damaged during the formation of the horizontal openings 833-1, 833-2, …, 833-N in fig. 8A through 8E. As described herein, the surface 947 of the first electrode 961 may be subjected to a process that can repair damage caused by forming the horizontal openings 833-1, 833-2, …, 833-N in fig. 8A through 8E. For example, the first electrode 961 may be repaired by a process for restoring the conductive quality of the surface 947 of the first electrode 961.
In one embodiment, Atomic Layer Deposition (ALD), post-deposition annealing, or doping can be used to initiate repair of the first electrode 961. In this process, the precursor can flow to contact the first electrode 961. The precursor can be used before the gases that make up the surface of the first electrode 961 are mixed for subsequent gases that will contact the first electrode 961. In one example embodiment, the precursor may comprise a compound, such as silane, hydroxyl, ethyl, methyl, or oxysilane. The first electrode 961 may then be exposed to hydrogen (H) gas generated by thermal energy, plasma energy, microwaves, or other energy source2) Oxygen (O)2) Nitrogen (N)2) Helium (He), silane, carbonyl, metallo-organic, peroxide, hydrazine form, ammonia (NH)3) And/or at least one of a halide. Thus, prior to depositing the first source/drain (e.g., 998-1C), channel region (e.g., 998-1B), and second source/drain region (e.g., 998-1A) of the horizontal access devices 998-1, 998-2, …, 998-N, the surface 947 of the first electrode 961 will first be reduced to remove metal oxide therefrom. In some embodiments, this reduction may be accomplished using ionized hydrogen, ammonia, hydrazine (and/or derivatives thereof) forms and mixtures with molecular forms thereof.
As described herein, the interface and free surface bond termination can be controlled using a combination of oxidation, reduction, or passivation conditions. The intrinsic and the inhibition methods can be used to achieve distinct conditions on one surface but not the other. Silanes, thiols, carbonyls, siloxanes and others with head groups that terminate attached to one surface bond but not to another surface bond are used to affect the inhibition process. Intrinsic methods are methods in which the precursor used to deposit the material already has the property of a particular bond termination attached to a particular surface. Thus, repairing the conductive quality of the surface 947 of the first electrode 961 with the processes described herein may repair and/or improve the conductive properties of the electrical contact (e.g., interface) between the first electrode 961 and the first source/drain region (e.g., 998-1C), the channel region (e.g., 998-1B), and the second source/drain region (e.g., 998-1A) of the horizontal access device 998-1, 998-2, …, 998-N prior to depositing the first source/drain region (e.g., 998-1C), the channel region, and the second source/drain region (e.g., 998-1A).
Figure 9D illustrates a cross-sectional view of another view of the semiconductor structure taken along cut line C-C in figure 9A showing this particular point in one example semiconductor fabrication process of an embodiment of the present disclosure. The cross-sectional view shown in fig. 9D is illustrated as extending left and right along the axis of repeated iterations of alternating layers of dielectric materials 930-1, 930-2, …, 930-N, 930- (N +1) and horizontal digit lines 999-1, 999-2, …, 999-N in the plane of the drawing in a second direction (D2)905, extending in and out of the plane of the drawing outside of the region in which horizontally oriented access devices 938-1, 938-2, …, 938-N and horizontally oriented storage nodes (e.g., capacitor cells) in access device region 942 and storage node region 944 are formed in the first direction (D1). In FIG. 9D, dielectric material 941 is shown filling the space between horizontally oriented access devices, which may be spaced along a first direction (D1) extending into and out of the plane of the drawing sheet for a three-dimensional array of vertically oriented memory cells. However, in the cross-sectional view of fig. 9D, a second electrode 956 is additionally shown that is present in the space between horizontally adjacent devices (e.g., to the top common electrode of the capacitor cell structure). Repeated iterations of alternating layers of dielectric material 930-1, 930-2, …, 930- (N +1) and horizontal digit lines 999-1, 999-2, …, 999-N (such as digit lines 107-1, 107-2, …, 107-P shown in fig. 1 and below) integrated to form the horizontal access device formed in electrical contact with a second source/drain region (such as 938-1C) are shown at the left end of the drawing.
Figure 9E illustrates a cross-sectional view of another view of the semiconductor structure taken along cut line D-D' in figure 9A showing this particular point in one example semiconductor fabrication process of an embodiment of the present disclosure. The cross-sectional view shown in FIG. 9E is illustrated as extending left and right in the plane of the drawing along the axis of repeated iterations of alternating layers of channel regions of dielectric materials 930-1, 930-2, …, 930- (N +1) and horizontal access devices 998-1, 998-2, …, 998-N separated by gate dielectric 938 from a plurality of separate, vertical access lines 940-1, 940-2, …, 940-4, in a first direction (D1) 909. In fig. 9E, a first dielectric fill material 939 is shown separating spaces between adjacent horizontally oriented access devices and horizontally oriented storage nodes, which may be formed to extend into and out of the plane of the drawing sheet (as described in more detail below) and may be spaced along a first direction (D1)909 and vertically stacked in an array extending in a third direction (D3)911 in a three-dimensional (3D) memory.
Fig. 10A-10D illustrate an example method for source/drain integration in a three-node horizontally oriented access device at a particular point in time in a semiconductor fabrication process, according to several embodiments of the present disclosure. Fig. 10A and 10C are cross-sectional side views of source/drain integration in horizontal access device region 1042 after a storage node (e.g., a capacitor cell) is formed in storage node region 1044 that extends left and right along the plane of the drawing (e.g., along cut line B-B' in fig. 8A) in second direction 1005 (D2). Fig. 10B and 10D are end views of source/drain integration in the formation of a three-node horizontally oriented access device at a particular point in time in the semiconductor fabrication process.
As shown in fig. 10A-10D, storage nodes (e.g., capacitor cells) have been formed in a storage node region 1044. In this example, the storage node is a horizontally oriented storage node extending in a second direction (D2)1005 adjacent to a horizontal access device region 1042 of a vertical three-dimensional (3D) memory having vertically oriented access lines. A storage node, such as a capacitor, includes a first electrode 1061, such as a bottom electrode, and a second electrode 1065, such as a top electrode and/or a common node electrode, separated by cell dielectric material 1063. As described above, structures may be formed in repeating alternating layers of dielectric materials 1030-1 and 1030-2 and sacrificial material (not shown) that has been removed to form respective storage node regions 1044 and which is now source/drain integrated in the horizontal access device region 1042. As also described above, a first etchant process may be used to form a first vertical opening (e.g., 871 in fig. 8A) to expose sidewalls in the vertical stack adjacent to the first portion of the sacrificial material and the first portion of the sacrificial material removed by the selective etch process to form a horizontal opening (e.g., 833 in fig. 8C) adjacent to the cell side region 1044 in the access device region 1042.
The example in fig. 10A and 10B illustrates the formation of a multi-layer source/drain region 1071-1 by depositing a first conductive material 1071-1 in a first horizontal opening to make electrical contact with a storage node at the distal end of the first horizontal opening 833 in fig. 8C a first horizontal distance (D1 opening) back from the first vertical opening 871 in fig. 8A. In one example, depositing the first conductive material 1071-1 includes depositing a metal material (e.g., layer) that does not oxidize in contact with the oxide semiconductor material. In the examples described herein, a storage node (e.g., a capacitor) has been formed. In this example, the first electrode 1061 can provide an etch stop during removal of the sacrificial material (e.g., 732 in fig. 7C) to form the first horizontal opening 833 in fig. 8C. However, in other embodiments, the storage node (e.g., capacitor) may be formed after formation of a three-node horizontal storage device including source/drain integration as described herein. In this example embodiment, the first conductive material 1071-1 may be chosen to act as an etch stop for sacrificial material (e.g., 732 in fig. 7C) removal and provide an electrically ohmic contact to the first electrode 1061 of the storage node during the formation of the second horizontal opening 833 in fig. 8C in the storage node region 1044 for storage node formation.
In one example embodiment, depositing the first conductive metal material 1071-1 includes depositing a ruthenium (Ru) -containing material. In one example, depositing the first conductive metal material 1071-1 includes depositing a molybdenum (Mo) containing material. In one example, depositing the first conductive metal material 1071-1 includes depositing a nickel (Ni) -containing material. In one example, depositing the first conductive metal material 1071-1 includes depositing a titanium (Ti) -containing material. In one example, depositing the first conductive metal material 1071-1 includes depositing a copper (Cu) -containing material. In one example, depositing the first conductive metal material 1071-1 includes depositing a tin (Sn) -containing material. However, embodiments are not limited to these examples.
In another example, depositing the first conductive material 1071-1 includes depositing a metal material (e.g., layer) that forms a conductive oxide in contact with the oxide semiconductor material. For example, in one embodiment, depositing the first conductive material 1071-1 includes depositing a highly doped degenerate semiconductor. In one example, depositing the first conductive material 1071-1 includes depositingIndium oxide (In)2O3) The composition serves as a first conductive material 1071-1. In one example, depositing the first conductive material 1071-1 includes depositing indium tin oxide (In)2-xSnxO3) The composition serves as a first conductive material 1071-1. However, embodiments are not limited to these examples.
The conductive material 1071-1 can be deposited such that the conductive material 1071-1 fills the entire opening and is deposited on the area beside the opening, such as in the first vertical opening 871 in fig. 8A. Figure 10B illustrates an end view of the three-node horizontal access device formation in this particular stage of the semiconductor fabrication process.
In one example, depositing the first conductive material 1071-1 includes filling the first horizontal opening to the distal end using an Atomic Layer Deposition (ALD) process to form an electrical ohmic contact with the first electrode 1061. As shown in fig. 10A and 10B, the ALD deposition process of the first conductive contact material 1071-1 may also fill the first vertical opening.
As shown in fig. 10C and 10D, the method includes removing a portion of the first conductive contact material 1071-1 to recess the first conductive contact material 1071-1 to remain in electrical ohmic contact with the first electrode 1061 only at the distal ends of the horizontal openings. In one example, the removal process may be performed using an Atomic Layer Etch (ALE) process. However, embodiments are not limited to this example. In one example, the first conductive material 1071-1 may be recessed back in the horizontal opening 833 in fig. 8C to have a thickness of about ten (10) nanometers (nm) and form an electrical ohmic contact with the first electrode 1061. However, embodiments are not limited to this example, and other thicknesses may be suitably employed according to particular design rules and/or sizing of the three-node horizontal access device. Figure 10D illustrates an end view of the three-node horizontal access device formation in this particular stage of the semiconductor fabrication process.
Fig. 11A-11D illustrate an example method for source/drain integration in a three-node horizontally oriented access device at a particular point in time in a semiconductor fabrication process, according to several embodiments of the present disclosure. Fig. 11A and 11C are cross-sectional side views of source/drain integration in horizontal access device region 1042 after storage nodes (e.g., capacitor cells) are formed in storage node region 1044 that extend left and right along the plane of the drawing (e.g., along cut line B-B' in fig. 8A) in second direction 1005 (D2). 11B and 11D are end views of source/drain integration in the formation of a three-node horizontally oriented access device at a particular point in time in the semiconductor fabrication process. According to an embodiment, the point in time in the semiconductor manufacturing process illustrated in fig. 11A-11D may be subsequent to the structure and point in time illustrated in fig. 10A-10D. However, the embodiments are not limited thereto.
As shown in fig. 11A and 11B, the method can include depositing a second conductive material 1173-1 in electrical contact with a first conductive material 1171-1 in electrical ohmic contact with a first electrode 1161 of a horizontally oriented storage node (e.g., a capacitor cell). In one example, depositing the second conductive material 1173-1 includes depositing a degenerate semiconductor material. As used herein, degenerate semiconductor material is intended to mean a semiconductor material (e.g., polysilicon) that contains a high degree of doping and significant interactions between dopants (e.g., phosphorus (P), boron (B), etc.). In contrast, non-degenerate semiconductors contain moderate doping, where the dopant atoms are well separated from each other in the semiconductor host lattice and have negligible interactions.
In one example, depositing the second conductive material 1173-1 includes depositing the second conductive material having an electronic bandgap lower than that of the channel material. In one embodiment, depositing the second conductive material 1173-1 includes depositing the second conductive material with a conduction band offset intermediate to the conduction band offset of the first conductive material 1171-1 and the conduction band offset of the channel material (e.g., offset from the fermi (fermi) level of the implant electrode (the first electrode 1161 of the capacitor cell)). Further, in some embodiments, the conductive material 1173-1 can be a metallic material. In some embodiments, the conductive material 1173-1 can include indium oxide (In)2O3) Or indium tin oxide (In)2-xSnxO3) At least one of (a). Conductive material 1173-1 may have an electronic band gap that is lower than an electronic band gap of a subsequent conductive material (such as channel material 1398 shown with respect to fig. 13) and a conduction band offset that is lower than a conduction band offset of the subsequent conductive material. In addition, the conductive material 1173-1 can have a lower conductivity than the conductive materialThe electronic band gap of the electrical channel region.
For example, in one example, depositing the second conductive material 1173-1 comprises depositing a ruthenium (Ru) -containing material. In one example, depositing the second conductive material 1173-1 includes depositing a molybdenum (Mo) containing material. In one example, depositing the second conductive material 1173-1 includes depositing a nickel (Ni) -containing material. In one example, depositing the second conductive material 1173-1 includes depositing a titanium (Ti) -containing material. In one example, depositing the second conductive material 1173-1 includes depositing a copper (Cu) -containing material. In one example, depositing the second conductive material 1173-1 includes depositing a tin (Sn) -containing material.
In another example, depositing the second conductive material 1173-1 includes depositing a metal material (e.g., a layer) that forms a conductive oxide in contact with the oxide semiconductor material. For example, in one embodiment, depositing the second conductive material 1173-1 comprises depositing a highly doped degenerate semiconductor. In one example, depositing the second conductive material 1173-1 includes depositing indium oxide (In)2O3) The composition serves as the second conductive material 1173-1. In one example, depositing the second conductive material 1173-1 includes depositing indium tin oxide (In)2-xSnxO3) The composition serves as the second conductive material 1173-1. However, embodiments are not limited to these examples.
The second conductive material 1173-1 can be deposited such that the second conductive material 1173-1 fills the entire opening and is deposited on areas beside the opening, such as in the first vertical opening 871 in fig. 8A. Figure 11B illustrates an end view of the three-node horizontal access device formation in this particular stage of the semiconductor fabrication process.
In one example, depositing the second conductive material 1173-1 includes filling the first horizontal opening using an Atomic Layer Deposition (ALD) process. As shown in fig. 11A and 11B, the ALD deposition process of the first conductive contact material 1173-1 may also fill the first vertical opening.
As shown in fig. 11C and 11D, the method includes removing a portion of the second conductive contact material 1173-1 to recess the second conductive contact material 1173-1. In one example, the removal process may be performed using an Atomic Layer Etch (ALE) process. However, embodiments are not limited to this example. In one example, the second conductive material 1173-1 may be recessed back in the horizontal opening 833 of fig. 8C and may have a thickness of about ten (10) nanometers (nm). However, embodiments are not limited to this example, and other thicknesses may be suitably employed according to particular design rules and/or sizing of the three-node horizontal access device. Figure 11D illustrates an end view of the three-node horizontal access device formation in this particular stage of the semiconductor fabrication process.
Fig. 12A-12D illustrate an example method for source/drain integration in a three-node horizontally oriented access device at a particular point in time in a semiconductor fabrication process, according to several embodiments of the present disclosure. Fig. 12A and 12C are cross-sectional side views of source/drain integration in the horizontal access device region 1242 after storage nodes (e.g., capacitor cells) are formed in the storage node region 1244 that extends left and right along the plane of the drawing (e.g., along cut line B-B' in fig. 8A) in the second direction 1205 (D2). Fig. 12B and 12D are end views of source/drain integration in the formation of a three-node horizontally oriented access device at a particular point in time in the semiconductor fabrication process. According to an embodiment, the point in time in the semiconductor fabrication process illustrated in fig. 12A-12D may be subsequent to the structure and point in time illustrated in fig. 11A-11D. However, the embodiments are not limited thereto.
As shown in fig. 12A and 12B, the method may include depositing an nth (e.g., third) conductive material 1275-1 in electrical contact with an nth (e.g., second) conductive material 1273-1, the second conductive material 1273-1 in electrical contact with the first conductive material 1271-1. In one example, depositing the third conductive material 1275-1 includes depositing a degenerate semiconductor material. As used herein, degenerate semiconductor material is intended to mean a semiconductor material (e.g., polysilicon) that contains a high degree of doping and significant interactions between dopants (e.g., phosphorus (P), boron (B), etc.). In contrast, non-degenerate semiconductors contain moderate doping, where the dopant atoms are well separated from each other in the semiconductor host lattice and have negligible interactions.
In one example, depositing the third conductive material 1275-1 includes depositing a third layer having a previous (e.g., second) conductive material 1171-1 and a channel materialThe electronic bandgap of (a) a third conductive material of an electronic bandgap intermediate the electronic bandgaps of (b). In one embodiment, depositing the third conductive material 1275-1 includes depositing the third conductive material 1275-1 having a conduction band offset (e.g., a fermi level offset from the implant electrode (the first electrode 1261 of the capacitor cell)) intermediate the conduction band offset of the second conductive material 1273-1 and the conduction band offset of the channel material. Further, in some embodiments, conductive material 1275-1 may be a metallic material. In some embodiments, the conductive material 1275-1 may comprise indium oxide (In)2O3) Or indium tin oxide (In)2-xSnxO3) At least one of (a). Conductive material 1275-1 may have an electronic bandgap that is lower than the electronic bandgap of a subsequent conductive material (e.g., channel material 1398 shown with respect to fig. 13) and a conduction band offset that is lower than the conduction band offset of the subsequent conductive material.
For example, in one example, depositing the third conductive material 1275-1 comprises depositing a ruthenium (Ru) -containing material. In one example, depositing the third conductive material 1275-1 includes depositing a molybdenum (Mo) containing material. In one example, depositing the third conductive material 1275-1 includes depositing a nickel (Ni) -containing material. In one example, depositing the third conductive material 1275-1 includes depositing a titanium (Ti) -containing material. In one example, depositing the third conductive material 1275-1 includes depositing a copper (Cu) -containing material. In one example, depositing the third conductive material 1275-1 includes depositing a tin (Sn) -containing material.
In another example, depositing the third conductive material 1275-1 includes depositing a metal material (e.g., layer) that forms a conductive oxide in contact with the oxide semiconductor material. For example, in one embodiment, depositing the third conductive material 1275-1 comprises depositing a highly doped degenerate semiconductor. In one example, depositing the third conductive material 1275-1 includes depositing indium oxide (In)2O3) The composition acts as the third conductive material 1275-1. In one example, depositing the third conductive material 1275-1 includes depositing indium tin oxide (In)2-xSnxO3) The composition acts as the third conductive material 1275-1. However, embodiments are not limited to these examples.
The third conductive material 1275-1 to the multi-layer source/drain conductive contacts may be deposited such that the third conductive material 1275-1 fills the entire opening and is deposited on the area beside the opening, such as in the first vertical opening 871 in fig. 8A. Figure 12B illustrates an end view of the three-node horizontal access device formation in this particular stage of the semiconductor fabrication process.
In one example, depositing the third conductive material 1275-1 includes filling the first horizontal opening in electrical contact with the second conductive material 1273-1 using an ALD process. As shown in fig. 12A and 12B, the ALD deposition process of the third conductive material 1275-1 may also fill the first vertical opening. In some embodiments, the third conductive material 1275-1 may be deposited with a previous (e.g., second) conductive contact material to form a composition graded contact material.
As shown in fig. 12C and 12D, the method includes removing a portion of the third conductive contact material 1275-1 to recess the third conductive contact material 1275-1. In one example, the removal process may be performed using an ALE process. However, embodiments are not limited to this example. In one example, the third conductive material 1275-1 may be recessed back in the horizontal opening 833 of fig. 8C to make electrical contact with the second conductive material 1273-1 and have a thickness of about ten (10) nanometers (nm). However, embodiments are not limited to this example, and other thicknesses may be suitably employed according to particular design rules and/or sizing of the three-node horizontal access device.
Fig. 13A-13D illustrate an example method for source/drain integration in a three-node horizontally oriented access device at a particular point in time in a semiconductor fabrication process, according to several embodiments of the present disclosure. Fig. 13A and 13C are cross-sectional side views of source/drain integration in the horizontal access device region 1342 after a storage node (e.g., a capacitor cell) is formed in the storage node region 1344 that extends left and right along the plane of the drawing (e.g., along cut line B-B' in fig. 8A) in the second direction 1305 (D2). Fig. 13B and 13D are end views of source/drain integration in the formation of a three-node horizontally oriented access device at a particular point in time in the semiconductor fabrication process. According to an embodiment, the point in time in the semiconductor fabrication process illustrated in fig. 13A-13D may be subsequent to the structure and point in time illustrated in fig. 12A-12D. However, the embodiments are not limited thereto.
As shown in fig. 13A and 13B, the method may include depositing conductive channel material 1398 in electrical contact with third conductive material 1375-1, the third conductive material 1375-1 being in electrical contact with second conductive material 1373-1. In one example, depositing the conductive channel material 1398 includes depositing a degenerate semiconductor material. As used herein, degenerate semiconductor material is intended to mean a semiconductor material (e.g., polysilicon) that contains a high degree of doping and significant interactions between dopants (e.g., phosphorus (P), boron (B), etc.). In contrast, non-degenerate semiconductors contain moderate doping, where the dopant atoms are well separated from each other in the semiconductor host lattice and have negligible interactions.
In one example, depositing conductive channel material 1398 includes depositing conductive channel material 1398 having an electronic bandgap higher than that of a subsequent conductive material. In one embodiment, depositing conductive channel material 1398 includes depositing conductive channel material 1398 having a conduction band offset (e.g., a fermi level offset from the implant electrode (first electrode 1361 of the capacitor cell)) that is higher than the conduction band offset of third conductive material 1375-1 and higher than the conduction band offset of the subsequent conductive material. Further, in some embodiments, the conductive channel material 1398 may be a metal material. In some embodiments, the conductive channel material 1398 may comprise indium oxide (In)2O3) Or indium tin oxide (In)2-xSnxO3) At least one of (a). Conductive channel material 1398 may have an electronic bandgap that is higher than the electronic bandgap of a subsequent conductive material (e.g., conductive material 1475-2 shown with respect to fig. 14) and a conduction band offset that is higher than the conduction band offset of the subsequent conductive material.
In some embodiments, a multilayer conductive channel material with reverse channel passivation may be deposited as conductive channel material 1398. For example, Indium Gallium Zinc (IGZO) rich indium gallium oxide (IGZO) conductive channel material 1398 is deposited to form a first layer of conductive channel material 1398, and indium (In) poor material relative to the first layer is next deposited as part of the IGZO conductive channel material to form a leakage suppression layer. In one example, the gallium (Ga) -rich layer relative to the first layer is deposited as part of the IGZO conductive channel materialTo form a leakage inhibiting layer. In one example, a zinc (Zn) -rich layer opposite the first layer is deposited as part of the IGZO conductive channel material to form a leakage suppression layer. In one example, gallium oxide (GaO)x) The layer is deposited as part of the IGZO conductive channel material to form a leakage suppression layer. In one embodiment, the leakage inhibiting layer is an oxide layer. One example for Channel region formation using an ALD process is disclosed in co-pending U.S. patent application No. 16/986,466, co-pending co-application No. 1013.0560001, Channel Integration in Three-Node Access Device for Vertical Three-Dimensional (3D) Memory, attorney docket No. 1013.0560001, having at least one co-inventor and entitled Channel Integration in Three-Node Access Device for Vertical Three-Dimensional (3D) Memory. The U.S. patent application is incorporated by reference herein in its entirety. Other suitable semiconductor fabrication techniques may be used to form conductive channel material 1398.
The conductive channel material 1398 may be deposited such that the conductive channel material 1398 fills the entire opening and is deposited on the area beside the opening, such as in the first vertical opening 871 in figure 8A. Figure 13B illustrates an end view of the three-node horizontal access device formation in this particular stage of the semiconductor fabrication process.
In one example, depositing the conductive channel material 1398 includes filling the first horizontal opening using an ALD process to form an electrical contact with the third conductive material 1375-1. As shown in fig. 13A and 13B, the ALD deposition process of the conductive channel material 1398 may also fill the first vertical opening.
As shown in fig. 13C and 13D, the method includes removing a portion of the conductive channel material 1398 to recess the conductive channel material. In one example, the removal process may be performed using an ALE process. However, embodiments are not limited to this example. In one example, the conductive channel material 1398 may be recessed back in the horizontal opening 833 of fig. 8C to make electrical contact with the third conductive material 1375-1 and have a length (L) (e.g., 1778 in fig. 17) of approximately fifty (50) nanometers (nm). However, embodiments are not limited to this example, and other lengths (L) of the conductive channel material 1375-1 may be suitably employed depending on the particular design rules and/or sizing of the three-node horizontal access device.
Fig. 14A-14D illustrate an example method for source/drain integration in a three-node horizontally oriented access device at a particular point in time in a semiconductor fabrication process, according to several embodiments of the present disclosure. Fig. 14A and 14C are cross-sectional side views of source/drain integration in the horizontal access device region 1442 after storage nodes (e.g., capacitor cells) are formed in the storage node region 1444 that extends left and right along the plane of the drawing (e.g., along cut line B-B' in fig. 8A) in the second direction 1405 (D2). Fig. 14B and 14D are end views of source/drain integration in the formation of a three-node horizontally oriented access device at a particular point in time in the semiconductor fabrication process. According to an embodiment, the point in time in the semiconductor manufacturing process illustrated in fig. 14A-14D may be subsequent to the structure and point in time illustrated in fig. 13A-13D. However, the embodiments are not limited thereto.
The source/drain integration methods illustrated in figures 14A-14D, 15A-15D, 16A-16D may be used to form a second source/drain region associated with the digit line contact side of a three-node horizontal access device structure. Thus, for convenience, and not by way of limitation, the discussion refers to the second source/drain as a digit line contact conductive material.
As shown in fig. 14A and 14B, the method may include depositing a first digit line contact conductive material 1475-2 in electrical contact with a conductive channel material (e.g., channel material 1398 described with respect to fig. 13A-13D), the conductive channel material in electrical contact with a third conductive material 1475-1 to a previously formed source/drain integration (e.g., a first source/drain region). In one example, depositing the first digit line contact conductive material 1475-2 includes depositing a degenerate semiconductor material. As used herein, degenerate semiconductor material is intended to mean a semiconductor material (e.g., polysilicon) that contains a high degree of doping and significant interactions between dopants (e.g., phosphorus (P), boron (B), etc.). In contrast, non-degenerate semiconductors contain moderate doping, where the dopant atoms are well separated from each other in the semiconductor host lattice and have negligible interactions.
In one example, depositing the first digit line conductive material 1475-2 includes depositing the first digit line conductive material having an electronic bandgap lower than the electronic bandgap of the channel material (e.g., 1398 in fig. 13A-13D). In one embodiment, depositing the first digit line conductive material 1475-2 includes depositing the first digit line contact conductive material 1475-2 having a conduction band offset (e.g., a fermi level offset from an injection electrode (in this example, digit line 1699 in fig. 16A-16D)) intermediate to a conduction band offset of the conductive channel material 1498 and a conduction band offset of a subsequent digit line contact conductive material.
In some embodiments, the first digit line contact conductive material 1475-2 may include indium oxide (In)2O3) Or indium tin oxide (In)2-xSnxO3) At least one of (a). The digit line contact conductive material 1475-2 may have an electronic bandgap that is higher than an electronic bandgap of a subsequent digit line contact conductive material (such as digit line contact conductive material 1573-2 shown with respect to fig. 15A-15D) and a conduction band offset that is higher than a conduction band offset of the subsequent digit line contact conductive material. In some embodiments, the electronic bandgap of the first digit line contact conductive material 1475-2 can be intermediate the electronic bandgap of a subsequent digit line contact conductive material formed by the electronic bandgap of the conductive channel material (e.g., 1398 in fig. 13A-13D) making electrical contact with the first digit line conductive material 1475-2.
In one example, depositing the first digit line contact conductive material 1475-2 includes depositing a metal material (e.g., layer) that forms a conductive oxide in contact with an oxide semiconductor material. For example, in one embodiment, depositing the first digit line contact conductive material 1475-2 includes depositing a highly doped degenerate semiconductor. In one example, depositing the first digit line contact conductive material 1475-2 includes depositing indium oxide (In)2O3) The composition contacts the conductive material 1475-2 as a first digit line. In one example, depositing the first digit line contact conductive material 1475-2 includes depositing indium tin oxide (In)2-xSnxO3) The composition contacts the conductive material 1475-2 as a first digit line. However, embodiments are not limited to these examples.
The first digit line contact conductive material 1475-2 can be deposited such that the first digit line contact conductive material 1475-2 fills the entire opening and is deposited on the area beside the opening, such as in the first vertical opening 871 in figure 8A. Figure 14B illustrates an end view of the three-node horizontal access device formation in this particular stage of the semiconductor fabrication process.
In one example, depositing the first digit line contact conductive material 1475-2 includes filling the first horizontal opening using an ALD process. As shown in fig. 14A and 14B, the ALD deposition process of the first digit line contact conductive material 1475-2 may also fill the first vertical opening. In some embodiments, the digit line contact conductive material 1475-2 can have a composition that includes one or more of In, Zn, and Ga combined with the IGZO channel material at varying ratios or varying stoichiometry.
As shown in fig. 14C and 14D, the method includes removing a portion of the first digit line contact conductive material 1475-2 to recess the first conductive contact material. In one example, the removal process may be performed using an ALE process. However, embodiments are not limited to this example. In one example, the first digit line contact conductive material 1475-2 can be recessed back into the horizontal opening 833 of figure 8C to form an electrical contact with the conductive channel material and have a thickness of about ten (10) nanometers (nm). However, embodiments are not limited to this example, and other thicknesses may be suitably employed according to particular design rules and/or sizing of the three-node horizontal access device.
Fig. 15A-15D illustrate an example method for source/drain integration (e.g., digit line contact conductive material) in a three-node horizontally oriented access device at a particular point in time in a semiconductor fabrication process, according to several embodiments of the present disclosure. Fig. 15A and 15C are cross-sectional side views of source/drain integration in horizontal access device region 1542 after a storage node (e.g., a capacitor cell) is formed in storage node region 1544 that extends left and right along the plane of the drawing (e.g., along cut line B-B' in fig. 8A) in second direction 1505 (D2). Fig. 15B and 15D are end views of source/drain integration in the formation of a three-node horizontally oriented access device at a particular point in time in the semiconductor fabrication process. According to an embodiment, the point in time in the semiconductor manufacturing process illustrated in fig. 15A-15D may be subsequent to the structure and point in time illustrated in fig. 14A-14D. However, the embodiments are not limited thereto.
As shown in fig. 15A and 15B, the method may include depositing a second digit line contact conductive material 1573-2 in electrical contact with a first digit line contact conductive material 1575, the first digit line contact conductive material 1575 in electrical contact with the conductive channel material 1398 in fig. 13A-13D. In one example, depositing the second digit line contact conductive material 1573-2 includes depositing a degenerate semiconductor material. As used herein, degenerate semiconductor material is intended to mean a semiconductor material (e.g., polysilicon) that contains a high degree of doping and significant interactions between dopants (e.g., phosphorus (P), boron (B), etc.). In contrast, non-degenerate semiconductors contain moderate doping, where the dopant atoms are well separated from each other in the semiconductor host lattice and have negligible interactions.
In one example, depositing the second digit line conductive material 1573-2 includes depositing the second digit line contact conductive material 1573-2 having an electronic bandgap that is lower than an electronic bandgap of the first digit line contact conductive material 1575. In one embodiment, depositing the second digit line contact conductive material 1573-2 includes depositing the second conductive material 1573-2 having a conduction band offset (e.g., a fermi level offset from an injection electrode (in this example, digit line 1699 in fig. 16A-16D)) intermediate the conduction band offset of the first digit line contact conductive material 1575 and the conduction band offset of a subsequent digit line material. Furthermore, in some embodiments, the second digit line contact conductive material 1573-2 may be a metal composition material. In some embodiments, the digit line contact conductive material 1573-2 may include indium oxide (In)2O3) Or indium tin oxide (In)2-xSnxO3) At least one of (a). The second digit line contact conductive material 1573-2 may have an electronic bandgap that is higher than an electronic bandgap of a subsequent digit line material (such as digit line material 1699 shown with respect to fig. 16) and a conduction band offset that is higher than a conduction band offset of the subsequent digit line material.
In one example, depositing the second digit line contact conductive material 1573-2 includes depositing a metal composition material (e.g., layer) that forms a conductive oxide in contact with the oxide semiconductor material. For example, in a real worldIn an embodiment, depositing the second digit line contact conductive material 1573-2 includes depositing a highly doped degenerate semiconductor. In one example, depositing the second digit line contact conductive material 1573-2 includes depositing indium oxide (In)2O3) The composition serves as a second digit line contact conductive material 1573-2. In one example, depositing the second digit line contact conductive material 1573-2 includes depositing indium tin oxide (In)2- xSnxO3) The composition serves as a second digit line contact conductive material 1573-2. However, embodiments are not limited to these examples.
The second digit line contact conductive material 1573-2 may be deposited such that the second digit line contact conductive material 1573-2 fills the entire opening and is deposited on the area beside the opening, such as in the first vertical opening 871 in figure 8A. Figure 15B illustrates an end view of the three-node horizontal access device formation in this particular stage of the semiconductor fabrication process.
In one example, depositing the second digit line contact conductive material 1573-2 includes filling the first horizontal opening using an ALD process to form an electrical contact with the first digit line contact conductive material 1575. As shown in fig. 15A and 15B, the ALD deposition process of the second digit line contact conductive material 1573-2 may also fill the first vertical opening.
As shown in fig. 15C and 15D, the method includes removing a portion of the second digit line contact conductive material 1573-2 to recess the second digit line contact conductive material 1573-2. In one example, the removal process may be performed using an ALE process. However, embodiments are not limited to this example. In one example, the second digit line contact conductive material 1573-2 may be recessed back into the horizontal opening 833 in fig. 8C to form electrical contact with the first digit line contact conductive material 1575-2 and have a thickness of about ten (10) nanometers (nm). However, embodiments are not limited to this example, and other thicknesses may be suitably employed according to particular design rules and/or sizing of the three-node horizontal access device.
Fig. 16A-16D illustrate an example method for source/drain integration in a three-node horizontally oriented access device at a particular point in time in a semiconductor fabrication process, according to several embodiments of the present disclosure. In one example, fig. 16A-16D illustrate an example method for forming a digit line contact 1699 to a second digit line contact conductive material. Digit line 1699 may form a horizontally oriented digit line similar to digit lines 107, 207, and 307 shown in figures 1-3 to a three node horizontally oriented access device.
Fig. 16A and 16C are cross-sectional side views of source/drain integration in the horizontal access device region 1642 after formation of a storage node (e.g., a capacitor cell) in a storage node region 1644 extending left and right along the plane of the drawing (e.g., along cut line B-B' in fig. 8A) in the second direction 1605 (D2). Fig. 16B and 16D are end views of source/drain integration in the formation of a three-node horizontally oriented access device at a particular point in time in the semiconductor fabrication process. According to an embodiment, the point in time in the semiconductor manufacturing process illustrated in fig. 16A-16D may be subsequent to the structure and point in time illustrated in fig. 15A-15D. However, the embodiments are not limited thereto.
As shown in fig. 16A and 16B, the method may include depositing digit line material 1699 in electrical contact with a second digit line contact conductive material 1673-2, the second digit line contact conductive material 1673-2 in electrical contact with the first digit line contact conductive material 1675-2. In one example, depositing digit line material 1699 includes depositing metal digit line material 1699.
For example, depositing the digit line material 1699 can include depositing a ruthenium (Ru) -containing digit line material 1699. In one example, depositing the digit line material 1699 includes depositing a material containing molybdenum (Mo). In one example, depositing the digit line material 1699 includes depositing a nickel (Ni) -containing material. In one example, depositing the digit line material 1699 includes depositing a titanium (Ti) -containing material. In one example, depositing the digit line material 1699 includes depositing a copper (Cu) -containing material. In one example, depositing the digit line material 1699 includes depositing a tin (Sn) -containing material. However, embodiments are not limited to these examples.
In one example, depositing the digit line material 1699 includes filling the remaining first horizontal opening (e.g., 833 in fig. 8C) using an ALD process to form an electrical contact with the second digit line contact conductive material 1673-2. As shown in fig. 16A-16D, the ALD deposition process of the digit line material 1699 can also fill the first vertical opening (e.g., 871 in fig. 8A).
In some embodiments, the vertically oriented access lines 1640-3 may be formed to have a width (W)1679 that is greater than a horizontal length (L)1678 of the vertically oriented access lines 1640-3 that extends horizontally in the second direction (D2) 1605. In some embodiments, such as shown in FIG. 16C, the length (L)1678-2 of the vertically oriented access lines 1640-3 may horizontally overlap with both the multilayer digit line contact conductive material (e.g., 1675-2) and the multilayer source/drain regions (e.g., 1675-1) on the cell side. In some embodiments, the digit line material 1699 is integrated to make electrical contact with the digit line contact conductive material 1673-2. Vertical access lines 1640-3, such as Word Lines (WL), may be integrated to oppose the conductive channel material and separated therefrom by a gate dielectric to form a three-node access device of memory cells without body contacts.
According to the source/drain integration embodiments described herein, vertically oriented access lines 1640-3 (similar to access lines 103, 203, and 303 shown in fig. 1-3) may be formed to have shorter lengths 1678-1(L) due to the materials and techniques providing lower off current (Ioff) to a three-node horizontally oriented access device. In the example embodiment shown in fig. 16A, the vertical access lines 1640-3 may have a length 1678-1(L) that is less than the horizontal length of channel material (e.g., channel material 1398 shown with respect to fig. 13) extending in the second direction (D2) 1605. Thus, the vertically oriented access lines 1640-3 may be horizontally underlapped with both the multilayer digit line contact conductive material 1675-2 and the nth layer (on the capacitor cell side) of the multilayer source/drain region 1675-1.
FIG. 17 illustrates a three-node horizontally oriented access device 1742 coupled to a horizontally oriented storage node 1744 of a vertical three-dimensional (3D) memory in accordance with an embodiment of the present disclosure. In fig. 17, a three-node horizontally oriented access device 1742 is illustrated as extending left and right in the plane of the drawing in a second direction (D2) 1705. Horizontally oriented access device 1742 is illustrated as having a first multi-layered source/drain region 1798-1A in electrical contact with a first electrode 1761, e.g., a bottom electrode, of a horizontally oriented storage node 1744, e.g., a capacitor cell. The storage node 1744 may comprise a capacitor cell having a first horizontally oriented electrode 1761 electrically coupled to a first source/drain region 1798-1A of a three-node access device 1742 and a second electrode 1756 separated from the first horizontally oriented electrode 1761 by a cell dielectric 1763. In some embodiments, the horizontally oriented storage node 1744 is in direct electrical contact with the first source/drain region 1798-1A of the three-node access device 1742 on the same plane as the first source/drain region 1798-1A.
Channel region 1798-1B is illustrated in electrical contact with first source/drain region 1798-1A. Vertically oriented access lines 1740-3 are opposite channel region 1798-1B and are separated therefrom by a gate dielectric. Vertically oriented access lines 1740-2 are illustrated by dashed lines indicating that vertically oriented access lines are disposed in and out of the plane of the drawing sheet. The vertically oriented access lines 1740 may extend longer and/or shorter than the channel region in the second direction (D2)1705, e.g., with source/drain overlap and/or underlap, according to particular design rules.
A second source/drain region 1798-1C (e.g., a multi-layer digit line contact conductive material) is illustrated in electrical contact with the channel region 1798-1B and in electrical contact with a horizontally oriented digit line 1799 extending into and out of the plane of the drawing sheet and integrated into the horizontally oriented digit line 1799. In some embodiments, the first and second source/drain regions 1798-1A/C may be formed from one or more of indium (In), zinc (Zn), and gallium (Ga) combined to the IGZO channel material at varying ratios or varying stoichiometries.
As shown in fig. 17, the horizontally oriented access device 1742 and the horizontally oriented storage node 1744 may be horizontally spaced from adjacent memory cells along the second direction (D2)1705 by an interlayer dielectric material 1780 and may be vertically spaced from stacked adjacent cells in a three-dimensional (3D) memory by dielectric layers 1730-1 and 1730-2. In some embodiments, a horizontally oriented digit line 1799 can be integrated to make electrical contact with the multi-layer second source/drain region 1798-1C. The multi-layer first source/drain region 1798-1A can include a first conductive material that makes electrical contact with a storage node of the three-node access device 1742. In some embodiments, vertically oriented access lines opposite and separated from the channel material 1798-1B by a gate dielectric can be integrated to form a three-node access device 1742 of memory cells without body contacts. In some embodiments, the horizontally oriented digit line 1799 is in direct electrical contact with the second source/drain region 1798-1C of the three-node access device 1742 on the same plane as the height of the second source/drain region 1798-1C.
Fig. 18 is a block diagram of an apparatus in the form of a computing system 1800 that includes a memory device 1803 in accordance with several embodiments of the present disclosure. As used herein, memory device 1803, memory array 1810, and/or host 1802 can also be considered an "apparatus" alone. According to an embodiment, the memory device 1802 may include at least one memory array 1810 having three-node access devices of vertical three-dimensional (3D) memory, as has been described herein.
In this example, the system 1800 includes a host 1802 coupled to a memory device 1803 via an interface 1804. Computing system 1800 can be a personal laptop computer, desktop computer, digital camera, mobile phone, memory card reader, or internet of things (IoT) enabled device, among various other types of systems. The host 1802 may include a number of processing resources (e.g., one or more processors, microprocessors, or some other type of control circuitry) that are capable of accessing the memory 1803. The system 1800 can include separate integrated circuits, or both the host 1802 and the memory device 1803 can be on the same integrated circuit. For example, the host 1802 can be a system controller for a memory system that includes a plurality of memory devices 1803, wherein the system controller 1805 provides access to a respective memory device 1803 through another processing resource, such as a Central Processing Unit (CPU).
In the example shown in fig. 18, the host 1802 is responsible for executing an Operating System (OS) and/or various applications (e.g., processes) that may be loaded thereto (e.g., from the memory device 1803 via the controller 1805). The OS and/or various applications may be loaded from memory device 1803 by providing access commands from host 1802 to memory device 1803 to access data including the OS and/or various applications. The host 1802 may also access data utilized by the OS and/or various applications by providing access commands to the memory device 1803 to retrieve the data for execution of the OS and/or various applications.
For clarity, system 1800 has been simplified to focus on features that are of particular relevance to the present disclosure. The memory array 1810 may be a DRAM array, an SRAM array, an STT RAM array, a PCRAM array, a TRAM array, a RRAM array, a NAND flash array, and/or a NOR flash array comprising at least one three-node access device of three-dimensional (3D) memory. For example, memory array 1810 may be an unshielded DL 4F2 array, such as a 3D-DRAM memory array. The array 1810 may include memory cells arranged in rows coupled by word lines (which may be referred to herein as access lines or select lines) and columns coupled by digit lines (which may be referred to herein as sense lines or data lines). Although a single array 1810 is shown in fig. 1, embodiments are not so limited. For example, memory device 1803 may include several arrays 1810 (e.g., several banks of DRAM cells).
The memory device 1803 includes address circuitry 1806 for latching address signals provided via the interface 1804. The interface may comprise, for example, a physical interface employing a suitable protocol (e.g., a data bus, an address bus, and a command bus or a combined data/address/command bus). This protocol may be custom or proprietary, or the interface 1804 may employ a standardized protocol, such as peripheral component interconnect express (PCIe), Gen-Z, CCIX, or the like. Address signals are received and decoded by a row decoder 1808 and a column decoder 1812 to access the memory array 1810. Data can be read from the memory array 1810 by sensing voltage and/or current changes on sense lines using sensing circuitry 1811. The sense circuitry 1811 can include, for example, sense amplifiers that can read and latch a page (e.g., a row) of data from the memory array 1810. I/O circuitry 1807 may be used for bi-directional data communication with host 1802 via interface 1804. Read/write circuitry 1813 is used to write data to the memory array 1810 or read data from the memory array 1810. As an example, circuitry 1813 may include various drivers, latch circuitry, and so forth.
Control circuitry 1805 decodes signals provided by host 1802. The signal may be a command provided by the host 1802. These signals may include a chip enable signal, a write enable signal, and an address latch signal used to control operations performed on the memory array 1810, including data read operations, data write operations, and data erase operations. In various embodiments, control circuitry 1805 is responsible for executing instructions from host 1802. Control circuitry 1805 may comprise a state machine, a sequencer, and/or some other type of control circuitry, which may be implemented in hardware, firmware, or software, or any combination of the three. In some examples, host 1802 can be a controller external to memory device 1803. For example, host 1802 may be a memory controller coupled to the processing resources of a computing device.
The term "semiconductor" may refer to materials, wafers, or substrates, for example, and includes any basic semiconductor structure. It is understood that "semiconductor" includes silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, Thin Film Transistor (TFT) technology, doped and undoped semiconductors, epitaxial silicon supported by a base semiconductor structure, and other semiconductor structures. Furthermore, when reference is made to semiconductors in the above description, previous process steps may have been used to form regions/junctions in the basic semiconductor structure, and the term "semiconductor" may include the underlying material containing such regions/junctions.
The figures herein follow a numbering convention in which the first or first digit or digits correspond to the figure number and the remaining digits identify an element or component in the drawing. Similar (e.g., identical) elements or components between different figures may be identified by the use of similar digits. It should be appreciated that elements shown in the various embodiments herein may be added, exchanged, and/or eliminated so as to provide several additional embodiments of the present disclosure. Additionally, it should be understood that the proportion and the relative scale of the elements provided in the figures are intended to illustrate the embodiments of the present disclosure, and should not be taken as limiting.
As used herein, "number" or "amount" something may refer to one or more such things. For example, a number or quantity of memory cells may refer to one or more memory cells. "multiple" something is desirably two or more. As used herein, performing multiple actions simultaneously refers to actions that at least partially overlap within a particular time period. As used herein, the term "coupled" may include electrically coupled, directly coupled and/or directly connected (e.g., by direct physical contact) without intervening elements, indirectly coupled and/or connected using intervening elements, or wirelessly coupled. The term "coupled" may further include two or more elements that cooperate or interact with each other (e.g., in a causal relationship). An element coupled between two elements may be between the two elements and coupled to each of the two elements.
It is recognized that the term "vertical" contemplates variations from "exactly" vertical that result from conventional manufacturing, measurement, and/or assembly variations, and one of ordinary skill in the art will understand what is meant by the term "vertical". For example, vertical may correspond to the z-direction. As used herein, a particular element may overlie another element, may be above or transverse to the other element, and/or may be in direct physical contact with the other element when the element is "adjacent" the other element. "transverse" may refer to a horizontal direction (e.g., y-direction or x-direction), which may be perpendicular to the z-direction, for example.
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that an arrangement calculated to achieve the same results may be substituted for the specific embodiments shown. This disclosure is intended to cover adaptations or variations of various embodiments of the disclosure. It is to be understood that the above description has been made in an illustrative fashion, and not a restrictive one. Combinations of the above embodiments, and other embodiments not specifically described herein, will be apparent to those of skill in the art upon reviewing the above description. The scope of the various embodiments of the present disclosure includes other applications in which the above structures and methods are used. The scope of various embodiments of the disclosure should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims (15)

1. A method for forming a vertically stacked array of memory cells having horizontally oriented access devices and vertically oriented access lines, comprising:
depositing alternating layers of dielectric material (430-1, …, 430-N; 530-1, …, 530-N; 630-1, …, 630-N; 730-1, …, 730-N; 830-1, …, 830-N; 930-1, …, 930-N; 1030-1, 1030-2; 1130-1, 1130-2; 1230-1, 1230-2; 1330-1, 1330-2; 1430-1, 1430-2; 1530-1, 1530-2; 1630-1, 1630-2; 1730-1, 1730-2) and sacrificial material (432-1, …, 432-N; 532-1, …, 532-N; 632-1, …, 632-N; 732-1, …, 732-N) to form a vertical stack;
forming a plurality of first vertical openings (500) having a first horizontal direction (109, 209, 309, 509, 609, 709, 809, 909, 1009, 1109, 1209, 1309, 1409, 1509, 1609) and a second horizontal direction (105, 205, 305, 505, 605, 705, 805, 905, 1005, 1105, 1205, 1305, 1405, 1505, 1605, 1705), through the vertical stack to a substrate, and extending primarily in the second horizontal direction to form elongated vertical pillars (513, 542-1, 542-2, 542-3) having sidewalls (514) in the vertical stack;
conformally depositing a gate dielectric (304, 538, 638, 738, 838, 938, 1038, 1138, 1238, 1338, 1438, 1538, 1638) in the plurality of first vertical openings;
forming a conductive material (540-1, 540-2, 540-3, 540-4) on the gate dielectric;
removing portions of the conductive material to form a plurality of separate, vertical access lines (640-1, …, 640-N, 640- (N +1), …, 640- (Z-1), 640-Z; 740-1, …, 740-N, 740- (N +1), …, 740- (Z-1), 740-Z; 840-1, …, 840-N, 840- (N +1), …, 840- (Z-1), 840-Z; 940-1, …, 940-N, 940- (N +1), …, 940- (Z-1), 940-Z; 1040-2, 1040-3; 1140-2, 1140-3; 1240-2, 1240-3; 1340-2, 1340-3; 1340-1, 740-1), 740-Z, 840-1, 840-Z, 840-1, 1140-Z, 1140-1, and/or portions of the conductive material along the sidewalls of the elongated vertical pillars, 1340-3; 1440-2, 1440-3; 1540-2, 1540-3; 1640-2, 1640-3; 1740-3);
repairing a first side of the gate dielectric exposed at the conductive material removal (645);
forming second vertical openings (871-1, 871-2; 971-1, 971-2; 1071-1; 1171-1; 1271-1; 1371-1; 1471-1, 1571-1; 1671-1) through the vertical stack and extending primarily in the first horizontal direction to expose sidewalls of first regions (742; 842; 942; 1042, 1142; 1242; 1342; 1424; 1542; 1642; 1742) adjacent the sacrificial material;
selectively removing the sacrificial material in the first region a first horizontal distance from the second vertical opening to form a first horizontal opening (833-1, …, 833-N); and
a first source/drain region (998-1A), a channel region (998-1B, …, 998-NB), and a second source/drain region (998-1C) are deposited in the first horizontal opening.
2. The method of claim 1, wherein repairing the first side (645) of the gate dielectric (304, 538, 638, 738, 838, 938, 1038, 1138, 1238, 1338, 1438, 1538, 1638) exposed to the removal of the conductive material (540-1, 540-2, 540-3, 540-4) comprises:
ionizing oxygen or oxygen-containing species or a mixed gas in a ratio that preferentially repairs the gate dielectric while minimizing the plurality of separate, vertical access lines (640-1, …, 640-N, 640- (N +1), …, 640- (Z-1), 640-Z, 740-1, …, 740-N, 740- (N +1), …, 740- (Z-1), 740-Z, 840-1, …, 840-N, 840- (N +1), …, 840- (Z-1), 840-Z, 940-1, …, 940-N, 940- (N +1), …, 940- (Z-1), 940-Z, 1040-2, 1040-3, 1140-2, 1140-3, 1240-2, 1240-3, 1340-2, 1340-3; 1440-2, 1440-3; 1540-2, 1540-3; 1640-2, 1640-3; 1740-3).
3. The method of any of claims 1-2, further comprising performing a surface treatment on the gate dielectric (304, 538, 638, 738, 838, 938, 1038, 1138, 1238, 1338, 1438, 1538, 1638) to deposit a liner (651) thereon, the liner having a combination that provides a mixture of molecular oxygen and ionized species.
4. The method of any of claims 1-2, wherein repairing the first side (645) of the gate dielectric (304, 538, 638, 738, 838, 938, 1038, 1138, 1238, 1338, 1438, 1538, 1638) comprises pulsing ionized metal atoms used to form the gate dielectric into contact with a surface of the first side by plasma vapor deposition to return the first side of the gate dielectric to a desired stoichiometry.
5. The method of any of claims 1-2, wherein repairing the first side (645) of the gate dielectric (304, 538, 638, 738, 838, 938, 1038, 1138, 1238, 1338, 1438, 1538, 1638) comprises flowing ozone to react with a surface on the first side while limiting ozone from forming the plurality of separate, vertical lines (640-1, …, 640-N, 640- (N +1), …, 640- (Z-1), 640-Z, 740-1, …, 740-N, 740- (N +1), …, 740- (Z-1), 740-Z, 840-1, …, 840-N, 840- (N +1), …, 840- (Z-1), 840-Z, 940-1, …, 940-N, access, 940-N, or combinations thereof, 940- (N +1), …, 940- (Z-1), 940-Z; 1040-2, 1040-3; 1140-2, 1140-3; 1240-2, 1240-3; 1340-2, 1340-3; 1440-2, 1440-3; 1540-2, 1540-3; 1640-2, 1640-3; 1740-3) of said conductive material (540-1, 540-2, 540-3, 540-4).
6. The method of any of claims 1-2, further comprising repairing a second side (846) of the gate dielectric (304, 538, 638, 738, 938, 838, 1038, 1138, 1238, 1338, 1438, 1638) exposed to removal of the sacrificial material (432-1, …, 432-N; 532-1, …, 532-N; 632-1, …, 632-N; 732-1, …, 732-N) in the first region (742; 842; 942; 1042; 1142; 1242; 1342; 1424; 1542; 1642; 1742).
7. A method for forming a vertically stacked array of memory cells having horizontally oriented access devices and vertically oriented access lines, comprising:
depositing alternating layers of dielectric material (430-1, …, 430-N; 530-1, …, 530-N; 630-1, …, 630-N; 730-1, …, 730-N; 830-1, …, 830-N; 930-1, …, 930-N; 1030-1, 1030-2; 1130-1, 1130-2; 1230-1, 1230-2; 1330-1, 1330-2; 1430-1, 1430-2; 1530-1, 1530-2; 1630-1, 1630-2; 1730-1, 1730-2) and sacrificial material (432-1, …, 432-N; 532-1, …, 532-N; 632-1, …, 632-N; 732-1, …, 732-N) to form a vertical stack;
forming a plurality of first vertical openings (500) having a first horizontal direction (109, 209, 309, 509, 609, 709, 809, 909, 1009, 1109, 1209, 1309, 1409, 1509, 1609) and a second horizontal direction (105, 205, 305, 505, 605, 705, 805, 905, 1005, 1105, 1205, 1305, 1405, 1505, 1605, 1705), through the vertical stack, and extending primarily in the second horizontal direction to form elongated vertical pillars (513, 542-1, 542-2, 542-3) having sidewalls (514) in the vertical stack;
conformally depositing a gate dielectric (304, 538, 638, 738, 838, 938, 1038, 1138, 1238, 1338, 1438, 1538, 1638) in the plurality of first vertical openings;
forming a conductive material (540-1, 540-2, 540-3, 540-4) on the gate dielectric;
removing portions of the conductive material to form a plurality of separate, vertical access lines (640-1, …, 640-N, 640- (N +1), …, 640- (Z-1), 640-Z; 740-1, …, 740-N, 740- (N +1), …, 740- (Z-1), 740-Z; 840-1, …, 840-N, 840- (N +1), …, 840- (Z-1), 840-Z; 940-1, …, 940-N, 940- (N +1), …, 940- (Z-1), 940-Z; 1040-2, 1040-3; 1140-2, 1140-3; 1240-2, 1240-3; 1340-2, 1340-3; 1440-2, 1440-3; 1540-2; 940-1, 940-3), 1540-3; 1640-2, 1640-3; 1740-3);
repairing a first side of the gate dielectric exposed at the conductive material removal (645);
forming second vertical openings (871-1, 871-2; 971-1, 971-2; 1071-1; 1171-1; 1271-1; 1371-1; 1471-1, 1571-1; 1671-1) through the vertical stack and extending primarily in the first horizontal direction to expose sidewalls of first regions (742; 842; 942; 1042, 1142; 1242; 1342; 1424; 1542; 1642; 1742) adjacent the sacrificial material;
selectively removing the sacrificial material in the first region a first horizontal distance from the second vertical opening to form a first horizontal opening (833-1, …, 833-N);
repairing a second side (846) of the gate dielectric exposed to removal of the sacrificial material in the first region; and
a first source/drain region (998-1A), a channel region (998-1B, …, 998-NB), and a second source/drain region (998-1C) are sequentially deposited in the first horizontal opening to form a horizontally oriented three node access device (938-1, …, 938-N; 1038; 1138; 1238; 1338; 1438; 1538; 1638).
8. The method of claim 7, further comprising repairing the second side (846) of the gate dielectric (304, 538, 638, 738, 838, 938, 1038, 1138, 1238, 1338, 1438, 1538, 1638) from within the first horizontal opening (833-1, …, 833-N) prior to sequentially depositing the first source/drain region (998-1A), the channel region (998-1B, …, 998-NB), and a second source/drain region (998-1C) in the first horizontal opening (833-1, …, 833-N).
9. The method of any of claims 7-8, wherein repairing the second side (846) of the gate dielectric (304, 538, 638, 738, 838, 938, 1038, 1138, 1238, 1338, 1438, 1538, 1638) comprises repairing a surface key termination on a surface of the second side of the gate dielectric.
10. The method of claim 9, wherein repairing the surface bond termination comprises flowing a mixture of molecular oxygen and ionized species to the surface of the second side (846) at a temperature ranging from about 150 degrees celsius (° c) to 600 ℃.
11. The method of any of claims 7-8, wherein repairing the second side (846) of the gate dielectric (304, 538, 638, 738, 838, 938, 1038, 1138, 1238, 1338, 1438, 1538, 1638) comprises pulsing ionized metal atoms for depositing the gate dielectric by plasma vapor deposition to a surface of the second side to return the gate dielectric to a desired stoichiometry and a desired surface bond termination.
12. A method for forming a vertically stacked array of memory cells having horizontally oriented access devices and vertically oriented access lines, comprising:
depositing alternating layers of dielectric material (430-1, …, 430-N; 530-1, …, 530-N; 630-1, …, 630-N; 730-1, …, 730-N; 830-1, …, 830-N; 930-1, …, 930-N; 1030-1, 1030-2; 1130-1, 1130-2; 1230-1, 1230-2; 1330-1, 1330-2; 1430-1, 1430-2; 1530-1, 1530-2; 1630-1, 1630-2; 1730-1, 1730-2) and sacrificial material (432-1, …, 432-N; 532-1, …, 532-N; 632-1, …, 632-N; 732-1, …, 732-N) to form a vertical stack;
forming a plurality of first vertical openings (500) having a first horizontal direction (109, 209, 309, 509, 609, 709, 809, 909, 1009, 1109, 1209, 1309, 1409, 1509, 1609) and a second horizontal direction (105, 205, 305, 505, 605, 705, 805, 905, 1005, 1105, 1205, 1305, 1405, 1505, 1605, 1705), through the vertical stack to a substrate, and extending primarily in the second horizontal direction to form elongated vertical pillars (513, 542-1, 542-2, 542-3) having sidewalls (514) in the vertical stack;
conformally depositing a gate dielectric material (304, 538, 638, 738, 838, 938, 1038, 1138, 1238, 1338, 1438, 1538, 1638) in the plurality of first vertical openings;
forming a conductive material (540-1, 540-2, 540-3, 540-4) on the gate dielectric;
removing portions of the conductive material to form a plurality of separate, vertical access lines (640-1, …, 640-N, 640- (N +1), …, 640- (Z-1), 640-Z; 740-1, …, 740-N, 740- (N +1), …, 740- (Z-1), 740-Z; 840-1, …, 840-N, 840- (N +1), …, 840- (Z-1), 840-Z; 940-1, …, 940-N, 940- (N +1), …, 940- (Z-1), 940-Z; 1040-2, 1040-3; 1140-2, 1140-3; 1240-2, 1240-3; 1340-2, 1340-3; 1340-1, 740-1), 740-Z, 840-1, 840-Z, 840-1, 1140-Z, 1140-1, and/or portions of the conductive material along the sidewalls of the elongated vertical pillars, 1340-3; 1440-2, 1440-3; 1540-2, 1540-3; 1640-2, 1640-3; 1740-3);
repairing a first side of the gate dielectric material exposed to the conductive material removal (645);
forming second vertical openings (871-1, 871-2; 971-1, 971-2; 1071-1; 1171-1; 1271-1; 1371-1; 1471-1, 1571-1; 1671-1) through the vertical stack and extending primarily in the first horizontal direction to expose sidewalls of first regions (742; 842; 942; 1042, 1142; 1242; 1342; 1424; 1542; 1642; 1742) adjacent the sacrificial material;
selectively removing the sacrificial material in the first region a first horizontal distance from the second vertical opening to form a first horizontal opening (833-1, …, 833-N) to a first electrode (761; 861; 961; 1061; 1161; 1261; 1361; 1461; 1561, 1661; 1761) in a second region (744; 844; 944; 1044, 1144; 1244; 1344; 1444; 1544; 1644; 1744) of the vertical stack;
repairing a second side (846) of the gate dielectric exposed to removal of the sacrificial material in the first region;
repairing a surface of the first electrode in the second region; and
a first source/drain region (998-1A), a channel region (998-1B, …, 998-NB), and a second source/drain region (998-1C) are deposited in the first horizontal opening.
13. The method of claim 12, further comprising:
forming a third vertical opening (751; 851; 951) through the vertical stack and extending primarily in the first horizontal direction (109, 209, 309, 509, 609, 709, 809, 909, 1009, 1109, 1209, 1309, 1409, 1509, 1609) to expose a sidewall of a second region (744; 844; 944; 1044, 1144; 1244; 1344; 1444; 1544; 1644; 1744) adjacent to the sacrificial material (432-1, …, 432-N; 532-1, …, 532-N; 632-1, …, 632-N; 732-1, …, 732-N);
selectively removing the sacrificial material in the second region a second horizontal distance from the third vertical opening to form a second horizontal opening; and
depositing the first electrode (761; 861; 961; 1061; 1161; 1261; 1361; 1461; 1561, 1661; 1761), dielectric material (763; 863; 963; 1063; 1163; 1263; 1363; 1463; 1563, 1663; 1763), and a second electrode (756; 856; 956; 1056; 1156; 1256; 1356; 1456; 1556, 1656; 1756) to form a storage node (207) in the second region.
14. The method of any one of claims 12 to 13, wherein repairing the surface of the first electrode (761; 861; 961; 1061; 1161; 1261; 1361; 1461; 1561; 1661; 1761) in the second region (744; 844; 944; 1044, 1144; 1244; 1344; 1444; 1544; 1644; 1744) comprises flowing a precursor to contact the surface of the first electrode using an Atomic Layer Deposition (ALD) process to prepare the surface of the first electrode as a process to restore conductive quality of the surface of the first electrode prior to flowing a gas mixture to contact the surface.
15. The method of any of claims 12 to 13, wherein repairing the surface of the first electrode (761; 861; 961; 1061; 1161; 1261; 1361; 1461; 1561, 1661; 1761) in the second region (744; 844; 944; 1144; 1244; 1344; 1444; 1544; 1644; 1744) comprises reducing the surface of the first electrode to remove metal oxide from the surface prior to sequentially depositing the first source/drain region (998-1A), the channel region (998-1B, …, 998-NB), and the second source/drain region (998-1C) in the first horizontal opening (833-1, …, 833-N).
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