CN114203122B

CN114203122B - Driving circuit, electronic device and driving method of display screen

Info

Publication number: CN114203122B
Application number: CN202111437734.2A
Authority: CN
Inventors: 李卓然
Original assignee: Vivo Mobile Communication Co Ltd
Current assignee: Vivo Mobile Communication Co Ltd
Priority date: 2021-11-30
Filing date: 2021-11-30
Publication date: 2023-03-14
Anticipated expiration: 2041-11-30
Also published as: CN114203122A

Abstract

The application discloses a driving circuit, electronic equipment and a driving method of a display screen, and belongs to the technical field of display devices. The application discloses drive circuit of display screen includes: the display driving circuit comprises a display driving chip, a first power supply, a second power supply, a control module and a power feedback module; the first power supply is connected with a first input end of the power feedback module, the second power supply is connected with a second input end of the power feedback module through the control module, a feedback end of the power feedback module is connected with a control end of the control module, a first output end of the power feedback module is connected with a first power supply pin of the display driving chip, and a second output end of the power feedback module is connected with a second power supply pin of the display driving chip; the control module is used for adjusting the output voltage of the second power supply according to the feedback control signal input by the power feedback module.

Description

Driving circuit, electronic device and driving method of display screen

Technical Field

The application belongs to the technical field of display devices, and particularly relates to a driving circuit, an electronic device and a driving method of a display screen.

Background

At present, when a Liquid Crystal Display (LCD) of a smart phone is powered, a 4power technology is usually used to power the LCD, that is, a Display Driver IC (hereinafter, referred to as DDIC) for driving the LCD is powered by 4 paths of power. Specifically, the 1 st path and the 2 nd path of the 4 paths of power supplies (the 1 st path, the 2 nd path, the 3 rd path and the 4 th path) supply power to the bias driving module in the display driving IC, the 3 rd path of power supply supplies power to the display IO module in the display driving IC, and the 3 rd path of power supply also supplies power to the digital logic module in the display driving IC together with the 4 th path of power supply.

However, when the 3 rd power supply and the 4 th power supply power to the digital logic module, since the energy ratio output by the two power supplies is usually a constant value, and the actual power supply scenario is affected by various factors, when the digital logic module is supplied with power according to the fixed energy ratio, the overall power consumption may be large.

Disclosure of Invention

An object of the embodiments of the present application is to provide a driving circuit, an electronic device, and a driving method for a display screen, which can solve the problem of large power consumption when a 4power technology is used to supply power to an LCD display screen.

In a first aspect, an embodiment of the present application provides a driving circuit of a display screen, where the driving circuit includes: the display driving circuit comprises a display driving chip, a first power supply, a second power supply, a control module and a power feedback module; the first power supply is connected with a first input end of the power feedback module, the second power supply is connected with a second input end of the power feedback module through a control module, a feedback end of the power feedback module is connected with a control end of the control module, a first output end of the power feedback module is connected with a first power supply pin of the display driving chip, and a second output end of the power feedback module is connected with a second power supply pin of the display driving chip; the control module is used for adjusting the output voltage of the second power supply according to the feedback control signal input by the power feedback module.

In a second aspect, an embodiment of the present application provides an electronic device, which includes the driving circuit of the display screen of the first aspect.

In a third aspect, a driving method in an embodiment of the present application is applied to a driving circuit of the display screen in the first aspect, and the method includes: detecting total input power corresponding to the first power supply pin and the second power supply pin; obtaining a feedback control signal based on the total input power; and adjusting the output voltage of the second power supply according to the feedback control signal.

In the embodiment of the application, the power feedback module and the control module are added in the driving circuit of the display screen, so that when the first power supply and the second power supply power for the digital logic module in the display driving chip, the control module can adjust the output voltage of the second power supply according to the feedback control signal input by the power feedback module, further adjust the energy ratio of the first power supply and the second power supply to the digital logic module to the optimal ratio, and reduce the overall power consumption of the display driving chip in the power supply process.

Drawings

The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

FIG. 1 is a power supply architecture diagram of a conventional 3power technology;

fig. 2 is one of circuit architecture diagrams of a driving circuit of a display panel according to an embodiment of the present application;

FIG. 3 is a power supply architecture diagram for a 4power technology;

FIG. 4 is a power supply architecture diagram of another 4power technology;

FIG. 5 is a graph of total power of the VDDI circuit + VDDR circuit (i.e., total power showing IO blocks and digital logic) versus VDDR of the DC-DC output for a real project test;

fig. 6 is a second circuit architecture diagram of a driving circuit of a display panel according to an embodiment of the present application;

fig. 7 is a third circuit architecture diagram of a driving circuit of a display panel according to an embodiment of the present application;

fig. 8 is a fourth circuit architecture diagram of a driving circuit of a display panel according to an embodiment of the present application;

fig. 9 is a fifth circuit architecture diagram of a driving circuit of a display panel according to an embodiment of the present application;

fig. 10 is a schematic structural diagram of a power feedback module in a driving circuit of a display panel according to an embodiment of the present application;

fig. 11 is a schematic flow chart of a driving method according to an embodiment of the present application;

fig. 12 is a second flowchart of a driving method according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described clearly below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments that can be derived by one of ordinary skill in the art from the embodiments given herein are intended to be within the scope of the present disclosure.

The terms first, second and the like in the description and in the claims of the present application are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It will be appreciated that the data so used may be interchanged under appropriate circumstances such that embodiments of the application may be practiced in sequences other than those illustrated or described herein, and that the terms "first," "second," and the like are generally used herein in a generic sense and do not limit the number of terms, e.g., the first term can be one or more than one. In addition, "and/or" in the specification and claims means at least one of connected objects, a character "/" generally means that a preceding and succeeding related objects are in an "or" relationship.

Fig. 1 is a power architecture diagram of a conventional Liquid Crystal Display (LCD) Display (i.e., a power architecture diagram of 3power technology). At present, the LCD display screen with the structure is widely applied to the smart phone. For the LCD display screen power supply, the 3power technology refers to three main power supplies for power supply.

As shown in fig. 1, a Display Driver IC (hereinafter, abbreviated as DDIC) mainly includes three parts, namely, a bias driving module, a Display IO module and a digital logic module. The bias driving module is used for controlling the deflection of liquid crystal inside the screen to control the color of the pixel; the display IO module is used for driving actions of various IO ports in the DDIC; the digital logic module is used for driving the internal logic circuit to work so as to achieve the purpose of transmitting display data from the mobile phone CPU to the display screen.

Wherein, AVDD and AVEE are responsible for the bias driving power supply; VDDI is responsible for both the display driver IC internal IO power supply and the digital logic module. 3 of the 3 powers are three inputs, AVDD, AVEE and VDDI, respectively. The power supply scheme of the VDDI circuit is mainly optimized.

In the 3power architecture, the IO block source is shown to require 1.8V power, and the digital logic block requires a lower voltage (typically 1.0-1.3V, which is referred to as VDDR) for power supply. VDDI is a 1.8V power supply provided on the motherboard of the electronic device, so VDDI can directly power the display IO, but needs to be stepped down to VDDR to power the digital logic. The general pressure reduction mode is as follows: the screen module DDIC is internally integrated with an LDO for converting 1.8V into VDDR.

However, according to circuit theory, the structure of the LDO has significant power loss, and the efficiency is only the VDDR voltage value divided by 1.8V. It is assumed that the efficiency is at most 1.1V/1.8V =61.1% for a display panel having a VDDR value of 1.1V. Considering that the current value of VDDR is typically around 75mA, the power loss on the LDO is typically (1.8V-1.1V) × 75ma =52.5mw.

In order to reduce the power consumption generated by the LDO, a 4power technology is developed for display screens. In contrast to the 3-power technology, the 4-power technology alone pulls out the VDDR pin of the display DDIC, allowing a 1.1V power supply to be directly generated on the motherboard of the electronic device to connect to the digital logic module.

However, when the display panel DDIC is powered by the 4power technology, the 1 st and 2 nd power supplies of the 4power supplies (the 1 st, 2 nd, 3 rd and 4 th) supply power to the bias driving modules (i.e. two AVDD and AVEE) in the display driving IC, the 3 rd power supply (i.e. ADDI) supply power to the display IO module in the display driving IC, and the 3 rd power supply also supplies power to the digital logic modules in the display driving IC together with the 4 th power supply (i.e. the newly added VDDR).

In the driving circuit, the electronic device, and the driving method for the display screen provided by the embodiment of the application, the power feedback module and the control module are added in the driving circuit for the display screen, so that when the first power supply and the second power supply power to the digital logic module in the display driving chip, the control module can adjust the output voltage of the second power supply according to the feedback control signal input by the power feedback module, and further adjust the energy ratio input by the first power supply and the second power supply to the digital logic module to the optimal ratio, thereby reducing the overall power consumption of the display driving chip in the power supply process.

The driving circuit, the electronic device, and the driving method of the display screen according to the embodiments of the present application are described in detail below with reference to the accompanying drawings.

An embodiment of the present application provides a driving circuit of a display panel, and as shown in fig. 2, the driving circuit 100 includes: display driver chip 10, first power 11, second power 12, control module 13 and power feedback module 14, wherein:

the display driving chip 10 includes a first power pin 101 and a second power pin 102;

the first power supply 11 is connected with a first input end of a power feedback module 14, the second power supply 12 is connected with a second input end of the power feedback module 14 through a control module 13, a feedback end of the power feedback module 14 is connected with a control end of the control module 13, a first output end of the power feedback module 14 is connected with a first power supply pin 101 of the display driving chip 10, and a second output end of the power feedback module 14 is connected with a second power supply pin 102 of the display driving chip 10;

and the control module 13 is configured to adjust the output voltage of the second power supply 12 according to the feedback control signal input by the power feedback module 14.

In some possible embodiments, the power feedback module 14 is configured to detect a total input power of the first power pin 101 and the second power pin 102, and output a feedback control signal based on the total input power; and the control module 13 is configured to adjust the output voltage of the second power supply 12 according to the feedback control signal.

In some possible embodiments, the display driver chip 10 further includes a display IO module 103 and a digital logic module 104, the first power supply 11 can be conducted with the first power pin 101 through the power feedback module 14 to supply power to the display IO module 103, the first power supply 11 can be conducted with the second power pin 102 through the power feedback module 14 to supply power to the digital logic module 104, and the second power supply 12 can be conducted with the second power pin 102 through the power feedback module 14 to supply power to the digital logic module 104.

In some possible embodiments, the present application provides two power supply paths for the display driver chip 10 to respectively supply power to the display IO module 103 and the digital logic module 104. As shown in fig. 2, the path for supplying power to the display IO block 103 may be referred to as a VDDI path, and the path for supplying power to the digital logic block 104 may be referred to as a VDDR path.

IN one possible example, for the VDDI path, the output voltage VDDI _ IN of the first power supply is sampled and output by the power feedback module 14, and then the output voltage VDDI _ OUT of the power feedback module 14 is input to the display IO module 103 through the first power supply pin 101 to supply power to the display IO module 103. Meanwhile, the output voltage VDDI _ OUT is also input to the digital logic module 104 through the first power pin 101.

In one possible example, for the VDDR path, the output voltage VPH of the second power supply is sampled and output by the power feedback block 14, and then the output voltage VDDR _ OUT of the power feedback block 14 is input to the digital logic block 104 through the second power supply pin 102 to power the digital logic block 104.

IN other words, the main function of the power feedback module 14 is to detect the total power of the VDDR _ SP and VDDI _ IN lanes.

In some possible embodiments, the present application may also provide two other power supply paths for the display driver chip 10 to simultaneously supply power to the bias driver modules in the display driver chip 10.

In one possible example, as shown in fig. 3, the driving circuit 100 further includes: a third power supply 15 and a fourth power supply 16; the display driving chip 10 further includes: a third power supply pin 105, a fourth power supply pin 106, and a bias driving module 107, wherein: the third power supply 15 is connected to the third power pin 105 to supply power to the bias driving module 107, and the fourth power supply 16 is connected to the fourth power pin 106 to supply power to the bias driving module 107. Illustratively, as shown in fig. 3, the paths for supplying power to the bias driving module 107 are an AVDD path and an AVE path, the input voltage AVDD of the third power supply 15 is input to the bias driving module 107 through the third power supply pin 105, and the input voltage AVEE of the fourth power supply 16 is input to the bias driving module 107 through the fourth power supply pin 106.

It should be noted that the bias driving module 107 is used for controlling the deflection of the liquid crystal inside the screen to control the color of the pixel; the display IO module 103 is configured to drive various IO ports inside the DDIC; the digital logic module 104 is used to drive the internal logic circuit to operate so as to achieve the purpose of transmitting the display data from the CPU of the electronic device to the display screen.

In the driving circuit of the display screen provided by the embodiment of the application, the power feedback module and the control module are added in the driving circuit of the display screen, so that when the first power supply and the second power supply power for the digital logic module in the display driving chip, the control module can adjust the output voltage of the second power supply according to the feedback control signal input by the power feedback module, and further adjust the energy ratio input by the first power supply and the second power supply to the digital logic module to the optimal ratio, thereby reducing the overall power consumption of the display driving chip in the power supply process.

In the related art, in order to reduce the power consumption generated by the LDO in the architecture diagram shown in fig. 1, fig. 4 shows a power supply architecture diagram of one possible 4power technology, 4 of the 4power being referred to as AVDD, AVEE, VDDI, and VDDR, respectively.

Compared to the 3power architecture shown in fig. 1 and the 4power architecture shown in fig. 4, the following modifications are made:

(1) The VDDR pin of the DDIC of the display screen is pulled out independently, so that a 1.1V power supply is directly generated on a mainboard of the electronic equipment and connected to digital logic;

(2) The method for generating the 1.1V power supply on the whole machine is a DC-DC voltage reduction scheme: the main power supply VPH of the electronic device is converted to 1.1V by an additional DC-DC circuit. In circuit theory, DC-DC is much more efficient than LDO, up to 90% more, so VDDR is now generated by the more efficient DC-DC rather than the less efficient LDO.

(3) However, it should be noted that the DDIC of the 4power scheme still retains the LDO internally, i.e. the path of VDDI1.8V going through the LDO to VDDR is retained, which aims to: (1) if the external VDDR is abnormal, allowing the digital logic module to get power from the LDO circuit so as to maintain the normal work of the display screen; (2) allowing vendors to continue to design with a 3power architecture.

Furthermore, as shown in fig. 4, the energy of the digital logic block can be sourced from two paths, one of which is the part where VPH is converted to VDDR by DC-DC; and the second path is a part for converting VDDI into VDDR through an internal LDO of the chip. Since DC-DC is much more efficient than LDO, path one has less loss than path two, and it is desirable to design all the energy to go from path one. However, in the digital logic power-up, the energy ratio of the first path and the second path is configured according to the VDDR value of the DC-DC output.

Fig. 5 shows the VDDI + VDDR total power (i.e., the total power of the display IO block and the digital logic) versus VDDR change for the DC-DC output for the actual project test. As shown in fig. 5, a VDDR value may be found to minimize the total power of the display IO module source and the digital logic module, recording the VDDR voltage value as VDDR _ NEED at this time.

Specifically, referring to fig. 5, in the stage (1) of fig. 5, when VDDR of the DCDC output is gradually increased to be close to VDDR _ NEED, the energy occupation ratio provided by the first path is larger and larger, and the energy occupation ratio provided by the second path is smaller and smaller, that is, the power loss generated by the LDO is smaller and smaller, and the total power consumption is smaller; during stage (2) of fig. 5, when VDDR of the DCDC output gradually exceeds VDDR _ NEED and continues to increase, the energy share provided by path two increases rapidly (because path one is turned off rapidly to prevent the digital logic from being damaged by excessive VDDR generated by path one, which may cause over-voltage damage), and the energy share provided by path one decreases rapidly, i.e., the LDO generates more and more power consumption. Thus, the total energy actually consumed by the digital logic module has a trend as shown in fig. 5.

Thus, although the 4power scheme shown in fig. 4 can theoretically bring about a gain, in an actual circuit, due to various factors (such as deviation between the design value itself and VDDR _ NEED, voltage drop caused by PCB trace resistance, device uniformity, and the like), the VDDR value is often difficult to accurately fall on the optimal voltage position, and the 4power scheme cannot achieve the expected effect while the additional DC-DC cost is increased.

The embodiment of the application provides a strategy for automatically searching the lowest power consumption point aiming at the 4power scheme of the display screen, and aims to maximize the power consumption, the temperature rise and the time gain of the 4power scheme by a method of combining software and hardware.

In view of the above problems of the VDDR open-loop control method, the present invention intends to introduce a method of calculating the VDDI + VDDR path power (i.e. calculating the total power of the display IO module and the digital logic circuit), and adjust the output value of the DCDC according to the real-time feedback result of the total power, so as to implement a closed-loop control method to maximize the benefit of the 4power scheme.

In some possible embodiments, the control module 13 is an independent module, and the output voltage of the second power supply can be adjusted independently, which is not limited in this application.

In some possible embodiments, as shown in fig. 6 in combination with fig. 3, the driving circuit 100 may further include: a first voltage reduction module 17; the first voltage reduction module 17 is connected between the second power supply and the control module 13.

The control module 13 is specifically configured to adjust the output voltage output by the second power supply 12 and stepped down by the first step-down module 17 according to the feedback control signal.

Illustratively, the first voltage-reducing module 17 is configured to reduce the output voltage VPH of the second power supply 12 and input the reduced input voltage VDDR _ SR to the power feedback module 14. Namely, VDDR _ SR is the VDDR sampling signal output by VPH through the first voltage dropping module 17 for VDDR voltage acquisition.

In some possible embodiments, the control module 13 includes a voltage reduction unit and a control unit; wherein: the output end of the voltage reduction unit is connected with the input end of the control unit; the voltage reduction unit is used for carrying out voltage reduction processing on the input voltage of the second power supply; and the control unit is used for adjusting the output voltage output by the second power supply and subjected to voltage reduction by the voltage reduction unit according to the feedback control signal.

It can be understood that the control function of the control module can be integrated into the first voltage-reducing module 17, so that the first voltage-reducing module 17 can be integrated with the voltage-reducing function and the control function at the same time, thereby flexibly adjusting the output voltage of the second power supply.

In some possible embodiments, with reference to fig. 6, as shown in fig. 7, the display driving chip 10 may further include: a second voltage reduction module 108; one end of the second voltage reduction module 108 is connected to the first power pin 101; the other end of the second voltage dropping module 108 is connected to the digital logic module 104.

For example, as shown IN fig. 7, the input voltage VDDI _ IN of the first power supply 11 is input to the second voltage-reducing module 108 through the output voltage VDDI _ OUT output by the power feedback module 14, so that the second voltage-reducing module 108 reduces the output voltage VDDI _ OUT, and inputs the reduced output voltage VDDI _ OUT to the digital logic module 104 to supply power to the digital logic module 104.

Referring to fig. 7, VDDI _ IN fig. 7 is the VDDI input of power feedback module 14; the VDDR _ SP is a VDDR sampling signal which is converted and output by the VPH through the first voltage reduction module 17 and is used for collecting VDDR voltage; VDDI _ OUT and VDDR _ OUT are the outputs of VDDI _ IN and VDDR _ SP, respectively, after passing through the internal sampling resistors of the power feedback module 14, as the actual power supply for the screen module DDIC. In this way, the power feedback module 14 can sample the total power of the VDDR path and the VDDI path in real time, and then feed back and adjust the actual output of VDDR, so as to keep the total power consumption at a lower level.

For example, as shown in fig. 8, the second buck module 108 may be the LDO module in fig. 4.

For example, as shown in fig. 8, the first voltage-reducing module 107 may be a DC-DC circuit in fig. 4.

In some possible embodiments, as shown in fig. 9, the first buck block 17 shown in fig. 9 is a conventional buck circuit for buck VPH to VDDR SP. It should be noted that the circuit configuration diagram of the first buck module 17 shown in fig. 9 is only an example, and in practical applications, other configurations of the first buck module 17 capable of realizing the buck of VPH to VDDR _ SP may be applied to the present application.

In one possible example, the first voltage reduction module 17 includes: buck circuit input capacitance 600, buck circuit control upper tube 610, buck circuit control lower tube 620, first sampling feedback resistance 630, second sampling feedback resistance 640, power inductance 650 in the buck circuit, output capacitance 660 of the buck circuit, error amplifier 800, sawtooth generator 810, comparator 820, PWM logic controller 830, driver 840, where:

the buck circuit input capacitor 600 is used for stabilizing the amplitude of the input power supply VPH;

the buck circuit controls the upper tube 610, which is used for charging the power inductor 650 in the buck circuit with VPH current through the tube when the MOS tube is turned on, and the voltage value of VDDR _ SP rises;

the buck circuit controls the lower tube 620, and when the buck circuit controls the lower tube 620 to be conducted, the buck circuit controls the upper tube 610 to be always closed, at this time, VPH cannot charge the inductor, the inductor current decreases, and the voltage value of VDDR _ SP decreases. The buck circuit controlled top tube 610 and buck circuit controlled down tube 620 switch on-off-on-off rapidly to maintain VDDR SP at a steady state value dynamically;

the first sampling feedback resistor 630 and the second sampling feedback resistor 640 make the input voltage of the "-" terminal of the error amplifier 800 be set to be VDDR _ SP-R _ F1-R _ F2-PGND through the path of VDDR _ SP-R _ F1-PGND

A power inductor 650 in the buck circuit, which can output VDDR _ SP in cooperation with the buck circuit upper control tube 610 and the buck circuit lower control tube 620;

the output capacitor 660 of the buck circuit is used for stabilizing the amplitude of the output power supply;

an error amplifier 800 for correlating the value of the DC-DC internal reference voltage V _ REF with the voltage at R _ F2 (i.e., the voltage at R _ F2)

) And (5) amplifying the difference. When the DC-DC circuit reaches steady state, the two voltage values are equal, namely

Thus is provided with

A sawtooth generator 810 generating a sawtooth waveform;

a comparator 820 for comparing two input terminals thereof (voltage magnitude of "+" terminal and "-" terminal), and outputting high level when the "+" terminal voltage is greater than the "-" terminal voltage; when the + terminal voltage is less than the-terminal voltage, the comparator outputs a low level. Error amplifier 800, sawtooth generator 810, and comparator 820 collectively function as: when the value of VDDR _ SP is smaller, so that the voltage at the "-" terminal R _ F1 of the error amplifier 800 is smaller than the voltage at the "+" terminal V _ REF, the error amplifier outputs a positive voltage, which is compared with the sawtooth wave comparator, and the value of the positive voltage output by the error amplifier is greater than the average voltage of the sawtooth wave, so that the comparator outputs more high levels, which finally act on the buck circuit control upper tube 610 and the buck circuit control lower tube 620, so that the buck circuit control upper tube 610 has a longer conduction time, the buck circuit control lower tube 620 has a shorter conduction time, and further the value of VDDR _ SP becomes larger; when the VDDR _ SP value is larger, the voltage at the "-" terminal R _ F1 of the error amplifier 800 is larger than the voltage at the "+" terminal V _ REF, the error amplifier outputs a negative voltage, which is compared with the sawtooth comparator, and the negative voltage value output by the error amplifier is smaller than the average voltage of the sawtooth wave, so that the comparator outputs more low levels, which finally acts on the buck circuit control upper tube 610 and the buck circuit control lower tube 620, so that the buck circuit control upper tube 610 has a shorter conduction time, the buck circuit control lower tube 620 has a longer conduction time, and the VDDR _ SP value is reduced. This process causes the DC-DC to reach the same result at steady state as the voltages at the "+" and "-" terminals of the error amplifier 800. I.e., equation one above.

The PWM logic controller 830 and the driver 840 both amplify the signal output by the comparator 820, so as to drive the buck circuit upper control tube 610 and the buck circuit lower control tube 620.

In addition, further, the formula two is used for the above mentioned output value of VDDR

In the DC-DC of the conventional 4power scheme, the V _ REF value is fixed. In the present application, the value of V _ REF is variable and is adjusted according to the result of the power detection and the control module.

In some possible embodiments, as shown in fig. 10, the power feedback module 14 includes: a first power detection unit 141, a second power detection unit 142, an adder 143, and a logic processing unit 144, wherein:

a first power detection unit 141 connected to the first power supply 11, for detecting the input power of the first power supply pin 101;

a second power detection unit 142, connected to the output end of the control module 13, for detecting the input power of the second power pin 102;

the logic processing unit 144 is configured to obtain a feedback control signal based on the total input power corresponding to the first power pin 101 and the second power pin 102;

a first input end of the adder 143 is connected to the first power detecting unit 141, a second input end of the adder is connected to the second power detecting unit 142, and an output end of the adder 143 is connected to a first end of the logic processing unit 144;

a second end of the logic processing unit 144 is connected to the control module 13.

Illustratively, the adder is configured to add P _ VDDR (i.e., the input power of the first power pin 101) and P _ VDDI (i.e., the input power of the second power pin 102) to obtain the total power of the VDDR path and the VDDI path, i.e., the total power required by the display IO portion and the digital logic portion in the display module.

Illustratively, the logic processing unit 144 may be considered to have a control algorithm integrated therein.

In one example, the control algorithm may employ a "perturb-and-observe method," as shown in FIG. 11. The specific implementation mode is as follows: VDDR is firstly changed according to a certain direction, for example, VDDR can be firstly increased, the total power P (k + 1) of a VDDR + VDDI circuit at the next moment is collected and compared with the current moment P (k), if P (k + 1) is more than or equal to P (k), the total power consumption is increased due to the increase of VDDR, and then VDDR is reduced; if P (k + 1) ≦ P (k), indicating that an increase in VDDR will reduce power consumption, then VDDR should continue to increase. Thus, by calculation of the logic processing unit, a command (i.e., the above-mentioned feedback control signal) of the VDDR changing direction can be output.

In some possible embodiments, as shown in fig. 9, the control module 13 comprises: a regulator 131 and a low-pass filter 132; the input end of the voltage stabilizer 131 is connected with the feedback end of the power feedback module 14; the output of the regulator 131 is connected to one end 132 of the low pass filter; the other end of the low pass filter 132 is connected to a second input of the power feedback module 14.

Illustratively, the voltage regulator 131 is configured to adjust the output voltage of the second power supply according to the feedback control signal.

Illustratively, the low pass filter 132 described above is used to further stabilize the voltage. For example, a stable voltage may be used as the reference source V _ REF.

For example, referring to fig. 9, based on the output result of the logic processing unit 144, if VDDR is increased to reduce the total power consumption, the voltage regulator 131 and the low pass filter 132 are controlled to increase V _ REF, and VDDR is controlled to increase; if the total power consumption is reduced by reducing VDDR according to the output result of the logic processing unit 144, the voltage regulator 131 and the low pass filter 132 are controlled to reduce V _ REF, and thus VDDR is controlled to be reduced. Finally, a dynamic stabilization is achieved around the optimum point VDDR _ NEED.

In some possible embodiments, as shown in fig. 9, the first power detection unit 141 includes: a first sampling resistor 1411, a first amplifier 1412, a second amplifier 1413, a first analog-to-digital converter 1414, a second analog-to-digital converter 1415, and a first multiplier 1416, wherein:

a first terminal of the first sampling resistor 1411 is connected to a first input terminal of the first amplifier 1412 and a first input terminal of the second amplifier 1413, and a second terminal of the first sampling resistor 1411 is connected to the first power source 11 and a second input terminal of the second amplifier 1413;

the output of the first amplifier 1412 is connected to a first analog-to-digital converter 1414;

the output end of the second amplifier 1413 is connected with a second analog-to-digital converter 1415;

a first input of the first multiplier 1416 is connected to the first adc 1414, a second input of the first multiplier 1416 is connected to the second adc 1415, and an output of the first multiplier 1416 is connected to a first input of the adder 143.

For example, the first sampling resistor 1411 can be considered as a VDDI _ IN sampling resistor VDDI _ SP current, which generates a voltage drop across the resistor, and the voltage drop is used as the input of the first amplifier 1412 (i.e., amp4 IN fig. 9) and the second amplifier 1413 (i.e., amp3 IN fig. 9). The input signal of the second amplifier Amp3 is the difference between VDDI _ OUT and GND voltage, i.e. the voltage value of VDDI _ OUT, because the resistance of the sampling resistor 110 is very small and the voltage drop is very small, VDDI _ OUT is approximately equal to VDDI _ IN. The input signal of the first amplifier Amp4 is the voltage drop value caused by the second sampling resistor 1421, and the amplifier is used for amplifying the voltage drop value. The second analog-to-digital converter 1415 (i.e., ADC3 in fig. 9) is configured to convert the analog signal output by the second amplifier Amp3 into a digital signal recognizable by the processor, where the digital signal is a voltage drop generated when VDDI passes through the first sampling resistor 1411, and a current in the VDDI path can be calculated as I _ VDDI according to the voltage drop and a resistance value of the first sampling resistor 1411. The first analog-to-digital converter 1414 (i.e., ADC4 in fig. 9) is used for converting the analog signal output by the first amplifier Amp4 into a digital signal recognizable by the processor, wherein the digital signal can represent the voltage value of VDDI _ OUT, which is denoted as U _ VDDI. The first multiplier 1416 (i.e., mux2 in fig. 9) is used to multiply U _ VDDI and I _ VDDI to obtain the real-time power of VDDI path P _ VDDI.

In some possible embodiments, as shown in fig. 9, the second power detection unit 142 includes: a second sampling resistor 1421, a third amplifier 1422, a fourth amplifier 1423, a third adc 1424, a fourth adc 1425, and a second multiplier 1426, where:

a first end of the second sampling resistor 1421 is connected to a first input end of the third amplifier 1422 and a first input end of the fourth amplifier 1424, and a second end of the second sampling resistor 1421 is connected to an output end of the control module 13 and a second input end of the fourth amplifier 1421;

the output terminal of the third amplifier 1422 is connected to the third analog-to-digital converter 1424;

the output terminal of the fourth amplifier 1423 is connected to the fourth analog-to-digital converter 1425;

a first input of the second multiplier 1426 is connected to the third analog-to-digital converter 1424, a second input of the second multiplier 1426 is connected to the fourth analog-to-digital converter 1425, and an output of the second multiplier 1426 is connected to a second input of the adder 143.

For example, the second sampling resistor 1421 can be regarded as the VDDR _ IN sampling resistor VDDR _ IN, which is VDDR _ IN current, passing through the resistor, and generating a voltage drop thereon, which is used as the input of the third amplifier 1422 (i.e., amp1 IN fig. 9) and the fourth amplifier 1423 (i.e., amp2 IN fig. 9). The input signal of the fourth amplifier Amp2 is the difference between VDDR _ OUT and GND voltage, i.e. the voltage value of VDDR _ OUT, because the resistance of the second sampling resistor 1421 is very small and the voltage drop is very small, VDDR _ OUT is approximately equal to VDDR _ SP. The input signal of the third amplifier Amp1 is the voltage drop value caused by the second sampling resistor 1421, and the amplifier is used for amplifying the voltage drop value. The third analog-to-Digital Converter 1424 (ADC) (i.e., ADC1 in fig. 9) is used for converting the analog signal outputted from the third amplifier 1422 into a Digital signal recognizable by the processor, where the Digital signal can represent the voltage value of VDDR _ OUT, which is denoted as U _ VDDR. The fourth analog-to-digital converter 1425 (i.e., ADC2 in fig. 9) is configured to convert the analog signal output by the fourth amplifier 1423 into a digital signal recognizable by the processor, where the digital signal is a voltage drop generated when VDDR passes through the second sampling resistor 1421, and a current of the VDDR path can be calculated as I _ VDDR according to the voltage drop and a resistance value of the second sampling resistor 1421. The second multiplier 1426 (i.e., mux1 in fig. 9) is used to multiply U _ VDDR and I _ VDDR to obtain the real-time power of the VDDR path as P _ VDDR.

In addition, in the present application, it should be noted that the following points are required to be noted:

(1) the values of the first sampling resistor 1411 and the second sampling resistor 1421 (i.e., R _ S1 and R _ S2 in fig. 9) are selected according to the following 2 points: firstly, the voltage drop generated on the resistor is very small, and the voltage drop needs to be sampled by the ADC, otherwise, the sampling precision is too poor; secondly, the power consumption of the resistor cannot be too high, otherwise, the purpose of reducing the power consumption of the whole circuit cannot be achieved. For example, when the total power consumption is the lowest, the approximate current ranges of VDDR and VDDI are about 50mA and 10mA respectively, so R _ S1 can be selected to be 0.5 Ω, and R _ S2 can be 2 Ω, then the voltage on the resistor R _ S1 is roughly calculated to be 25mV and the power is 1.25mW; the voltage on the R _ S2 resistor is 20mV, and the power is 0.2mW. The two requirements can be met. The selection of the actual resistance value may be balanced between sampling accuracy and power consumption benefits.

(2) Amp is an operational amplifier, wherein the input of Amp2 and Amp3 is the voltage value on the sampling resistor, and the amplitude is small, so that the proper amplification ratio can be set to amplify the small signal amplitude. In addition, the four operational amplifiers can increase the input impedance of the ADC, and can isolate the front circuit from the rear circuit.

(3) The ADC is an analog-to-digital converter, and when selecting the ADC, attention needs to be paid to selection from the aspects of power consumption, resolution, sampling rate and the like. The resolution and the sampling rate are strongly related to the power consumption of the ADC, and for this application, the resolution of 10-12 bits is appropriate, and the sampling rate is selected from the ADC of KSPS (i.e., klo Samples per Second). In addition, on the framework of the ADC, the power consumption level of the successive approximation type ADC is low, the single-channel power consumption can be controlled to be 250 mu W level under the KSPS sampling rate, and the total power consumption of four ADC channels can be controlled to be 1mW.

It should be noted that the added modules do not introduce excessive additional power consumption.

In summary, the embodiment of the present application provides a closed-loop control method for detecting the total power consumption of the VDDI + VDDR paths (i.e., the I/O power supply and the digital logic module), which controls the VDDR value in real time, so that the benefit of reducing the power consumption by 4-power is maximized and stabilized. The specific beneficial effects comprise the following items:

(1) The temperature rise, the time length and the power consumption benefit of the 4power scheme of the display screen are improved;

(2) By introducing a closed-loop control method, the following design and actual deviation can be effectively optimally controlled:

(1) deviation of a design value of the whole VDDR and an optimal VDDR value;

(2) deviation between optimal VDDR values at different frame rates;

(3) the consistency of each machine component causes the deviation of the optimal value of VDDR (the VDDR consistency is caused by slight differences of the display module, a DCDC power supply, PCB wiring impedance and the like);

(3) When the VDDR is not at the optimal value, the leakage exists between the DC-DC (namely the first voltage reduction module) and the LDO (namely the second voltage reduction module), which brings the risk to the reliability of the circuit, and the leakage risk can be reduced after the control is introduced;

(4) Compared with the conventional 4power scheme, the method has the advantages that only modules such as an operational amplifier, an ADC (analog to digital converter), a logic control module and the like are additionally introduced, so that the cost is controllable;

(5) The scheme can be integrated, the whole scheme frame can be integrated into one chip, and the display module power management chip can be designed according to the scheme.

The embodiment of the application provides an electronic device, which comprises a display screen and a driving circuit of the display screen.

The electronic device provided by the embodiment of the application can be a mobile electronic device and can also be a non-mobile electronic device. By way of example, the mobile electronic device may be a mobile phone, a tablet computer, a notebook computer, a palm top computer, a vehicle-mounted electronic device, a wearable device, an ultra-mobile personal computer (UMPC), a netbook or a Personal Digital Assistant (PDA), and the like, and the non-mobile electronic device may be a server, a Network Attached Storage (NAS), a Personal Computer (PC), a Television (TV), a teller machine or a self-service machine, and the like, and the embodiments of the present application are not particularly limited.

In combination with the driving circuit provided above, an embodiment of the present application provides a driving method, as shown in fig. 12, the driving method provided by the embodiment of the present application includes the following steps:

step 201: and detecting the total input power corresponding to the first power supply pin and the second power supply pin.

Step 202: based on the total input power, a feedback control signal is derived.

Step 203: and adjusting the output voltage of the second power supply according to the feedback control signal.

Illustratively, the feedback control signal is used for indicating the adjustment trend of the output voltage of the second power supply. For example, an increase in the voltage output by the second power source to the power feedback module is indicated, or a decrease in the voltage output by the second power source to the power feedback module is indicated.

Illustratively, VDDR is changed according to a certain direction, for example, VDDR may be increased first, the total power P (k + 1) of the VDDR + VDDI path at the next time is collected, and compared with the current time P (k), if P (k + 1) is greater than or equal to P (k), it is indicated that the increase of VDDR increases the total power consumption, and VDDR should be decreased; if P (k + 1) ≦ P (k), indicating that an increase in VDDR will reduce power consumption, then VDDR should continue to increase. Thus, by calculation of the logic processing unit, a command (i.e., the above-mentioned feedback control signal) of the VDDR changing direction can be output.

In the driving method provided in the embodiment of the application, when the first power supply and the second power supply in the driving circuit supply power to the digital logic module in the display driving chip, the power feedback module in the driving circuit may detect total input power of the first power supply input to the first power supply pin of the display driving chip and the second power supply input to the second power supply pin of the display driving chip, and then output a feedback control signal to the control module based on the total input power, so that the control module can adjust an output voltage of the second power supply based on the feedback control signal, and further adjust an energy ratio of the first power supply and the second power supply input to the digital logic module to an optimal ratio, thereby reducing overall power consumption of the display driving chip in a power supply process.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an illustrative embodiment," "an example," "a specific example," or "some examples" or the like mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

While embodiments of the invention have been shown and described, it will be understood by those of ordinary skill in the art that: various changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A driving circuit of a display panel, the driving circuit comprising: the display driving circuit comprises a display driving chip, a first power supply, a second power supply, a control module and a power feedback module;

the first power supply is connected with a first input end of the power feedback module, the second power supply is connected with a second input end of the power feedback module through a control module, a feedback end of the power feedback module is connected with a control end of the control module, a first output end of the power feedback module is connected with a first power supply pin of the display driving chip, and a second output end of the power feedback module is connected with a second power supply pin of the display driving chip;

the control module is used for adjusting the output voltage of the second power supply according to a feedback control signal input by the power feedback module;

the power feedback module includes: the device comprises a first power detection unit, a second power detection unit, an adder and a logic processing unit, wherein:

the first power detection unit is connected with the first power supply and used for detecting the input power corresponding to the first power supply pin;

the second power detection unit is connected with the output end of the control module and is used for detecting the input power corresponding to the second power pin;

the logic processing unit is configured to obtain the feedback control signal based on total input power corresponding to the first power pin and the second power pin;

a first input end of the adder is connected with the first power detection unit, a second input end of the adder is connected with the second power detection unit, and an output end of the adder is connected with a first end of the logic processing unit;

and the second end of the logic processing unit is connected with the control module.

2. The driving circuit according to claim 1, further comprising: a first voltage reduction module; the first voltage reduction module is connected between the second power supply and the control module.

3. The driving circuit according to claim 1, wherein the control module comprises a voltage reduction unit and a control unit;

the output end of the voltage reduction unit is connected with the input end of the control unit;

the voltage reduction unit is used for carrying out voltage reduction processing on the input voltage of the second power supply;

and the control unit is used for adjusting the output voltage output by the second power supply and reduced by the voltage reduction unit according to the feedback control signal.

4. The drive circuit according to claim 1 or 3, wherein the control module comprises: a voltage regulator and a low-pass filter;

the input end of the voltage stabilizer is connected with the feedback end of the power feedback module;

the output end of the voltage stabilizer is connected with one end of the low-pass filter;

and the other end of the low-pass filter is connected with a second input end of the power feedback module.

5. The driving circuit according to claim 1, wherein the display driving chip includes a display IO module and a digital logic module, the first power supply can be conducted with the first power pin through the power feedback module to supply power to the display IO module, the first power supply can be conducted with the second power pin through the power feedback module to supply power to the digital logic module, and the second power supply can be conducted with the second power pin through the power feedback module to supply power to the digital logic module.

6. The drive circuit according to claim 1, wherein the first power detection unit includes: the digital-to-analog converter comprises a first sampling resistor, a first amplifier, a second amplifier, a first analog-to-digital converter, a second analog-to-digital converter and a first multiplier;

a first end of the first sampling resistor is connected with a first input end of the first amplifier and a first input end of the second amplifier, and a second end of the first sampling resistor is connected with the first power supply and a second input end of the second amplifier;

the output end of the first amplifier is connected with the first analog-to-digital converter;

the output end of the second amplifier is connected with the second analog-to-digital converter;

the first input end of the first multiplier is connected with the first analog-to-digital converter, the second input end of the first multiplier is connected with the second analog-to-digital converter, and the output end of the first multiplier is connected with the first input end of the adder.

7. The drive circuit according to claim 1, wherein the second power detection unit includes: the second sampling resistor, the third amplifier, the fourth amplifier, the third analog-to-digital converter, the fourth analog-to-digital converter and the second multiplier;

a first end of the second sampling resistor is connected with a first input end of the third amplifier and a first input end of the fourth amplifier, and a second end of the second sampling resistor is connected with an output end of the control module and a second input end of the fourth amplifier;

the output end of the third amplifier is connected with the third analog-to-digital converter;

the output end of the fourth amplifier is connected with the fourth analog-to-digital converter;

the first input end of the second multiplier is connected with the third analog-to-digital converter, the second input end of the second multiplier is connected with the fourth analog-to-digital converter, and the output end of the second multiplier is connected with the second input end of the adder.

8. An electronic device characterized by comprising a display panel and a driving circuit of the display panel of any one of claims 1 to 7.

9. A driving method applied to a driving circuit of the display panel according to any one of claims 1 to 7, the method comprising:

detecting total input power corresponding to the first power supply pin and the second power supply pin;

obtaining a feedback control signal based on the total input power;

and adjusting the output voltage of the second power supply according to the feedback control signal.