CN114201941A

CN114201941A - Chip performance verification method and device, electronic equipment and storage medium

Info

Publication number: CN114201941A
Application number: CN202111449083.9A
Authority: CN
Inventors: 鄢其力
Original assignee: Haiguang Information Technology Co Ltd
Current assignee: Haiguang Information Technology Co Ltd
Priority date: 2021-11-30
Filing date: 2021-11-30
Publication date: 2022-03-18

Abstract

The embodiment of the invention discloses a chip performance verification method and device, electronic equipment and a storage medium, relates to the field of electronic design automation, and can effectively improve the chip performance verification efficiency. The method comprises the following steps: receiving model state information from a preset model environment of a chip to be verified through a performance statistics management platform; the performance statistics management platform is communicated with the preset model environment through a preset interface, and the preset model environment comprises at least one of the following: a function verification environment, a hardware simulation environment and a performance model environment; triggering the performance statistics management platform to generate a verification control signal according to the model state information; and under the control of the verification control signal, receiving the model operation data of the chip to be verified from the preset model environment through a preset performance statistic component, and performing performance statistics on the model operation data to obtain a corresponding performance statistic result. The invention is suitable for chip performance verification.

Description

Chip performance verification method and device, electronic equipment and storage medium

Technical Field

The invention relates to the field of electronic design automation, in particular to a chip performance verification method and device, electronic equipment and a storage medium.

Background

In the field of integrated circuit technology, before a chip is delivered to a foundry for manufacturing, a series of functional verification and performance verification are usually performed to ensure that the manufactured chip can meet design requirements. The functional verification mainly refers to finding out functional bugs and defects in the design through software simulation or hardware simulation before the chip is manufactured. The performance verification or performance evaluation mainly refers to evaluating whether the performance of a chip reaches an expected value through software simulation or hardware simulation before the chip is manufactured.

In the field of integrated circuit Verification, there is a well-established and Universal Methodology for functional Verification, such as UVM (Universal Verification Methodology) which is widely used in functional Verification. There is no industry-consistent standard or methodology for performance verification or performance assessment.

Currently, the performance verification method commonly used in the industry generally evaluates whether the performance is expected by analyzing the waveform. The method comprises the following steps: some test cases with large traffic are operated in a software simulation or hardware simulation mode, and the generated waveforms are sent to a design engineer or an architecture engineer for analysis. The design engineer or the architecture engineer needs to open waveforms in the waveform viewer, pull the performance-related signals to the waveform display window, perform some logic operations on the signals, such as logically and the Valid signal and the Clock signal, select a period of time, and count the number of rising edges or falling edges of the signal in the period of time, thereby achieving the purpose of calculating performance. However, this method is inefficient in performance analysis due to the complicated steps. This process may last several hours if multiple performance metrics for multiple modules need to be calculated. The time required for analyzing the performance index in various application scenarios is also multiplied.

Aiming at the problem of low performance verification efficiency of an integrated circuit chip, no effective solution is available in the related technology.

Disclosure of Invention

In view of this, embodiments of the present invention provide a chip performance verification method and apparatus, an electronic device, and a computer-readable storage medium, which can effectively improve chip performance verification efficiency.

In a first aspect, an embodiment of the present invention provides a chip performance verification method, where the method includes: receiving model state information from a preset model environment of a chip to be verified through a performance statistics management platform; the performance statistics management platform is communicated with the preset model environment through a preset interface, and the preset model environment comprises at least one of the following: a function verification environment, a hardware simulation environment and a performance model environment; triggering the performance statistics management platform to generate a verification control signal according to the model state information; under the control of the verification control signal, receiving model operation data of the chip to be verified from the preset model environment through a preset performance statistics component, and performing performance statistics on the model operation data to obtain a corresponding performance statistics result, wherein a programming language based on the performance statistics management platform is compatible with a programming language based on the preset model environment and a programming language based on the performance statistics component.

Optionally, the triggering the performance statistics management platform to generate a verification control signal according to the model state information includes: triggering the performance statistics management platform to generate a statistics starting signal according to a running starting signal in the model state information; or triggering the performance statistics management platform to generate a stop statistics signal according to the stop running signal in the model state information.

Optionally, before receiving the model operation data of the chip to be verified from the preset model environment through a preset performance statistics component under the control of the verification control signal, the method further includes: adding the pointer of the performance statistic component into a component pointer index preset by the performance statistic management platform or into a component pointer index preset by a lower sub-platform of the performance statistic management platform according to a preset component membership relation; and/or adding the pointer of each lower-level sub-platform into a corresponding sub-platform pointer index preset by an upper-level sub-platform according to a preset platform membership relationship, or adding the pointer of each lower-level sub-platform into a sub-platform pointer index preset by the performance statistics management platform.

Optionally, under the control of the verification control signal, receiving, by a preset performance statistics component, the model operation data of the chip to be verified from the preset model environment, and performing performance statistics on the model operation data includes: the performance statistics management platform issues the verification control signal to each performance statistics component, wherein the performance statistics components are directly under the management of the performance statistics management platform or under the management of a lower-level sub-platform of the performance statistics management platform; each performance statistic component receives the corresponding model operation data according to the verification control signal; and each performance statistic component carries out performance statistics on the model operation data according to the respective statistic attribute.

Optionally, the issuing, by the performance statistics management platform, the verification control signal to each of the performance statistics components includes: if the performance statistics component is directly under the management of the performance statistics management platform, the performance management platform acquires a pointer of the performance statistics component from a component pointer index preset by the performance management platform, and respectively issues the verification control signals to the performance statistics component according to the pointer of the performance statistics component; if the performance statistics component is under the management of a lower-level sub-platform of the performance statistics management platform, the performance management platform acquires a pointer of a first sub-platform where the performance statistics component is located from a sub-platform pointer index preset by the performance management platform; and obtaining the first sub-platform according to the pointer of the first sub-platform, obtaining the pointer of the performance statistics component from a component pointer index preset by the first sub-platform, and respectively issuing the verification control signals to the performance statistics component according to the pointer of the performance statistics component.

Optionally, the receiving, by each of the performance statistics assemblies according to the verification control signal, the corresponding model operation data includes: each performance statistic component determines the starting or ending of each statistic task according to the verification control signal; responding to the starting of the statistical task, and respectively receiving the model operation data corresponding to each performance statistical component; and responding to the end of the statistic task, and stopping receiving the model operation data corresponding to each performance statistic component respectively.

Optionally, the performing, by each performance statistics component, performance statistics on the model operation data according to the respective statistical attribute includes: each performance statistic component respectively determines each statistic window in the life cycle of the statistic task and the statistic category of the statistic task according to the respective statistic attribute, wherein the statistic windows are connected end to end according to the time sequence to form the life cycle of the statistic task; each performance statistic component records the stage statistic and the overall statistic of the model operation data according to the verification control signal, the statistic window and the statistic category, wherein the statistic time of the stage statistic is one statistic window, and the statistic time of the overall statistic is from the beginning of the statistic task to the current moment; and each performance statistic component determines the stage performance of each statistic window of the chip to be verified according to the stage statistic and determines the overall performance of the chip to be verified according to the overall statistic.

Optionally, the statistical categories include: counting the packet speed; the phase statistics include: the number of phase packets; the population statistics include: the number of total data packets; the determining the phase performance of each statistical window according to the phase statistics and the overall performance according to the overall statistics comprises: and determining the stage average packet speed according to the number of the stage data packets and the statistical time of the stage statistics, and determining the total average packet speed according to the number of the total data packets and the statistical time of the total statistics.

Optionally, the statistical categories include: counting the throughput rate; the phase statistics include: phase throughput; the population statistics include: the overall throughput; the determining the phase performance of each statistical window according to the phase statistics and the overall performance according to the overall statistics comprises: and determining the stage average throughput rate according to the stage throughput and the statistical time of the stage statistic, and determining the overall average throughput rate according to the overall throughput and the statistical time of the overall statistic.

Optionally, the statistical categories include: counting the values; the phase statistics include: a stage accumulated value; the population statistics include: an overall accumulated value; the determining the phase performance of each statistical window according to the phase statistics and the overall performance according to the overall statistics comprises: and determining a stage average value according to the stage accumulated value and the statistical time of the stage statistic, and determining a population average value according to the population accumulated value and the statistical time of the population statistic.

Optionally, the phase statistics further include: the maximum value and the minimum value of the phase, and the overall statistic further comprises: overall maximum, overall minimum.

Optionally, after obtaining the corresponding performance statistic result, the method further includes: writing the performance statistic result into a log file; analyzing the log file and writing an analysis result into a preset file, wherein the preset file comprises: comma separated files and/or spreadsheet files; and generating a performance chart and/or a curve of the chip to be verified by using the analysis result in the preset file.

In a second aspect, an embodiment of the present invention further provides a chip performance verification apparatus, including: the receiving unit is used for receiving model state information from a preset model environment of a chip to be verified through the performance statistics management platform; the performance statistics management platform is communicated with the preset model environment through a preset interface, and the preset model environment comprises at least one of the following: a function verification environment, a hardware simulation environment and a performance model environment; the triggering unit is used for triggering the performance statistics management platform to generate a verification control signal according to the model state information; and the statistical unit is used for receiving the model operation data of the chip to be verified from the preset model environment through a preset performance statistical component under the control of the verification control signal, performing performance statistics on the model operation data and obtaining a corresponding performance statistical result, wherein the programming language based on the performance statistical management platform is compatible with the programming language based on the preset model environment and the programming language based on the performance statistical component.

Optionally, the triggering unit is specifically configured to: triggering the performance statistics management platform to generate a statistics starting signal according to a running starting signal in the model state information; or triggering the performance statistics management platform to generate a stop statistics signal according to the stop running signal in the model state information.

Optionally, the chip performance verification apparatus provided in the embodiment of the present invention further includes: the component adding unit is used for adding a pointer of the performance statistic component into a component pointer index preset by the performance statistic management platform or into a component pointer index preset by a lower sub-platform of the performance statistic management platform according to a preset component membership relation before receiving the model operation data of the chip to be verified from the preset model environment through a preset performance statistic component under the control of the verification control signal; and/or a sub-platform adding unit, configured to add, under the control of the verification control signal and by using a preset performance statistics component, the pointer of each lower sub-platform to a sub-platform pointer index preset by a corresponding upper sub-platform or to a sub-platform pointer index preset by the performance statistics management platform according to a preset platform membership before receiving the model operation data of the chip to be verified from the preset model environment.

Optionally, the statistical unit includes: the signal issuing module is used for the performance statistics management platform to issue the verification control signal to each performance statistics component, wherein the performance statistics component is directly under the management of the performance statistics management platform or under the management of a lower-level sub-platform of the performance statistics management platform; the data receiving module is used for receiving the model operation data corresponding to each performance statistic component according to the verification control signal; and the data statistics module is used for performing performance statistics on the model operation data according to respective statistical attributes of the performance statistics components.

Optionally, the signal issuing module is specifically configured to: if the performance statistics component is directly under the management of the performance statistics management platform, the performance management platform acquires a pointer of the performance statistics component from a component pointer index preset by the performance management platform, and respectively issues the verification control signals to the performance statistics component according to the pointer of the performance statistics component; if the performance statistics component is under the management of a lower-level sub-platform of the performance statistics management platform, the performance management platform acquires a pointer of a first sub-platform where the performance statistics component is located from a sub-platform pointer index preset by the performance management platform; and obtaining the first sub-platform according to the pointer of the first sub-platform, obtaining the pointer of the performance statistics component from a component pointer index preset by the first sub-platform, and respectively issuing the verification control signals to the performance statistics component according to the pointer of the performance statistics component.

Optionally, the data receiving module includes: the first determining submodule is used for each performance statistic component and determining the starting or ending of each statistic task according to the verification control signal; the receiving submodule is used for responding to the starting of the statistical task, and each performance statistical component receives the corresponding model operation data; and the stopping submodule is used for responding to the end of the statistical task, and each performance statistical component stops receiving the corresponding model operation data respectively.

Optionally, the data statistics module includes: the second determining submodule is used for determining each statistical window in the life cycle of the statistical task and the statistical category of the statistical task according to the respective statistical attributes of the performance statistical components, wherein the statistical windows are connected end to end according to the time sequence to form the life cycle of the statistical task; the recording submodule is used for recording stage statistics and overall statistics of the model operation data according to the verification control signal, the statistical window and the statistical category respectively, wherein the statistical time of the stage statistics is one statistical window, and the statistical time of the overall statistics is from the start of the statistical task to the current moment; and the third determining submodule is used for each performance statistic component, determining the stage performance of each statistic window of the chip to be verified according to the stage statistic, and determining the overall performance of the chip to be verified according to the overall statistic.

Optionally, the statistical categories include: counting the packet speed; the phase statistics include: the number of phase packets; the population statistics include: the number of total data packets; the third statistical submodule is specifically configured to: and determining the stage average packet speed according to the number of the stage data packets and the statistical time of the stage statistics, and determining the total average packet speed according to the number of the total data packets and the statistical time of the total statistics.

Optionally, the statistical categories include: counting the throughput rate; the phase statistics include: phase throughput; the population statistics include: the overall throughput; the third statistical submodule is specifically configured to: and determining the stage average throughput rate according to the stage throughput and the statistical time of the stage statistic, and determining the overall average throughput rate according to the overall throughput and the statistical time of the overall statistic.

Optionally, the statistical categories include: counting the values; the phase statistics include: a stage accumulated value; the population statistics include: an overall accumulated value; the third statistical submodule is specifically configured to: and determining a stage average value according to the stage accumulated value and the statistical time of the stage statistic, and determining a population average value according to the population accumulated value and the statistical time of the population statistic.

Optionally, the chip performance verification apparatus provided in the embodiment of the present invention further includes: the write-in unit is used for writing the performance statistical result into a log file after the corresponding performance statistical result is obtained; the analysis unit is used for analyzing the log file and writing an analysis result into a preset file, wherein the preset file comprises: comma separated files and/or spreadsheet files; and the generating unit is used for generating a performance chart and/or a curve of the chip to be verified by using the analysis result in the preset file.

In a third aspect, an embodiment of the present invention further provides an electronic device, including: the device comprises a shell, at least one processor, a memory, a circuit board and a power circuit, wherein the circuit board is arranged in a space enclosed by the shell, and the processor and the memory are arranged on the circuit board; a power supply circuit for supplying power to each circuit or device of the electronic apparatus; the memory is used for storing executable program codes; the at least one processor executes a program corresponding to the executable program code by reading the executable program code stored in the memory, and is used for executing any chip performance verification method provided by the embodiment of the invention.

In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, where one or more programs are stored, and the one or more programs are executable by one or more processors to implement any one of the chip performance verification methods provided by the embodiments of the present invention.

The chip performance verification method and device, the electronic device and the computer-readable storage medium provided by the embodiment of the invention can receive model state information from a preset model environment of a chip to be verified through a performance statistics management platform, trigger the performance statistics management platform to generate a verification control signal according to the model state information, receive model operation data of the chip to be verified from the preset model environment through a preset performance statistics component under the control of the verification control signal, and perform performance statistics on the model operation data to obtain a corresponding performance statistics result. Therefore, the programming language based on the performance statistics management platform is compatible with the programming language based on the preset model environment and the programming language based on the performance statistics component, so that the performance statistics operation of the chip to be verified can be conveniently integrated with the preset model environments such as the function verification environment, the hardware simulation environment, the performance model environment and the like of the chip to be verified, the performance information of the chip to be verified can be conveniently obtained and the performance verification can be completed by means of the preset model environment or while the function verification or other operations such as simulation, verification and the like are carried out, the waveform does not need to be generated, the manual statistics comparison is not needed, and the chip performance verification efficiency is effectively improved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a flowchart of a method for verifying chip performance according to an embodiment of the present invention;

fig. 2 is a schematic diagram of an organization structure of a statistics management platform in the chip performance verification method according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a program architecture for implementing a chip performance verification method according to an embodiment of the present invention;

FIG. 4 is a flow chart of outputting statistical results according to an embodiment of the present invention;

FIG. 5 is a flow chart of packet speed statistics according to an embodiment of the present invention;

FIG. 6 is a flow chart of performing numerical statistics in an embodiment of the present invention;

fig. 7 is a schematic structural diagram of a chip performance verification apparatus according to an embodiment of the present invention;

fig. 8 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.

Detailed Description

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

It should be understood that the described embodiments are only some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Technical ideas, embodiments and advantageous technical effects of the embodiments of the present invention will be described in detail below with reference to specific examples in order to enable those skilled in the art to better understand the technical ideas, embodiments and advantageous technical effects of the examples.

In a first aspect, embodiments of the present invention provide a chip performance verification method, which can effectively improve chip performance verification efficiency.

As shown in fig. 1, a chip performance verification method provided by an embodiment of the present invention may include:

s11, receiving model state information from a preset model environment of a chip to be verified through a performance statistics management platform; the performance statistics management platform is communicated with the preset model environment through a preset interface, and the preset model environment comprises at least one of the following: a function verification environment, a hardware simulation environment and a performance model environment;

the performance statistics management platform is mainly used for managing performance verification operations of the chip and performing statistics on performance data, where the performance data may be, for example, transmission or processing delay, throughput rate, buffer or FIFO (first in first out) occupation depth, backpressure rate, signal slew rate, and the like. The performance statistics management platform may be established through a programming language, for example, the related operations of the performance statistics management may be encapsulated into a class, and the class is instantiated into an object to obtain the corresponding performance statistics management platform.

Because the performance of the chip is expressed by the running dynamic representation of the chip in a certain running environment, the performance statistics management platform can also be based on the running of the chip to be verified in the running environment when performing performance statistics. In the embodiment of the invention, when the performance verification is performed, the operating environment of the chip to be verified can be referred to as a preset model environment. Optionally, the preset model environment may be specially designed for verifying the performance of the chip, or may be designed when the chip is subjected to functional verification or other aspects of verification, as long as the chip can embody at least a part of the performance of the chip when running in the preset model environment. For example, in one embodiment of the invention, the pre-set model environment may include one or more of a functional verification environment, a hardware simulation environment, a performance model environment.

The performance statistics management platform may communicate with the preset model environment through a preset interface, for example, may receive model state information from the preset model environment through the preset interface. The model state information may refer to a state of the model running in a preset model environment, such as start running, pause running, end running, and the like.

In order to enable the performance verification to be applied more widely and efficiently, and also to enable the performance verification of the chip to be more accurate, in an embodiment of the present invention, the programming language on which the performance statistics management platform is based and the programming language on which the preset model environment is based are compatible with each other, so as to open barriers of different environments.

S12, triggering the performance statistics management platform to generate a verification control signal according to the model state information;

after the performance statistics management platform receives the model state information from the preset model environment, in this step, the performance statistics management platform may be triggered, and a verification control signal may be generated according to the preset model state information, where the verification control signal may be used to control performance statistics operations. The performance of the chip to be verified is reflected when the chip to be verified operates in the preset model environment, so that the operation state of the chip to be verified in the preset model environment directly influences the performance statistical operation. For example, when performing performance statistics, statistics may be started according to the operation of the chip to be verified in the preset model environment, and the statistics may be ended according to the stop of the operation of the chip to be verified.

And S13, under the control of the verification control signal, receiving the model operation data of the chip to be verified from the preset model environment through a preset performance statistic component, and performing performance statistics on the model operation data to obtain a corresponding performance statistic result, wherein the programming language based on the performance statistic management platform is compatible with the programming language based on the preset model environment and the programming language based on the performance statistic component.

After the performance statistics management platform generates the verification control signal, the preset performance statistics component may receive the model operation data of the chip to be verified from the preset model environment under the control of the verification control signal, and perform performance statistics on the model operation data. Similar to the performance statistics management platform, the performance statistics component may be implemented by a programming language, for example, operations related to the performance statistics operation may be encapsulated into a corresponding statistics class, and then the statistics class is instantiated into a statistics class object, where the statistics class object is the corresponding performance statistics component. Optionally, in an embodiment of the present invention, some basic statistical operations may also be encapsulated into a statistical base class, and different statistical classes may be derived from the statistical base class respectively.

In the embodiment of the invention, the performance statistics refers to mathematical statistics of the performance of the chip to be verified in the process of running in the preset model environment. Optionally, when performing performance statistics, the performance statistics component may receive each model operating parameter transmitted from the preset model environment, and after analyzing the model operating parameters, select a part of the data to record, for example, select the data that can represent the performance of the chip most to record, so as to accurately reflect the performance of the chip, and at the same time, greatly reduce the data storage burden, and further improve the performance statistics efficiency of the chip.

Optionally, according to the difference of the specific performance being counted, the performance statistics components may also be different, and each performance statistics management platform may manage one or more performance statistics components, for example, in an embodiment of the present invention, the performance statistics management platform may manage one or more performance statistics components that count transmission delay, one or more performance statistics components that count throughput, and the like.

In order to enable the performance verification to be applied more widely and efficiently, and also to enable the performance verification of the chip to be more accurate, in the embodiment of the present invention, the programming language on which the performance statistics component is based, the programming language on which the performance statistics management platform is based, and the programming language on which the preset model environment is based are also compatible with each other, for example, all of the three may be established based on a hardware verification language systemvverilog.

The chip performance verification method provided by the embodiment of the invention can receive model state information from a preset model environment of a chip to be verified through a performance statistics management platform, trigger the performance statistics management platform to generate a verification control signal according to the model state information, receive model operation data of the chip to be verified from the preset model environment through a preset performance statistics component under the control of the verification control signal, and perform performance statistics on the model operation data to obtain a corresponding performance statistics result. Therefore, the programming language based on the performance statistics management platform is compatible with the programming language based on the preset model environment and the programming language based on the performance statistics component, so that the performance statistics operation of the chip to be verified can be conveniently integrated with the preset model environments such as the function verification environment, the hardware simulation environment, the performance model environment and the like of the chip to be verified, the performance information of the chip to be verified can be conveniently obtained and the performance verification can be completed by means of the preset model environment or while the function verification or other operations such as simulation, verification and the like are carried out, the waveform does not need to be generated, the manual statistics comparison is not needed, and the chip verification efficiency is effectively improved.

Further, under the condition that the preset model environment comprises a function verification environment or a hardware simulation environment, since the function verification, the hardware simulation and the like are the verification which is widely adopted in the field of chip verification and is very close to the real condition of the chip, the performance statistical result obtained according to the method also has good accuracy and is greatly superior to the performance analysis performed by other commercial tools or high-level modeling languages (such as SystemC) and the like, and therefore, the accuracy of the performance verification can be greatly improved while the efficiency of the chip verification is effectively improved.

Specifically, after the performance statistics management platform receives the model state information from the preset model environment of the chip to be verified in step S11, the performance statistics management platform may be triggered in step S12 to generate the verification control signal according to the received model state information. Optionally, the generated verification control signal is correspondingly different according to different model state information, for example, in an embodiment of the present invention, the performance statistics management platform may be triggered to generate a start statistics signal according to a start operation signal in the model state information; or, the performance statistics management platform may be triggered to generate a stop statistics signal according to the stop operation signal in the model state information.

For example, when a chip to be verified in a preset model environment is in an operating state, the performance statistics management platform receives model state information of 'operating', and generates a verification control signal of 'executing statistics operation' according to the model state information of 'operating'; when a chip to be verified in a preset model environment is in a stop state, the performance statistics management platform receives model state information of 'stop running', and generates a verification control signal of 'stop statistics operation' according to the model state information of 'stop running'.

After the performance statistics management platform generates the verification control signal, in step S13, under the control of the verification control signal, the model operation data of the chip to be verified is received from the preset model environment through a preset performance statistics component, and performance statistics is performed on the model operation data.

Specifically, in order to facilitate performance verification of different circuit modules in a chip to be verified, in an embodiment of the present invention, a performance statistics management platform may be hierarchically managed, each relatively independent circuit module may correspond to a lower-level sub-platform, and performance statistics operation on the circuit module may be controlled by controlling the lower-level sub-platform. Illustratively, as shown in fig. 2, in one embodiment of the present invention, one or more levels of sub-platforms may be provided under the performance management platform. Each lower-level sub-platform and the performance statistics management platform can be based on the same class and obtained by respectively instantiating the class differently, so that the variables and/or member functions corresponding to each lower-level sub-platform and the performance statistics management platform can be the same. Optionally, each performance statistics component may be directly under management of the performance statistics management platform, or may also be under management of a lower-level sub-platform of the performance statistics management platform. The performance statistics management platform can call the direct lower-level sub-platform and/or the performance statistics component, and similarly, each level of sub-platform can call the direct lower-level sub-platform and/or the performance statistics component, so that the hierarchical logic is realized.

Based on this, the step S12, under the control of the verification control signal, receiving, by a preset performance statistics component, the model operation data of the chip to be verified from the preset model environment, and performing performance statistics on the model operation data may specifically include:

the performance statistics management platform issues the verification control signal to each performance statistics component;

each performance statistic component receives the corresponding model operation data according to the verification control signal;

and each performance statistic component carries out performance statistics on the model operation data according to the respective statistic attribute.

Specifically, in order to better control each performance statistics component, in an embodiment of the present invention, the performance statistics management platform and its subordinate sub-platform may respectively manage their respective subordinate sub-platforms and performance statistics components by means of a pointer queue. For example, a component pointer index and a sub-platform pointer index may be preset in the performance statistics management platform, a pointer of a component to be verified is added to the component pointer index, and a pointer of a sub-platform to be verified is added to the sub-platform index. When the verification control signal needs to be sent to the performance statistics component and/or the lower-level sub-platform, the verification control signal can be sent to the corresponding performance statistics component through the component pointer index and the sub-platform pointer index. Similarly, each lower sub-platform may also have its own component pointer index and sub-platform pointer index set therein, and perform similar management operations, thereby forming a hierarchical management structure. Optionally, the pointer index here may have various forms as long as the corresponding pointer can be obtained according to the pointer index. For example, the pointer index may include: pointer queues, pointer arrays, pointer sets, pointer linked lists, and the like.

In order to add the various pointers to the corresponding pointer indexes, optionally, before receiving the model operation data of the chip to be verified from the preset model environment through a preset performance statistics component under the control of the verification control signal, the chip performance verification method provided in the embodiment of the present invention may further include: adding the pointer of the performance statistic component into a component pointer index preset by the performance statistic management platform or into a component pointer index preset by a lower sub-platform of the performance statistic management platform according to a preset component membership relation; and/or adding the pointer of each lower-level sub-platform into a corresponding sub-platform pointer index preset by an upper-level sub-platform according to a preset platform membership relationship, or adding the pointer of each lower-level sub-platform into a sub-platform pointer index preset by the performance statistics management platform, so that the performance statistics management forms a hierarchical organization structure.

Through the hierarchical organization structure, the performance management statistical platform can conveniently select a part of circuit modules of the chip to be verified according to the requirement, or verify or uniformly verify each circuit module respectively, thereby effectively improving the flexibility of chip performance verification.

Based on the organization structure of the performance statistics management platform, optionally, in an embodiment of the present invention, the issuing, by the performance statistics management platform, the verification control signal to each of the performance statistics components may specifically include:

if the performance statistics component is directly under the management of the performance statistics management platform, the performance management platform acquires a pointer of the performance statistics component from a component pointer index preset by the performance management platform, and respectively issues the verification control signals to the performance statistics component according to the pointer of the performance statistics component;

if the performance statistics component is under the management of a lower-level sub-platform of the performance statistics management platform, the performance management platform acquires a pointer of a first sub-platform where the performance statistics component is located from a sub-platform pointer index preset by the performance management platform; and obtaining the first sub-platform according to the pointer of the first sub-platform, obtaining the pointer of the performance statistics component from a component pointer index preset by the first sub-platform, and respectively issuing the verification control signals to the performance statistics component according to the pointer of the performance statistics component.

For example, as shown in fig. 2, when the statistics management platform a1 needs to send the verification control signal to the statistics component B1, the statistics management platform a1 may directly obtain the pointer of the statistics component B1 from the component pointer index under the statistics management platform a1, and issue the verification control signal to the performance statistics component B1 according to the pointer. When the statistics management platform a1 needs to send the verification control signal to the statistics component B2, the statistics management platform a1 may obtain the pointer of the sub-platform a2 from the sub-platform pointer index under the statistics management platform a1, and obtain the sub-platform a2 according to the pointer, and the sub-platform a2 may further obtain the pointer of the statistics component B2 from the component pointer index under the statistics management platform a2, and issue the verification control signal to the performance statistics component B2 according to the pointer.

After the performance statistics management platform issues the verification control signal to each performance statistics component, each performance statistics component can receive the corresponding model operation data according to the verification control signal, and perform performance statistics on the model operation data according to the statistical attributes.

Specifically, the receiving, by each of the performance statistics assemblies according to the verification control signal, the corresponding model operation data may include: each performance statistic component determines the starting or ending of each statistic task according to the verification control signal; responding to the starting of the statistical task, and respectively receiving the model operation data corresponding to each performance statistical component; and responding to the end of the statistic task, and stopping receiving the model operation data corresponding to each performance statistic component respectively. Here, the model operation data may refer to various items of data generated when the chip to be verified operates in a preset model environment such as a functional verification environment, a hardware simulation environment, and the like, such as transmission or processing delay, occupation depth of a buffer or a FIFO (first in first out), the number of transmission or processing packets, and length of each packet.

It can be understood that, when the chip to be verified operates in the preset model environment, the performance to be counted may be various, for example, both the transmission delay and the throughput rate are counted, and for each performance to be counted, the performance may be implemented by a corresponding performance counting component, and each performance counting component may work in parallel. For example, each performance statistics component may simultaneously begin receiving model operational data or simultaneously stop receiving model operational data based on the received verification control signal to unify the performance statistics of the various aspects.

Further, after receiving the model operation data, each performance statistics component may perform performance statistics on the model operation data according to the respective statistical attributes. The specific method of performance statistics may be determined based on the statistical attributes of each performance statistics component. The statistical attributes are parameters for describing statistical characteristics of each performance statistics component, for example, whether the performance statistics component performs continuous statistics or intermittent statistics, which data needs to be counted, which strategy is adopted to screen out the data, and the like.

In order to effectively know the performance of each stage in the operation of the chip to be verified so as to improve the chip design more specifically, and simultaneously, in order to not excessively increase the data storage capacity so as to improve the performance verification efficiency, in an embodiment of the invention, besides verifying the overall performance of the chip to be verified, a plurality of statistical windows can be divided into statistical tasks executed by a performance statistical component, and statistics corresponding to the statistical windows are recorded by taking each statistical window as a unit. In a certain range, the smaller the statistical window is, the shorter the corresponding time is, the more accurate the obtained window statistics is, and the larger the data storage amount is, the larger the statistical window is, the longer the corresponding time is, the coarser the obtained window statistics is, and the smaller the data storage amount is. Optionally, the statistical windows corresponding to different performance statistical components may be flexibly set or adjusted as required. The statistical windows corresponding to different performance statistical components may be equal or different.

Besides the statistical window, the statistical categories of the performance statistical components are different, and the corresponding statistical strategies are also different. Based on this, in an embodiment of the present invention, the performing, by each performance statistics component, performance statistics on the model operation data according to the respective statistical attributes may specifically include:

each performance statistic component respectively determines each statistic window in the life cycle of the statistic task and the statistic category of the statistic task according to the respective statistic attribute, wherein the statistic windows are connected end to end according to the time sequence to form the life cycle of the statistic task;

each performance statistic component records the stage statistic and the overall statistic of the model operation data according to the verification control signal, the statistic window and the statistic category, wherein the statistic time of the stage statistic is one statistic window, and the statistic time of the overall statistic is from the beginning of the statistic task to the current moment;

and each performance statistic component determines the stage performance of each statistic window of the chip to be verified according to the stage statistic and determines the overall performance of the chip to be verified according to the overall statistic.

For example, in one embodiment of the present invention, the statistical category of the performance statistics component comprises packet speed statistics, and the stage statistics comprises the number of stage packets; the total statistic comprises the number of total data packets; then based thereon, determining phase performance for each statistical window from the phase statistics, and determining the overall performance from the overall statistics may comprise: and determining the stage average packet speed according to the number of the stage data packets and the statistical time of the stage statistics, and determining the total average packet speed according to the number of the total data packets and the statistical time of the total statistics. For example, the statistical window is 10 ns, and the time of 3 statistical windows is currently running, where the number of data packets processed by the statistical windows W1, W2, and W3 is 12, 18, and 27, respectively, and the stage average packet speed is 1.2/ns, 1.8/ns, and 2.7/ns, respectively. The total number of the data packets is 12+18+27 to 57 (ns), the total statistical time is 10+10+10 to 30 (ns), and the total average packet rate is 57/30 to 1.9 (ns).

Optionally, in another embodiment of the present invention, the statistical category of the performance statistics component includes throughput rate statistics, the phase statistics include phase throughput, and the population statistics include population throughput; then, based on this, determining the phase performance of each statistical window according to the phase statistics, and determining the overall performance according to the overall statistics may specifically include: and determining the stage average throughput rate according to the stage throughput and the statistical time of the stage statistic, and determining the overall average throughput rate according to the overall throughput and the statistical time of the overall statistic.

For example, the statistical window is 10 ns, and 3 statistical windows of time have been currently run, where the statistical windows W1, W2, and W3 process data amounts of 512 bits, 1024 bits, and 2048 bits, respectively, and the stage throughput rates are 51.2 bits/ns, 102.4 bits/ns, and 204.8 bits/ns, respectively. The total data volume is 512+1024+2048 (3584 bits), the total statistical time is 10+10+10 (ns) — 30 (ns), and the total average packet rate is 3584/30 (bits/ns) — 119.5 (ns).

Optionally, in another embodiment of the invention, the statistical categories of the performance statistics component include numerical statistics, the stage statistics include stage accumulations, and the population statistics include population accumulations; then based thereon, determining phase performance for each statistical window from the phase statistics, and determining the overall performance from the overall statistics may comprise: and determining a stage average value according to the stage accumulated value and the statistical time of the stage statistic, and determining a population average value according to the population accumulated value and the statistical time of the population statistic.

For example, the statistical window is 10 nanoseconds, and the time of 3 statistical windows has been currently run, where the statistical window W1 receives 4 data, the phase accumulated value obtained by adding the 4 data to each other is 3.5, the statistical window W2 receives 6 data, the phase accumulated value obtained by adding the 6 data to each other is 7.2, the statistical window W3 receives 8 data, the phase accumulated value obtained by adding the 8 data to each other is 8.6, and the total accumulated value is 3.5+7.2+8.6, which is 19.3.

Optionally, in the value statistics, in addition to the phase accumulated value and the overall accumulated value, other feature values may be counted, for example, the phase statistics may further include a phase maximum value, a phase minimum value, and the overall statistics may further include an overall maximum value, an overall minimum value, and the like.

The stage statistic and the population statistic are both performance statistics results corresponding to the chip to be verified, and after the corresponding performance statistics results are obtained, the chip performance verification method provided by the embodiment of the invention may further include: writing the performance statistic result into a log file; analyzing the log file and writing an analysis result into a preset file, wherein the preset file comprises: comma separated files and/or spreadsheet files; and generating a performance chart and/or a curve of the chip to be verified by using the analysis result in the preset file.

Since the above performance verification process can be implemented by a programming language, the obtained performance statistics result can also be output to a corresponding file by the programming language. In order to make the statistics well readable, in one embodiment of the invention, the performance statistics may be written to a log file. Optionally, the log file may be a text-type file.

Further, in order to more intuitively and vividly show the performance of the chip to be verified, in an embodiment of the present invention, after the performance statistical result is written into the log file, the log file may be analyzed through the scripting language to obtain a performance analysis result, the performance analysis result is written into the comma separation file and/or the data table file, and then a performance graph and/or a curve of the chip to be verified is conveniently generated by using the analysis result in the comma separation file and/or the data table file, thereby effectively improving the visualization degree of the chip performance.

The chip performance verification method provided by the embodiment of the invention is described in detail through specific embodiments.

The performance verification method of the chip provided by the embodiment of the invention can be written based on a hardware verification language and can be very conveniently integrated in a function verification environment or a performance model based on the hardware verification language. As shown in fig. 3, the method is generally implemented by a performance statistics management platform (stat _ management), a statistics base class (stat _ base), a packet speed statistics class (tps _ stat), a throughput statistics class (bps _ stat), a numerical statistics class (num _ stat), a log parsing script tool, and so on. Wherein, the first 5 parts can be realized based on hardware verification language, and the last part can be realized based on script language.

The performance statistics management platform may be used to manage all statistics class objects (statistics class objects, i.e. performance statistics components in the foregoing). The statistical class object is instantiated from the corresponding statistical class. Each statistical class is inherited by the statistical base class. The statistics base class is a parent class of each statistics class, and some common methods are declared and implemented in the statistics base class. The respective portions in fig. 3 are explained below separately.

Performance statistics management platform

The performance statistics management platform can manage each performance statistics component and is the top-level structure of performance verification. The inside of the statistics management platform can be provided with a pointer queue for storing the performance statistics component pointers:

stat_base m_child_stat[$]；

the performance statistics management platform is also provided with a function for adding a statistical component pointer to the pointer queue:

function void add_child_stat(stat_base child)。

an engineer may instantiate various statistical classes in a pre-defined model environment (e.g., in a verification environment or a performance model), obtain corresponding statistical class objects, and instantiate a statistical management platform. The statistical class object is also the performance statistics component of the previous text. Furthermore, the statistical class object can be added to the statistical management platform in a mode of calling add _ child _ stat, so that the statistical management platform can conveniently perform unified management.

Furthermore, a queue for storing pointers of subordinate sub-platforms of the statistical management platform can be further arranged in the performance statistical management platform:

stat_manage m_child_manage[$]；

optionally, each lower sub-platform and the statistics management platform may use the same statistics class as a parent class, and therefore, member functions of each lower sub-platform and the performance statistics management platform may be the same, and a performance statistics component and a sub-platform at a next level may also be set in each lower sub-platform.

A function for adding a sub-platform to the queue may be set in the performance statistics management platform:

function void add_child_manage(stat_manage child)；

an engineer may instantiate the statistics management platform and its subordinate sub-platforms in a preset model environment (e.g., in a verification environment or a performance model), and perform hierarchical management of a tree structure by calling an add _ child _ management function. For example, the hierarchical structure of the performance statistics management platform may be as shown in FIG. 2.

In order to output the performance statistics, a function print _ result of the print statistics may also be provided in the performance statistics management platform. The function may have a parameter file handle of the type integer ("0", "1", "X", "Z" 4 state integer), the default value of which is 0. As shown in fig. 4, in this function, if the incoming parameter file _ handle is 0, the log file may be created in an "open" manner and the file handle may be acquired, otherwise, if the incoming parameter file _ handle is not 0, the incoming parameter may be directly used as the file handle of the write log. Then, the print _ result of the function of the print statistical result may traverse all statistical windows of the statistical management platform and its lower sub-platforms, and for each statistical window, if the current platform to which the statistical window belongs is the topmost statistical management platform, the start time of the statistical window may be printed, and the print _ result function of each sub-management platform may be called in a recursive manner, and finally, the statistical result of the current statistical window of each statistical object may be printed in each statistical object (i.e., performance statistics component) under the statistical management platform and its lower sub-platforms.

Illustratively, the print _ result function of the print statistics may be implemented as follows:

further, in order to control the start and end of the performance statistics operation, in the performance statistics management platform, a function start _ start of start statistics and a function stop _ start of stop statistics are also defined, and a user can start statistics or end statistics by calling the functions. In the two functions, each lower sub-platform and each statistical object are traversed, and the starting statistical function or the stopping statistical function in each lower sub-platform and each statistical object is respectively called, so that the performance statistics of each lower sub-platform and each statistical object can be started or stopped simultaneously.

Illustratively, the function start _ start of the start statistic may be implemented as follows:

similarly, a stop-statistic function stop _ stat can be obtained.

(II) statistics base class

The statistics base class (stat base) is a parent class to the individual statistics classes, which declares and implements some common methods. All statistical classes inherit the statistical base class.

In the statistical base, a statistical function stat is implemented, and a user performs statistics by calling the statistical function. In the statistical function, it is first determined whether statistics have been started, and if in the started state, the incoming data to be counted is stored in a statistics mailbox (m _ stat _ data _ box). Wherein, the statistical data mailbox is equivalent to a section of cache.

Exemplarily, the statistical function stat can be implemented as follows:

wherein, value is the incoming DATA to be counted, the DATA type is bit, and the bit WIDTH is PERF _ STAT _ DATA _ WIDTH.

In the statistical base class, a pure imaginary function phase _ result2string is also declared, which is used to return the statistical result of a certain statistical window, and the starting time of the statistical window is transmitted through the function parameter.

pure virtual function void phase_result2string(bit[63:0]phase_time)；

In the statistical base class, a pure virtual statistical task do _ stat is also declared, and the task is responsible for counting data and recording results.

In the statistical base class, a function start _ start of starting statistics and a function stop _ start of stopping statistics are also defined, and the two functions can be respectively called by the function start _ start of starting statistics and the function stop _ start of stopping statistics in the statistical management platform, so that the statistical management platform can uniformly start or stop the statistical tasks of all statistical objects. It should be noted that the statistics base class is a parent class of each statistics class, and each statistics class is provided with a function start _ start and a function stop _ start for starting statistics, that is, the function start _ start and the function stop _ start for stopping statistics are member functions of each statistics class, and a name of a corresponding statistics class object needs to be added in front when the member function is called, so that the function start _ start and the function stop _ start for starting statistics in the statistics management platform are not confused.

In the start statistic function (start _ start) of the statistic base class, a flag indicating that statistics have been started can be set first, then the time for starting statistics is recorded, and the do _ start task is started.

Illustratively, the start statistics function (start _ start) of the statistics base class may be implemented as follows:

in the stop statistics function (stop _ stat), the time at which the statistics stopped is recorded and a flag is set that the statistics had stopped. Illustratively, the stop statistics function (stop _ stat) of the statistics base class may be implemented as follows:

based on the statistical base class, a plurality of specific statistical classes can be derived, as illustrated below.

(III) packet speed statistics

The packet speed statistic class (tps _ stat), inherited from the statistic base class, can be used to count the packet speed of each node in the chip, i.e. count how many packets are transmitted or processed per second.

In the packet speed statistic class, a pure virtual statistic task do _ stat declared in the statistic base class is realized. As shown in FIG. 5, a while (1) loop is entered immediately after the task is initiated. And delaying a time unit in the loop body, judging whether a stop counting function is called currently, and jumping out of the loop body and ending the task if the stop counting is finished. If the statistics are not stopped, an attempt is made to acquire data from a statistics mailbox (m _ stat _ data _ box), and if the data acquisition is successful, the statistics are accumulated. In the statistics class, two accumulated values are recorded, one for the stage accumulated value and one for the total accumulated value, which are used to calculate the stage packet rate (i.e., the packet rate of the statistics window) and the total packet rate, respectively. The next step in the loop body is to judge whether the current statistical window is finished, and if the statistical window is finished, the statistical result is calculated and recorded. The statistical result is stored in the form of an associative array (hash), and the index is the starting time of the statistical window. And after the stage packet speed is calculated once, clearing the stage accumulated value.

The calculation formula of the stage packet speed is as follows:

phase packet rate ═ phase accumulation value/statistical window time

The calculation formula of the total packet speed is as follows:

the total packet speed is the total accumulated value/(current time-statistical start time)

Further, in the packet speed statistics class, a pure virtual function phase _ result2string declared in the statistics base class is also implemented, and the function is used for returning window statistics data to the statistics management platform. The parameter passed in by this function is the start time of the statistical window. In the function, whether the statistical result of the starting time exists in the statistical result association array is judged firstly. If the statistical result exists, the statistical result is read from the associated array, and the speed unit and the caption are pieced together into a character string to be returned. If the statistical result does not exist, returning an empty character string.

(IV) class of throughput statistics

The throughput rate statistics class (bps _ stat) is also inherited from the above statistics base class, and belongs to rate class statistics as well as the packet speed statistics class, and the statistics function and the statistics task can be the same as those of the packet speed statistics class. The only difference between the packet rate statistics class and the packet rate statistics class is that the rate units used when the character strings are pieced together in phase _ result2string are different, for example, the rate unit corresponding to the throughput rate statistics class is bit/nanosecond, and the rate unit corresponding to the packet rate statistics class is one/nanosecond.

(V) numerical statistics class

The numeric statistic class (num _ stat) is also inherited from the statistic base class, and can count the maximum value, the minimum value and the average value of a certain performance index in a statistic window. The statistical target can be any numerical indicator, such as delay, backpressure rate, buffer or FIFO (first-in-first-out) occupancy depth, signal slew rate, etc.

Similar to the packet speed statistics class, the numerical statistics class also implements its own statistics task do _ stat. As shown in FIG. 6, inside the statistical task is a while (1) loop. And delaying a time unit in the loop body, judging whether a stop counting function is called currently, and jumping out of the loop body and ending the task if the stop counting is finished. If the statistics are not stopped, an attempt is made to retrieve data from the statistics mailbox (m _ stat _ data _ box). And if the data acquisition is successful, recording the maximum value, the minimum value and the accumulated value of the data, and simultaneously recording the number of the data for calculating the average value. After a statistical window is finished, calculating a stage average value and a population average value by dividing an accumulated value by the number of data, and then recording a statistical result into an associated array (hash) with an index as the starting time of the statistical window. After recording data once, the maximum value, the minimum value and the average value of the phase need to be reset.

(VI) statistical Log Format and analysis script

In the statistical log, the statistical starting time of each statistical window can be printed, special symbols such as "#", "+" and the like can be added on the left side and the right side of the statistical time, and the special symbols are used for extracting the time conveniently for analysis and are also used for keeping the log neat and attractive. And starting to print the names and the statistical results of the statistical objects below the statistical time line. The name of the statistical object can be exclusive to one line, and a special symbol is added on the left and the right to facilitate script analysis and beautifulness. The statistical result phase values and the overall values are in the same row, separated by "|".

For example, part of the content of the statistics log may be:

############################100ns#########################

--------------------input_downstream_req_tps(MT/s)-------------------

Phase|Total:1030.00MT/s|188.7MT/s

--------------------input_downstream_data_bps(Gb/s)-------------------

Phase|Total:263.00Gb/s|61.00Gb/s

in order to show the statistical result to the user, the statistical log can be read through the log parsing script, and the statistical result can be parsed and extracted and written into a Comma Separated Values (CSV) file or a data table file. And reading each line of the log file by the analysis script, and matching by using three regular expressions for each line. The three regular expressions are respectively matched with a statistical time row, a statistical object name row and a statistical data row. After any one of the three regular expressions is successfully matched, required character strings such as statistical starting time, statistical object names, statistical data and the like are recorded. After matching the upper data line, one line of data may be recorded into the DataFrame, and the line number of the DataFrame recorded data is increased by 1. Here, DataFrame is a data structure in the Pandas library in Python, which is similar to excel, and is a two-dimensional table that can be used to store numerical values, character strings, and the like. After all the rows of the log are parsed, the data in the DataFrame can be written into a comma separated file or a data table file. Further, a chart and/or a curve can be generated by utilizing data written into a comma separated file or a data table file, so that the performance statistical result can be displayed more intuitively.

(VII) application of Performance verification method in Pre-silicon Performance analysis

The chip performance verification method provided by the embodiment of the invention is based on a hardware verification language systemverilog, so that the method can be applied to any simulation platform built by using the systemverilog. Typically, it can be applied in EDA functional verification platforms and building performance models using systemverilog.

Specifically, in an EDA functional verification platform, a statistics class may be instantiated in a monitor (monitor), resulting in a statistics class object (i.e., a performance statistics component). Wherein, the monitor is a component in the EDA functional verification platform, and can also be instantiated by a corresponding monitor class. After the monitor (monitor) collects the input/output data packets, the stat function of the corresponding performance statistic component can be called to perform performance statistics. For example, when the packet rate needs to be counted, the stat function of tps _ stat may be called after a packet is received, and the incoming parameter is 1. If the throughput needs to be counted, the stat function of bps _ stat can be called after the data packet is received, and the input parameter is the bit number of the data packet.

Alternatively, the statistics management platform and monitor (monitor) may be instantiated in the same location, for example, in an Agent, UVC (Universal Verification Component) or ENV (environment).

After the monitor (monitor) and the statistics management platform are instantiated, the add _ child _ stat function of the statistics management platform can be called to add the statistics object in the monitor (monitor) to the management platform. After all the traffic is processed, the UVM environment may call a print _ result function of the statistics management platform in the post _ main phase to print the performance statistics result.

After the performance verification method provided by the embodiment of the invention is introduced into the EDA function verification platforms at a module level, a subsystem level and a system level, various performance data such as packet speed, throughput rate, back pressure rate, FIFO/Buffer occupation depth, time delay and the like can be analyzed by running corresponding performance test cases. During data analysis, the data table analyzed by the script can be drawn into a curve, so that the fluctuation condition of the index along with the time can be observed more conveniently and intuitively.

Besides the functional verification environment, it is also a feasible solution to build a performance model by using systems optimization and TLM (Transaction Level Modeling) and analyze various interested performance indexes by using a performance statistical device. In the performance model, a stat function of the statistics class may be called in the TLM receive function.

Correspondingly, in a second aspect, the embodiment of the invention further provides a chip performance verification device, which can effectively improve the chip performance verification efficiency.

As shown in fig. 7, the chip performance verification apparatus provided by the embodiment of the present invention may include:

the receiving unit 31 is configured to receive model state information from a preset model environment of a chip to be verified through the performance statistics management platform; the performance statistics management platform is communicated with the preset model environment through a preset interface, and the preset model environment comprises at least one of the following: a function verification environment, a hardware simulation environment and a performance model environment;

the triggering unit 32 is configured to trigger the performance statistics management platform to generate a verification control signal according to the model state information;

and a statistical unit 33, configured to receive, under the control of the verification control signal, the model operation data of the chip to be verified from the preset model environment through a preset performance statistics component, and perform performance statistics on the model operation data to obtain a corresponding performance statistics result, where a programming language on which the performance statistics management platform is based is compatible with a programming language on which the preset model environment is based and a programming language on which the performance statistics component is based.

The chip performance verification device provided by the embodiment of the invention can receive model state information from a preset model environment of a chip to be verified through a performance statistics management platform, trigger the performance statistics management platform to generate a verification control signal according to the model state information, receive model operation data of the chip to be verified from the preset model environment through a preset performance statistics component under the control of the verification control signal, and perform performance statistics on the model operation data to obtain a corresponding performance statistics result. Therefore, the programming language based on the performance statistics management platform is compatible with the programming language based on the preset model environment and the programming language based on the performance statistics component, so that the performance statistics operation of the chip to be verified can be conveniently integrated with the preset model environments such as the function verification environment, the hardware simulation environment, the performance model environment and the like of the chip to be verified, the performance information of the chip to be verified can be conveniently obtained and the performance verification can be completed by means of the preset model environment or while the function verification or other operations such as simulation, verification and the like are carried out, the waveform does not need to be generated, the manual statistics comparison is not needed, and the chip verification efficiency is effectively improved.

Optionally, the triggering unit 32 may be specifically configured to:

triggering the performance statistics management platform to generate a statistics starting signal according to a running starting signal in the model state information;

or

And triggering the performance statistics management platform to generate a stop statistics signal according to the stop running signal in the model state information.

Optionally, the chip performance verification apparatus provided in the embodiment of the present invention may further include:

the component adding unit is used for adding a pointer of the performance statistic component into a component pointer index preset by the performance statistic management platform or into a component pointer index preset by a lower sub-platform of the performance statistic management platform according to a preset component membership relation before receiving the model operation data of the chip to be verified from the preset model environment through a preset performance statistic component under the control of the verification control signal;

and/or

And the sub-platform adding unit is used for adding the pointer of each lower sub-platform into a sub-platform pointer index preset by a corresponding upper sub-platform or adding the pointer of each lower sub-platform into a sub-platform pointer index preset by the performance statistics management platform according to a preset platform membership relationship before receiving the model operation data of the chip to be verified from the preset model environment through a preset performance statistics component under the control of the verification control signal.

Optionally, the statistical unit 33 may include:

the signal issuing module is used for the performance statistics management platform to issue the verification control signal to each performance statistics component, wherein the performance statistics component is directly under the management of the performance statistics management platform or under the management of a lower-level sub-platform of the performance statistics management platform;

the data receiving module is used for receiving the model operation data corresponding to each performance statistic component according to the verification control signal;

and the data statistics module is used for performing performance statistics on the model operation data according to respective statistical attributes of the performance statistics components.

Optionally, the signal issuing module may be specifically configured to:

Optionally, the data receiving module may include:

the first determining submodule is used for each performance statistic component and determining the starting or ending of each statistic task according to the verification control signal;

the receiving submodule is used for responding to the starting of the statistical task, and each performance statistical component receives the corresponding model operation data;

and the stopping submodule is used for responding to the end of the statistical task, and each performance statistical component stops receiving the corresponding model operation data respectively.

Optionally, the data statistics module may include:

the second determining submodule is used for determining each statistical window in the life cycle of the statistical task and the statistical category of the statistical task according to the respective statistical attributes of the performance statistical components, wherein the statistical windows are connected end to end according to the time sequence to form the life cycle of the statistical task;

the recording submodule is used for recording stage statistics and overall statistics of the model operation data according to the verification control signal, the statistical window and the statistical category respectively, wherein the statistical time of the stage statistics is one statistical window, and the statistical time of the overall statistics is from the start of the statistical task to the current moment;

and the third determining submodule is used for each performance statistic component, determining the stage performance of each statistic window of the chip to be verified according to the stage statistic, and determining the overall performance of the chip to be verified according to the overall statistic.

Optionally, the statistical categories include: counting the packet speed; the phase statistics include: the number of phase packets; the population statistics include: the number of total data packets; the third statistical submodule may be specifically configured to: and determining the stage average packet speed according to the number of the stage data packets and the statistical time of the stage statistics, and determining the total average packet speed according to the number of the total data packets and the statistical time of the total statistics.

Optionally, the statistical categories may include: counting the throughput rate; the phase statistics include: phase throughput; the population statistics include: the overall throughput; the third statistical submodule may be specifically configured to: and determining the stage average throughput rate according to the stage throughput and the statistical time of the stage statistic, and determining the overall average throughput rate according to the overall throughput and the statistical time of the overall statistic.

Optionally, the statistical categories include: counting the values; the phase statistics include: a stage accumulated value; the population statistics include: an overall accumulated value; the third statistical submodule may be specifically configured to: and determining a stage average value according to the stage accumulated value and the statistical time of the stage statistic, and determining a population average value according to the population accumulated value and the statistical time of the population statistic.

Optionally, the phase statistics may further include: the phase maximum value and the phase minimum value, and the overall statistics may further include: overall maximum, overall minimum.

the write-in unit is used for writing the performance statistical result into a log file after the corresponding performance statistical result is obtained;

the analysis unit is used for analyzing the log file and writing an analysis result into a preset file, wherein the preset file comprises: comma separated files and/or spreadsheet files;

and the generating unit is used for generating a performance chart and/or a curve of the chip to be verified by using the analysis result in the preset file.

In a third aspect, as shown in fig. 8, an embodiment of the present invention further provides an electronic device, including: the electronic device comprises a shell 100, at least one processor 110, a memory 120, a circuit board 130 and a power circuit 140, wherein the circuit board 130 is arranged inside a space enclosed by the shell 100, and the processor 110 and the memory 120 are arranged on the circuit board 130; a power supply circuit 140 for supplying power to each circuit or device of the electronic apparatus; the memory 120 is used to store executable program code; the processor 110 executes a program corresponding to the executable program code by reading the executable program code stored in the memory 120, for performing any one of the chip performance verification methods provided by the foregoing embodiments. For a specific execution process of the above steps by the processor 110 and further steps executed by the processor 110 by running the executable program code, reference may be made to the description of the foregoing embodiments, which are not described herein again.

In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium storing one or more programs, which are executable by one or more processors to implement the chip performance verification method provided in any one of the foregoing embodiments. For a specific execution process of the above steps by the processor and further steps executed by the processor by running the executable program code, reference may be made to the description of the foregoing embodiments, which are not described herein again.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

All the embodiments in the present specification are described in a related manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments.

In particular, as for the apparatus embodiment, since it is substantially similar to the method embodiment, the description is relatively simple, and for the relevant points, reference may be made to the partial description of the method embodiment.

For convenience of description, the above devices are described separately in terms of functional division into various units/modules. Of course, the functionality of the units/modules may be implemented in one or more software and/or hardware implementations of the invention.

It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like.

The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A method for verifying chip performance, comprising:

receiving model state information from a preset model environment of a chip to be verified through a performance statistics management platform; the performance statistics management platform is communicated with the preset model environment through a preset interface, and the preset model environment comprises at least one of the following: a function verification environment, a hardware simulation environment and a performance model environment;

triggering the performance statistics management platform to generate a verification control signal according to the model state information;

under the control of the verification control signal, receiving model operation data of the chip to be verified from the preset model environment through a preset performance statistics component, and performing performance statistics on the model operation data to obtain a corresponding performance statistics result, wherein a programming language based on the performance statistics management platform is compatible with a programming language based on the preset model environment and a programming language based on the performance statistics component.

2. The method of claim 1, wherein triggering the performance statistics management platform to generate validation control signals based on the model state information comprises:

or

3. The method according to claim 1, wherein before receiving the model operation data of the chip to be verified from the preset model environment through a preset performance statistic component under the control of the verification control signal, the method further comprises:

adding the pointer of the performance statistic component into a component pointer index preset by the performance statistic management platform or into a component pointer index preset by a lower sub-platform of the performance statistic management platform according to a preset component membership relation;

and/or

And adding the pointer of each lower-level sub-platform into a corresponding sub-platform pointer index preset by the upper-level sub-platform or adding the pointer of each lower-level sub-platform into a sub-platform pointer index preset by the performance statistics management platform according to a preset platform membership.

4. The method according to any one of claims 1 to 3, wherein the receiving, by a preset performance statistics component, model operation data of the chip to be verified from the preset model environment under the control of the verification control signal, and performing performance statistics on the model operation data comprises:

the performance statistics management platform issues the verification control signal to each performance statistics component, wherein the performance statistics components are directly under the management of the performance statistics management platform or under the management of a lower-level sub-platform of the performance statistics management platform;

5. The method of claim 4, wherein the performance statistics management platform issuing the verification control signal to each of the performance statistics components comprises:

6. The method of claim 4, wherein the receiving, by each performance statistics component, the corresponding model operating data according to the verification control signal comprises:

each performance statistic component determines the starting or ending of each statistic task according to the verification control signal;

responding to the starting of the statistical task, and respectively receiving the model operation data corresponding to each performance statistical component;

and responding to the end of the statistic task, and stopping receiving the model operation data corresponding to each performance statistic component respectively.

7. The method of claim 4, wherein the performance statistics component, based on the respective statistical attributes, performs performance statistics on the model operating data separately comprises:

8. The method of claim 7, wherein the statistical categories comprise: counting the packet speed; the phase statistics include: the number of phase packets; the population statistics include: the number of total data packets;

the determining the phase performance of each statistical window according to the phase statistics and the overall performance according to the overall statistics comprises:

and determining the stage average packet speed according to the number of the stage data packets and the statistical time of the stage statistics, and determining the total average packet speed according to the number of the total data packets and the statistical time of the total statistics.

9. The method of claim 7, wherein the statistical categories comprise: counting the throughput rate; the phase statistics include: phase throughput; the population statistics include: the overall throughput;

and determining the stage average throughput rate according to the stage throughput and the statistical time of the stage statistic, and determining the overall average throughput rate according to the overall throughput and the statistical time of the overall statistic.

10. The method of claim 7, wherein the statistical categories comprise: counting the values; the phase statistics include: a stage accumulated value; the population statistics include: an overall accumulated value;

and determining a stage average value according to the stage accumulated value and the statistical time of the stage statistic, and determining a population average value according to the population accumulated value and the statistical time of the population statistic.

11. The method of claim 10, wherein the phase statistics further comprise: the maximum value and the minimum value of the phase, and the overall statistic further comprises: overall maximum, overall minimum.

12. The method of any of claims 1 to 3, wherein after obtaining the corresponding performance statistic, the method further comprises:

writing the performance statistic result into a log file;

analyzing the log file and writing an analysis result into a preset file, wherein the preset file comprises: comma separated files and/or spreadsheet files;

and generating a performance chart and/or a curve of the chip to be verified by using the analysis result in the preset file.

13. A chip performance verification apparatus, comprising:

the receiving unit is used for receiving model state information from a preset model environment of a chip to be verified through the performance statistics management platform; the performance statistics management platform is communicated with the preset model environment through a preset interface, and the preset model environment comprises at least one of the following: a function verification environment, a hardware simulation environment and a performance model environment;

the triggering unit is used for triggering the performance statistics management platform to generate a verification control signal according to the model state information;

and the statistical unit is used for receiving the model operation data of the chip to be verified from the preset model environment through a preset performance statistical component under the control of the verification control signal, performing performance statistics on the model operation data and obtaining a corresponding performance statistical result, wherein the programming language based on the performance statistical management platform is compatible with the programming language based on the preset model environment and the programming language based on the performance statistical component.

14. The apparatus according to claim 13, wherein the triggering unit is specifically configured to:

or

15. The apparatus of claim 13, further comprising:

and/or

16. The apparatus according to any one of claims 13 to 15, wherein the statistical unit comprises:

17. The apparatus of claim 16, wherein the signal issuing module is specifically configured to:

18. The apparatus of claim 16, wherein the data receiving module comprises:

19. The apparatus of claim 16, wherein the data statistics module comprises:

20. The apparatus of claim 19, wherein the statistical categories comprise: counting the packet speed; the phase statistics include: the number of phase packets; the population statistics include: the number of total data packets;

the third statistical submodule is specifically configured to:

21. The apparatus of claim 19, wherein the statistical categories comprise: counting the throughput rate; the phase statistics include: phase throughput; the population statistics include: the overall throughput;

the third statistical submodule is specifically configured to:

22. The apparatus of claim 19, wherein the statistical categories comprise: counting the values; the phase statistics include: a stage accumulated value; the population statistics include: an overall accumulated value;

the third statistical submodule is specifically configured to:

23. The apparatus of claim 22, wherein the phase statistics further comprise: the maximum value and the minimum value of the phase, and the overall statistic further comprises: overall maximum, overall minimum.

24. The apparatus of any one of claims 13 to 15, further comprising:

25. An electronic device, comprising: the device comprises a shell, at least one processor, a memory, a circuit board and a power circuit, wherein the circuit board is arranged in a space enclosed by the shell, and the processor and the memory are arranged on the circuit board; a power supply circuit for supplying power to each circuit or device of the electronic apparatus; the memory is used for storing executable program codes; the at least one processor executes a program corresponding to the executable program code by reading the executable program code stored in the memory for performing the method of any of the preceding claims 1-12.

26. A computer-readable storage medium, characterized in that the computer-readable storage medium stores one or more programs which are executable by one or more processors to implement the method of any of the preceding claims 1-12.