CN114201307A

CN114201307A - Processing device and data access method thereof

Info

Publication number: CN114201307A
Application number: CN202011609542.0A
Authority: CN
Inventors: 黄煌彬; 谢崇祥
Original assignee: Nuvoton Technology Corp
Current assignee: Nuvoton Technology Corp
Priority date: 2020-09-17
Filing date: 2020-12-30
Publication date: 2022-03-18
Also published as: TW202213149A; TWI818194B

Abstract

The invention provides a processing device and a data access method thereof. The first buffer is used for storing first data, the second buffer is used for storing second data, the mirror image buffer controller is coupled with the first buffer and the second buffer, and the mirror image buffer controller automatically copies the first data in the first buffer to the second buffer as the second data when the first data is modified so as to be read by a reading program.

Description

Processing device and data access method thereof

Technical Field

The present invention relates to a data processing technology, and more particularly, to a processing apparatus capable of securely sharing data and a data access method thereof.

Background

Multiple programs or cores of a processing device often have a data sharing requirement in the process of running cooperatively. Therefore, in the field of data processing devices, a memory space is usually divided to provide multiple programs or multiple cores of the processing device for exchanging data. However, in the event of a program error or malicious memory access, the shared data may be altered. Although the conventional Memory Protection Unit (MPU) technology and advanced instruction set machine trusted zone (ARM TrustZone) technology can control the authority of the core of the processing apparatus to the Memory block, neither the MPU technology nor the ARM TrustZone technology has a function of cross-core control. That is, the existing mechanisms cannot ensure the synchronization and security of the shared data. For multi-core processing devices, a unified standard is also lacking to limit the memory access range of each core.

Disclosure of Invention

The embodiment of the invention provides a processor and a data access method thereof, which can achieve the effect of protecting shared data.

The processing device of the embodiment of the invention comprises a first buffer, a second buffer and a mirror image buffer controller. The first buffer is used for storing first data, and the second buffer is used for storing second data. The mirror buffer controller is coupled to the first buffer and the second buffer. The mirror buffer controller automatically copies the first data in the first buffer to the second buffer as the second data when the first data is modified.

The data access method of the processing device comprises the following steps: providing a first buffer and a second buffer to store first data and second data, respectively; and providing a mirror buffer controller, and automatically copying, by the mirror buffer controller, the first data in the first buffer to the second buffer as the second data when the first data is modified.

Based on the above, the processing apparatus and the data access method thereof according to the embodiments of the present invention isolate the original data to be shared from the copied data through the copy operation of the mirror buffer controller, and share the original data to provide other cores or other programs for reading and using on the premise that the original data to be shared is protected. Therefore, the original data in the buffer can be prevented from being changed due to programming errors or external malicious operations. Furthermore, through the configuration of the embodiment of the present invention, the multi-core processing device may limit the memory access range of each core by the same standard.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1A is a schematic view of a processing apparatus according to an embodiment of the invention;

FIG. 1B is a schematic view of a processing apparatus according to another embodiment of the present invention;

FIG. 2 is a schematic view of a processing apparatus according to another embodiment of the present invention;

FIG. 3 is a schematic view of a processing apparatus according to another embodiment of the present invention;

FIG. 4 is a schematic view of a processing apparatus according to another embodiment of the present invention;

FIG. 5 is a schematic view of a processing apparatus according to another embodiment of the present invention;

FIG. 6 is a schematic view of a processing apparatus according to another embodiment of the present invention;

FIG. 7 is a flowchart illustrating data access of a processing device according to an embodiment of the invention.

[ description of reference numerals ]

100. 200, …, 600: processing apparatus

110. 120, 210, 220, 230, 240, 310, 320, …, 370, 410, 420, …, 470, 510, 520, …, 580, 610, 620, …, 670: buffer device

130. 250, 380, 480, 590, 680: mirror image buffer controller

140: writing program

150: read-out program

710. 720: step (ii) of

B: core(s)

B1-B4: memory block

P1-P4: procedure for measuring the movement of a moving object

S1: a first setting command

S2: second setting command

Detailed Description

Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

The processing device of the embodiment of the invention comprises at least one mirror image buffer controller and at least two buffers, wherein the mirror image buffer controller is coupled with the two buffers through a data bus. One of the two buffers may be written with data by a core of the processing device executing a write program. The mirror buffer controller can copy the data to generate copied data and store the copied data in the other buffer, so that the processing device can execute a read program to read the copied data in the other buffer.

The mirror buffer controller may be a microcontroller (Microprocessor) or other programmable circuit. The mirror buffer controller may be comprised of an arithmetic logic unit and a control logic unit. The buffer functions to temporarily store data and provide data reading. The buffer may be disposed in a memory module within the core or outside the core. Still alternatively, one of the two buffers may be disposed in the core and the other of the two buffers may be disposed outside the core. The embodiments of the present invention do not limit the location of the buffer.

Fig. 1A is a schematic diagram of a processing apparatus according to an embodiment of the invention. In the embodiment of FIG. 1A, the processing device 100 includes a buffer 110, a buffer 120, and a mirror buffer controller 130. A mirror buffer controller 130

couples buffers

110 and 120. The mirror buffer controller 130 may enable the processing device 100 to execute the write program to the buffer 110 according to the first setting command S1. In contrast, the mirror buffer controller 130 may enable the processing device 100 to execute the readout program on the buffer 120 according to the first setting command S1. When detecting that the processing device 100 executes the write program 140 to store the data in the buffer 110, the mirror buffer controller 130 copies the data according to the first setting command S1 to generate a copied data, and stores the copied data in the buffer 120 for the read program 150 to read. However, the present invention does not limit the processing device 100 to execute the write procedure only on the buffer 110. In other embodiments, the user may configure the mirror buffer controller 130 so that the processing device 100 can execute the read program and the write program to the buffer 110. The operation between the processing device 100 and the buffer 120 may be similar. It is important that the original data stored in the buffer 110 is not affected no matter how the processing device 100 uses the data in the buffer 120.

The embodiment of the present invention shares the data in the buffer 110 through the above mechanism. As such, the data in the

buffers

110 and 120 can be isolated from each other. When the processing device 100 reads the program 150 from the buffer 120, the data in the buffer 110 is not affected, so as to prevent the data in the buffer 110 from being modified due to a programming error or a malicious operation from the outside, and achieve the effects of protecting the data and confirming the data synchronization.

However, the behavior defined by the first setting command S1 (i.e., the execution of the writing procedure on the buffer 110 and the reading procedure on the buffer 120) can be modified. In another embodiment, a new behavior may be defined by another set command. Fig. 1B is a schematic view of a processing apparatus according to another embodiment of the invention. Referring to fig. 1B, in another embodiment, the mirror buffer controller 130 may enable the processing apparatus 100 to execute the write program 140 on the buffer 120 according to a second setting command S2 different from the first setting command S1 (see fig. 1A). In contrast, the mirror buffer controller 130 may enable the processing device 100 to execute the readout program 150 on the buffer 110 according to the second setting command S2. When detecting that the processing device 100 executes the write program 140 to store the data in the buffer 120, the mirror buffer controller 130 copies the data according to the second setting command S2 to generate a copied data, and stores the copied data in the buffer 110 for the read program 150 to read.

It should be noted that the first setting command S1 and the second setting command S2 can be switched according to a swap command sent by a user. That is, the processing apparatus 100 can determine the setting command according to the actual requirement, so that the mirror buffer controller 130 monitors (Monitor) one buffer. The buffer controller 130 is mirrored and copies the data of the aforementioned buffer to another buffer when the data in the aforementioned buffer is modified. In addition, the mirror buffer controller 130 may determine that the buffer can only be written with data (or can only be read with data, or both) according to the set command.

The embodiment of the invention can be applied to a single core processing device and a plurality of core processing devices. In the embodiments shown in FIGS. 1A and 1B, the processing device may comprise a single core. That is, the core of the processing device can write to and read from the two buffers, respectively. In another embodiment, the processing device may also include a plurality of cores. Fig. 2 is a schematic view of a processing apparatus according to another embodiment of the present invention. Referring to FIG. 2, the processing apparatus 200 includes cores A and B, buffers 210-240, and a mirror buffer controller 250. Mirror buffer controller 250 is coupled to buffer 210 and buffer 220. In this embodiment, the mirror buffer controller 250 may enable core a to execute the write procedure to the buffer 210 according to a set command. Conversely, the mirror buffer controller 250 may enable the core B to execute the read procedure on the buffer 220 according to the aforementioned set command. When the buffer 210 is written by the core a, that is, the buffer 210 is written with data, the mirror buffer controller 250 copies the data to generate copied data, and stores the copied data in the buffer 220. In addition, the processing device 200 may further include

buffers

230 and 240. Core a may execute a write program to buffer 230 and may also execute a read program to buffer 230. The core B may execute a write program to the buffer 240 and may execute a read program to the buffer 240. However, the present invention does not restrict core A to only be able to perform the write procedure to buffer 210. In other embodiments, the user may configure the mirror buffer controller 250 so that core a may perform the read and write processes on the buffer 210. The action between core B and buffer 220 may be repeated. The important point is that the original data stored in buffer 210 is not affected no matter how core B uses the data in buffer 220.

The above-described embodiment may make the data in the

buffers

210 and 220 identical and isolated from each other. The core B program can only read the data in the buffer 220 and cannot access the data in the buffer 210. In this way, the data written by core A into buffer 210 can be protected. Buffer 230 may be written to and read from core a and buffer 240 may be written to and read from core B. Core a may write the data to be shared to buffer 210 instead of buffer 230. That is, in the processing apparatus 200, the cores a and B have a buffer 210 for sharing data in addition to their dedicated buffers (the buffer 230 and the buffer 240, respectively). The mirror buffer controller 250 may detect the data in the buffer 210 and perform a copy operation when detecting a change in the data in the buffer 210. Through the copy operation of the mirror buffer controller 250, the copied data in the buffer 220 can be read out by the core B, so as to achieve the purpose of securely sharing data.

In another application, the mirror buffer controller may copy data from one buffer to other buffers. Fig. 3 is a schematic view of a processing apparatus according to another embodiment of the invention. Referring to fig. 3, the processing apparatus 300 includes a core a, a memory module B, buffers 310-370 in the memory module B, and a mirror buffer controller 380. The mirror buffer controller 380 is coupled to the buffers 310-330. In this embodiment, the processing device 300 has a single core A. Mirror buffer controller 380 may enable core A to execute the write procedure to buffer 310 according to a set command. In this embodiment, different permissions may be set for the cores or the programs respectively, and the core or the program with higher permission may use the reserved area of the specific memory, and if the program or the core with lower permission needs the data with restricted access permission, the mirror buffer controller 380 obtains a copy of the data to prevent the source of the data from being changed by mistake. The program with higher authority may also reserve the authority to read the specific memory, so that the subsequent operation may need to use the data in the specific memory to perform the related operation.

In the present application example, the program P1 in the design core A has higher authority than the programs P2-P4. For example, the program P1 may be a kernel program of an operating system, and the programs P2-P4 are managed by the kernel program (program P1). The core a may execute the program P1 to execute a write program to the buffer 310 and may also execute a read program to the buffer 310. In the case that the program P2, P4 needs to use the execution result of the program P1, the execution result of the program P1 (stored in the buffer 310) can be isolated and protected by the mechanism of the present invention, so that the read action of the program P2, P4 will not modify the data in the buffer 310. The mirror buffer controller 380 enables core a to execute read processes to the

buffers

320 and 330 but not write processes to the

buffers

320 and 330 according to the set command. The mirror buffer controller 380 may Monitor (Monitor) the buffer 310. When the buffer 310 is written with data by core A, the mirror buffer controller 380 copies the data to generate copied data, and stores the copied data in the

buffers

320 and 330 for reading by the readout process. In addition, core A may perform write and read processes to buffers 340-370.

More specifically, core A may execute programs P1-P4. The process P1 can use the space of the bank B1, but cannot use the space of the banks B2-B4. Similarly, the programs P2-P4 can only use the space of the memory blocks B2-B4, respectively. Memory block B1 includes

buffers

310 and 340. Memory block B2 includes

buffers

320 and 350. Memory block B3 includes buffer 360. Memory block B4 includes

buffers

330 and 370. The programs P1-P4 can perform the write program and read program to the buffers 340-370, respectively. The program P1 may write the data to be shared into the buffer 310. Mirror buffer controller 380 may copy the data in buffer 310 to

buffers

320 and 330 for providing programs P2 and P4 for reading, respectively.

Fig. 4 is a schematic view of a processing apparatus according to another embodiment of the present invention. Referring to fig. 4, a difference between fig. 4 and fig. 3 is that the processing apparatus 400 of fig. 4 has cores a and B. The core A processes P1 and P2 use the space of memory blocks B1 and B2, respectively. The programs P3 and P4 of core B use the space of memory blocks B3 and B4, respectively. Memory block B1 includes

buffers

410 and 440. Memory block B2 includes

buffers

420 and 450. Memory block B3 includes buffer 460. Memory block B4 includes

buffers

430 and 470. The programs P1-P4 can perform the write program and read program to the buffers 440-470, respectively. The mirror buffer controller 480 is coupled to the buffers 410-430. The program P1 can write the data to be shared into the buffer 410. The buffer controller 480 is mirrored and copies the data in the buffer 410 to the

buffers

420 and 430 to provide program P2 of core A and P4 of core B for readout, respectively.

Fig. 5 is a schematic view of a processing apparatus according to another embodiment of the invention. Referring to FIG. 5, the processing device 500 includes cores A and B, buffers 510-580, and a mirror buffer controller 590.

Buffers

510 and 550 are located in memory block B1.

Buffers

520 and 560 are disposed in memory block B2.

Buffers

530 and 570 are disposed in memory block B3.

Buffers

540 and 580 are disposed in memory block B4.

In this embodiment, the processing device 500 has cores a and B. The mirror buffer controller 590 is coupled to the buffers 510-540. The mirror buffer controller 590 may enable the program P1 of core a to execute the write program to the buffer 510 according to a set command. In the present application, the authority of the program P1 in the core A is higher than the authorities of the programs P2-P4. Core a may execute program P1 to perform a write program to buffer 510 and may also execute a read program to buffer 510. In the case where the program P4 requires the execution result of the program P1, the execution result of the program P1 (stored in the buffer 510) can be isolated and protected by the mechanism of the present invention so that the read operation of the program P4 does not alter the data in the buffer 510. The mirror buffer controller 590 may enable the core a program P2 to execute the read program to the buffer 520 according to the setting command. The mirror buffer controller 590 may enable the program P3 of the core B to execute the write program to the buffer 530 or execute the read program to the buffer 530 according to the setting command. In the case where the program P2 requires the execution result of the program P3 to be used, the execution result of the program P3 (stored in the buffer 530) can be isolated and protected by the mechanism of the present invention so that the read operation of the program P2 does not alter the data in the buffer 530. The mirror buffer controller 590 may enable the program P4 of the core B to execute the read program to the buffer 540 according to the setting command. In addition, the programs P1-P4 can access the data in the buffers 550-580, respectively. However, the present invention does not limit the program P2 of core a to only execute the read program on the buffer 520. In other embodiments, the user may configure the mirror buffer controller so that the program P2 of core a can execute the read and write processes to the buffer 520. The operation between the program P4 of core B and the buffer 540 can be analogized. It is important to note that no matter how the programs P2 and P4 use the data in the

buffers

520 and 540, the original data stored in the

buffers

530 and 510 will not be affected.

The mirror buffer controller 590 may monitor the buffer 510. When the buffer 510 is written with data by the program P1 of core A, the mirror buffer controller 590 copies the data to generate a copy data, and stores the copy data in the buffer 540 for the program P4 of core B to read. Similarly, mirror buffer controller 590 may monitor buffer 530. When the buffer 530 is written with data by the program P3 of the core B, the mirror buffer controller 590 copies the data to generate a copy data, and stores the copy data in the buffer 520 for the program P2 of the core A to read. In addition, programs P1 and P2 of core A can read from and write to

buffers

550 and 560, respectively. Programs P3 and P4 of core B can read from and write to

buffers

570 and 580, respectively.

The programs P1-P4 can only use the space of the memory blocks B1-B4, respectively. Core A, program P1, writes data to be shared into buffer 510, and core B, program P3, writes data to be shared into buffer 530. The mirror buffer controller 590 copies the data in the

buffers

510 and 530 into the

buffers

520 and 540, respectively, to provide the program P2 of core A and the program P4 of core B for reading. As such, data may be shared across cores and data may be protected. The embodiment of fig. 5 may also be applied to a single-core processing device. For example, in some embodiments, the processing device 500 may only have core A to operate, and the processing device 500 of FIG. 5 may also have core A and core B to operate together.

FIG. 6 is a schematic view of a processing apparatus according to another embodiment of the present invention. Referring to FIG. 6, the processing device 600 includes cores A and B, buffers 610-670, and a mirror buffer controller 680. In this embodiment, the mirror buffer controller 680 is coupled to the buffers 610-640. The mirror buffer controller 680 may enable the program P2 of core B to write to the

buffers

610 and 620 according to a set command. In the present application, the program P2 in the core B has a higher authority than the programs P1, P3. The core B may execute the program P2 to execute the write program to the

buffers

610 and 620, and may execute the read program to the

buffers

610 and 620. In the case where the program P1, P3 needs to use the execution result of the program P2, the execution result of the program P2 (stored in the buffer 610, 620) can be isolated and protected by the mechanism of the present invention, so that the data in the

buffer

610, 620 will not be altered by the read action of the program P1, P3. The mirror buffer controller 680 may enable the core a program P1 to execute the read program to the buffer 630 according to the setting command. The mirror buffer controller 680 may enable the program P3 of the core B to execute the read program to the buffer 640 according to the setting command. In addition, the programs P1-P3 can access the data in the buffers 650-670, respectively. However, the present invention does not limit the program P1 of core a to only execute the read program on the buffer 630. In other embodiments, the user may configure the mirror buffer controller so that the program P1 of core a can execute the read and write processes on the buffer 630. The operation between program P3 and buffer 640 of core B may be repeated. It is important to note that no matter how the programs P1 and P3 use the data in the

buffers

630 and 640, the original data stored in the

buffers

610 and 620 will not be affected.

Mirror buffer controller 680 may monitor

buffers

610 and 620. When the buffer 610 is written with data by the program P2 of the core B, the mirror buffer controller 680 copies the data to generate a copy data, and stores the copy data in the buffer 630 for the program P1 of the core A to read. Similarly, mirror buffer controller 680 may monitor buffer 620. When the buffer 620 is written with data by the program P2 of the core B, the mirror buffer controller 680 copies the data to generate a copy data, and stores the copy data in the buffer 640 for the program P3 of the core B to read. In addition, the program P1 of core a can read and write to the buffer 650. Core B programs P2 and P3 can read from and write to

buffers

660 and 670, respectively.

Core B's program P2 may write the data to be shared into

buffers

610 and 620. Mirror buffer controller 680 may copy the data from

buffers

610 and 620 to

buffers

630 and 640, respectively, for providing program P1 of core A and program P3 of core B for reading. In this way, the original data can be shared for other programs to read and use while being protected.

FIG. 7 is a flowchart illustrating data access of a processing device according to an embodiment of the invention. Referring to fig. 7, in step 710, a first buffer and a second buffer are provided for storing a first data and a second data, respectively. In step 720, a mirror buffer controller is provided and the first data in the first buffer is automatically copied to the second buffer as the second data by the mirror buffer controller when the first data is modified. The mirror buffer controller can enable the processing module to execute the write program to one of the first buffer and the second buffer (for example, the first buffer) according to a set command. When the mirror buffer controller monitors that the data is written into the first buffer, the mirror buffer controller copies the data and stores the copied data into the second buffer so as to provide a read program of the processing module for reading. It should be noted that the mirror buffer controller may enable the processing device to write data into the first buffer according to the setting command. Conversely, the mirror buffer controller may enable the processing device to read data from the second buffer in accordance with the aforementioned set command. However, the present invention does not limit the processing device to only execute the write procedure on the first buffer. In other embodiments, the user may configure the mirror buffer controller so that the processing device can execute the read program and the write program on the first buffer. The action between the processing means and the second buffer may be analogized to that.

In summary, the embodiments of the invention can isolate the original data to be shared from the copied data by the copy operation of the mirror buffer controller. And on the premise that the original data to be shared is protected, the original data is shared out to provide other cores or other programs for reading and using. Therefore, the original data in the buffer can be prevented from being changed due to programming errors or external malicious operations. Furthermore, through the configuration of the embodiment of the present invention, the multi-core processing device may limit the memory access range of each core by the same standard.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A processing apparatus, comprising:

a first buffer for storing first data;

a second buffer for storing second data; and

a mirror buffer controller coupled to the first buffer and the second buffer,

wherein the mirror buffer controller automatically copies the first data in the first buffer to the second buffer as the second data when the first data is modified.

2. The processing apparatus according to claim 1, wherein the processing apparatus executes a write program on the first buffer to write the first data into the first buffer, and the mirror buffer controller stores the second data into the second buffer to provide a read program for the processing apparatus to read.

3. The processing apparatus according to claim 1, wherein the processing apparatus comprises a first core and a second core, the first core executes a write procedure on the first buffer to write the first data into the first buffer, and the mirror buffer controller stores the second data into the second buffer to provide a read procedure of the second core for reading.

4. The processing apparatus according to claim 3, wherein the processing apparatus further comprises a third buffer and a fourth buffer, the first core performs a write procedure and a read procedure on the third buffer, and the second core performs a write procedure and a read procedure on the fourth buffer.

5. The processing apparatus according to claim 1, further comprising:

a third buffer for storing third data;

wherein the mirror buffer controller is coupled to the third buffer, the mirror buffer controller further configured to automatically copy the first data in the first buffer to the third buffer as the third data when the first data is modified.

6. The processing apparatus according to claim 1, characterized in that the processing apparatus further comprises:

a third buffer for storing third data; and

a fourth buffer for storing fourth data,

wherein the buffer controller is coupled to the third buffer and the fourth buffer, the mirror buffer controller automatically copying the third data in the third buffer to the fourth buffer as the fourth data when the third data is modified.

7. The processing apparatus according to claim 6, wherein the processing apparatus executes a write procedure on the first buffer and the third buffer to write the first data and the third data into the first buffer and the third buffer, respectively, and the mirror buffer controller stores the second data and the fourth data into the second buffer and the fourth buffer, respectively, to provide a read procedure for the processing apparatus to read.

8. The processing apparatus as claimed in claim 2, wherein the mirror buffer controller causes the processing apparatus to execute a write procedure on the second buffer to write third data into the second buffer according to a swap command, and the mirror buffer controller automatically copies the third data into the first buffer as fourth data according to the swap command to provide a read procedure of the processing apparatus for reading.

9. A data access method of a processing apparatus, comprising:

providing a first buffer and a second buffer to store first data and second data, respectively;

a mirror buffer controller is provided and the first data in the first buffer is automatically copied to the second buffer as the second data by the mirror buffer controller when the first data is modified.

10. The data access method of a processing device according to claim 9, comprising:

executing, by the processing device, a write procedure on the first buffer to write the first data to the first buffer; and

and storing the second data into the second buffer by the mirror buffer controller so as to provide a reading program of the processing device for reading.