CN114200995A - Reference voltage generating circuit and Sigma Delta modulator - Google Patents
Reference voltage generating circuit and Sigma Delta modulator Download PDFInfo
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- CN114200995A CN114200995A CN202111509713.7A CN202111509713A CN114200995A CN 114200995 A CN114200995 A CN 114200995A CN 202111509713 A CN202111509713 A CN 202111509713A CN 114200995 A CN114200995 A CN 114200995A
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- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
Abstract
The invention discloses a reference voltage generating circuit and a Sigma Delta modulator. The reference voltage generating circuit includes: a first integrator. The first integrator comprises an operational amplifier, a first resistor string and a second resistor string; the first resistor string is connected between the first output end of the operational amplifier and the power supply in series; the first resistor string comprises at least two output ends; the number of the resistors connected between the output ends of the different first resistor strings and the first output end of the operational amplifier is different; the first resistor string is used for providing a first group of reference voltages for the quantizer; the second resistor string is connected between the second output end of the operational amplifier and the power supply in series; the second resistor string comprises at least two output ends; the number of the resistors connected between the output ends of the different second resistor strings and the second output end of the operational amplifier is different; the second resistor string is used for providing a second group of reference voltages for the quantizer. The embodiment of the invention can save power consumption and reduce circuit complexity.
Description
Technical Field
The embodiment of the invention relates to the technical field of integrated circuits, in particular to a reference voltage generating circuit and a Sigma Delta modulator.
Background
A conventional Sigma Delta Analog-to-Digital Converter (ADC) generally includes a cascade integrator, a quantizer and a feedback Digital-to-Analog Converter (DAC). The quantizer serves as an important component, and serves to quantize the signal output from the integrator at the previous stage. The quantizer is generally implemented by connecting a plurality of comparators in parallel, and then, in addition to the output signal of the preceding integrator, the quantizer needs to have a reference voltage input. Therefore, in the prior art, a reference voltage generating circuit is additionally arranged in the Sigma Delta analog-to-digital converter to provide a reference voltage for the quantizer. Thus, the existing Sigma Delta analog-to-digital converter has complex circuit and high power consumption.
Disclosure of Invention
The embodiment of the invention provides a reference voltage generating circuit and a Sigma Delta modulator, so that the circuit complexity is reduced, and the power consumption of the Sigma Delta modulator is saved.
In a first aspect, an embodiment of the present invention provides a reference voltage generating circuit, including:
a first integrator comprising an operational amplifier, a first resistor string and a second resistor string;
the first resistor string is connected between the first output end of the operational amplifier and a power supply in series; the first resistor string comprises at least two output ends; the number of resistors connected between the output end of the first resistor string and the first output end of the operational amplifier is different; the first resistor string is used for providing a first group of reference voltages for the quantizer;
the second resistor string is connected between the second output end of the operational amplifier and a power supply in series; the second resistor string comprises at least two output ends; the number of resistors connected between the output end of the second resistor string and the second output end of the operational amplifier is different; the second resistor string is used for providing a second set of reference voltages to the quantizer.
Optionally, the quantizer is an n-bit quantizer comprising 2n-1 comparator; wherein n is more than or equal to 2 and is an integer;
the first resistor string comprises 2n-1 output terminal, the output terminal of the first resistor string being electrically connected to the first input terminals of all the comparators in reverse order;
the second resistor string comprises 2n-1 output terminal, the output terminal of the second resistor string is electrically connected with the second input terminals of all the comparators in sequence.
Optionally, the first resistor string comprises 2 connected in seriesn-2 first resistors, a first terminal of a1 st first resistor being electrically connected to the first output terminal of the operational amplifier and being a1 st output terminal of the first resistor string; 1 st to 2 ndn-the second ends of the 2 first resistors are sequentially used as the 2 nd to 2 nd resistors of the first resistor stringn-1 output terminal;
the second resistor string comprises 2 connected in seriesn-2 second resistors, a first terminal of a1 st second resistor being electrically connected to the second output terminal of the operational amplifier and being a1 st output terminal of the second resistor string; 1 st to 2 ndn-the second ends of the 2 second resistors are sequentially used as the 2 nd to 2 nd ends of the second resistor stringn-1 output.
In a second aspect, an embodiment of the present invention further provides a Sigma Delta modulator, including: a quantizer and a reference voltage generation circuit as provided in any of the embodiments of the invention.
Optionally, the Sigma Delta modulator further comprises: a first adder and a feedback unit;
the first adder and the first integrator are connected in series with the quantizer, the input end of the feedback unit is electrically connected with the output end of the quantizer, and the output end of the feedback unit is electrically connected with the feedback input end of the first adder;
the first adder, the first integrator, the quantizer, and the feedback unit form a first order modulation loop.
Optionally, the Sigma Delta modulator further comprises: m second adders and m second integrators;
one of the second adders and one of the second integrators are connected in series to form a functional unit; the m functional units are sequentially connected with the first adder, the first integrator and the quantizer in series; the output end of the feedback unit is also electrically connected with the feedback input ends of all the second adders; wherein m is more than or equal to 1 and is an integer;
the m second adders, the m second integrators, the first adder, the first integrator, the quantizer, and the feedback unit form an m +1 order modulation loop.
Optionally, the m +1 order modulation loop further includes: m +1 first coefficient units;
the kth first coefficient unit is connected between the kth second adder and the kth second integrator in series; wherein k is more than or equal to 1 and less than or equal to m;
the (m + 1) th first coefficient unit is connected in series between the first adder and the first integrator.
Optionally, the m +1 order modulation loop further includes: m +1 second coefficient units;
the kth second coefficient unit is connected between the feedback input end of the kth second adder and the output end of the feedback unit in series; wherein k is more than or equal to 1 and less than or equal to m;
the (m + 1) th second coefficient unit is connected in series between the feedback input end of the first adder and the output end of the feedback unit.
Optionally, the Sigma Delta modulator comprises at least two of the modulation loops connected in cascade.
Optionally, the Sigma Delta modulator further comprises:
a processing module; the number of the input ends of the processing module is the same as that of the modulation loops, and the input ends of the processing module are electrically connected with all the modulation loops in a one-to-one correspondence manner.
In the reference voltage generating circuit provided by the embodiment of the invention, the first resistor string and the second resistor string are both embedded into the operational amplifier of the first integrator, and the output signal of the first output end of the operational amplifier is converted into the first group of reference voltages through the voltage division effect of the first resistor string and the second resistor string, and the output signal of the second output end of the operational amplifier is converted into the second group of reference voltages. That is, the reference voltage required by the quantizer is generated by adjusting the structure of the first integrator, and no additional circuit is required to generate the reference voltage, and no new reference voltage signal needs to be introduced. Therefore, compared with the prior art, the embodiment of the invention can reduce the circuit complexity and save the power consumption of the Sigma Delta modulator.
Drawings
FIG. 1 is a schematic diagram of a prior art Sigma Delta modulator;
FIG. 2 is a schematic diagram of a prior art quantizer;
FIG. 3 is a schematic diagram of a conventional reference voltage generating circuit;
FIG. 4 is a schematic diagram of a reference voltage generating circuit according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a quantizer according to an embodiment of the present invention;
FIG. 6 is a schematic structural diagram of a Sigma Delta modulator according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of another Sigma Delta modulator according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
As described in the background, a reference voltage generating circuit is additionally provided in the conventional Sigma Delta analog-to-digital converter to provide a reference voltage to the quantizer. Problems in the prior art are specifically described below.
Fig. 1 is a schematic diagram of a conventional Sigma Delta modulator. Referring to fig. 1, as an important component of the Sigma Delta analog-to-digital converter, a Sigma Delta modulator is a key module for realizing analog-to-digital conversion. Taking a first order single-loop modulator as an example, a prior art Sigma Delta modulator includes: adder 030, integrator 010, quantizer 020, reference voltage generation circuit 050, and DAC (digital-to-analog converter) 040. The adder 030, the integrator 010 and the quantizer 020 are connected in series, the reference voltage generating circuit 050 provides a reference voltage signal for the quantizer 020, and the DAC (digital-to-analog converter) 040 is used as a negative feedback unit and is electrically connected with the adder 030 and the quantizer 020 respectively. Therefore, the Sigma Delta modulator is actually a negative feedback system, and integrates the difference between the input signal VIN0 and the feedback signal of the output signal DATA, and then performs quantization coding to realize analog-to-digital conversion. As an important component of the modulator, the quantizer 020 requires the reference voltage generation circuit 050 to provide a series of reference signals to achieve quantization of the output signal of the integrator 010. The operation principle of the 3-bit (bit) quantizer and the structure of the reference voltage generating circuit 050 will be described below.
Fig. 2 is a schematic diagram of a conventional quantizer. Referring to fig. 2, the 3-bit quantizer includes 7 comparators CMP00-CMP 06. The corresponding relationship between the output signals of the 7 comparators and the digital output signal DATA encoded and converted according to the output signals of all the comparators can be seen in table 1.
TABLE 1
Referring to table 1, it can be seen that a 3-bit digital output signal can be obtained according to the output results of 7 comparators in the quantizer. A detailed description will be given below of how the above-described conversion function is realized by the quantizer from the output signal of the integrator in the prior art. Illustratively, the integrators connected to the quantizer in the Sigma Delta analog-to-digital converter are differential outputs, and then, each comparator in the quantizer includes four input terminals, a first input terminal is connected to the first output signal INP of the integrator, a second input terminal is connected to the second output signal INN of the integrator, a third input terminal is connected to the first reference signal, and a fourth input terminal is connected to the second reference signal. The first input terminals of the comparators CMP00 to CMP06 are all connected to the same first output signal INP, and the second input terminals of the comparators CMP00 to CMP06 are all connected to the same second output signal INN; in order to quantize the output signal of the integrator, the quantizer needs to compare the two output signals of the integrator with a series of reference signals. Then, the third input terminals of the comparators CMP00 to CMP06 sequentially receive different first reference signals, and the first reference signals REFP <0> to REFP <6> may be equal difference signals distributed in a step; the fourth inputs of the comparators CMP00 to CMP06 are sequentially connected to different second reference signals REFN <0> to REFN <6>, which may be equal difference signals distributed in steps.
Fig. 3 is a schematic diagram of a conventional reference voltage generating circuit. Referring to fig. 3, the reference voltage generating circuit illustratively includes: an operational amplifier OP1, an operational amplifier OP2, a voltage-dividing resistor string 021, a transistor T01 and a transistor T02. The transistor T01, the voltage dividing resistor 021 and the transistor T02 are connected in series between a power supply and a grounding terminal; a first input end of the operational amplifier OP1 is electrically connected with a second pole of the transistor T01, and a second input end is connected with a reference signal REFP; the operational amplifier OP2 has a first input terminal electrically connected to the second pole of the transistor T02 and a second input terminal connected to the reference signal REFN. The reference voltage generating circuit outputs a first reference signal REFP <6:0> and a second reference signal REFN <6:0> according to the reference signals REFP and REFN through the voltage division of each series resistor in the voltage division resistor string 021. That is, in the reference voltage generating circuit in the prior art, in addition to the complicated structure, two initial reference signals are additionally provided to generate the reference signal group required by the quantizer.
Based on the above research, the embodiment of the invention provides a reference voltage generating circuit, which generates a reference voltage by embedding a resistor string into an operational amplifier of an integrator, thereby achieving the purposes of saving power consumption and reducing circuit complexity. Fig. 4 is a schematic structural diagram of a reference voltage generating circuit according to an embodiment of the invention. Referring to fig. 4, the reference voltage generating circuit includes: a first integrator. The first integrator includes an operational amplifier, a first resistor string 111 and a second resistor string 112. The first resistor string 111 is connected in series between the first output terminal N1 of the operational amplifier and the power supply; the first resistor string 111 includes at least two output terminals; the number of resistors connected between the output end of different first resistor strings 111 and the first output end N1 of the operational amplifier is different; the first resistor string is used for providing a first set of reference voltages for the quantizer. The second resistor string 112 is connected in series between the second output terminal N2 of the operational amplifier and the power supply; the second resistor string 112 includes at least two output terminals; the number of resistors connected between the output end of the different second resistor string 112 and the second output end N2 of the operational amplifier is different; the second resistor string 112 is used to provide a second set of reference voltages to the quantizer.
The first integrator may be, for example, an RC integrator formed by a resistor, a capacitor, and an operational amplifier, and may output in a differential form, but the present invention is not limited thereto. In order to clearly show the embedding positions of the two resistor strings, fig. 1 only exemplarily shows the specific structures and connection manners of the operational amplifier and the two resistor strings, and does not show other parts of the first integrator. It should be noted that fig. 1 illustrates a specific internal structure of an operational amplifier composed of a plurality of transistors (i.e., transistors T1-T6) and a plurality of current sources (i.e., current sources I1-I7), which can process the first input signal VINP and the second input signal VINN. However, the structure is not limited to the present invention, and the specific structure of the operational amplifier may be selected from any one of the prior art according to the requirement.
Illustratively, the number of outputs of the first resistor string 111 and the number of outputs of the second resistor string 112 are both the same as the number of comparators included in the quantizer. The first group of reference voltages output by the first resistor string 111 and the second group of reference voltages output by the second resistor string 112 are directly used as output signals of the first integrator and are provided to the quantizer according to a preset rule, for example, the output ends of the resistor strings are connected with different input ends of the quantizer according to a preset connection rule; then, the quantizer outputs the quantized result directly according to the first set of reference voltages and the second set of reference voltages, and neither an operational amplifier is required to provide other output signals nor is an additional reference signal required to be provided.
The different numbers of resistors connected between the output end of the different first resistor strings 111 and the first output end N1 of the operational amplifier can be understood as follows: the first resistor string 111 is a voltage-dividing resistor string formed by a plurality of first resistors R1 connected in series, different output terminals thereof are led out by different first resistors R1, and the larger the number of the first resistors R1 connected between the output terminal of the first resistor string 111 and the first output terminal N1 of the operational amplifier, the higher the potential of the output terminal becomes, so that the first group of reference voltages includes a series of potentials which are increased in a stepwise manner. Accordingly, the different numbers of resistors connected between the output terminals of the different second resistor strings 112 and the second output terminal N2 of the operational amplifier can be understood as: the second resistor string 112 is a voltage-dividing resistor string formed by a plurality of second resistors R2 connected in series, different output terminals thereof are led out by different second resistors R2, and the larger the number of the second resistors R2 connected between the output terminal of the second resistor string 112 and the second output terminal N2 of the operational amplifier, the higher the potential of the output terminal becomes, so that the second group of reference voltages includes a series of potentials which are increased in a stepwise manner. Illustratively, the power supply may be a power supply that the operational amplifier itself needs to be switched in for normal operation.
In the reference voltage generating circuit provided by the embodiment of the invention, the first resistor string 111 and the second resistor string 112 are both embedded in the operational amplifier of the first integrator, the output signal of the first output end N1 of the operational amplifier is converted into the first group of reference voltages through the voltage division function of the first resistor string 111 and the second resistor string 112, and the output signal of the second output end N2 of the operational amplifier is converted into the second group of reference voltages. That is, the reference voltage required by the quantizer is generated by adjusting the structure of the first integrator, and no additional circuit is required to generate the reference voltage, and no new reference voltage signal needs to be introduced. Therefore, compared with the prior art, the embodiment of the invention can reduce the circuit complexity and save the power consumption of the Sigma Delta modulator.
Based on the above embodiments, optionally, the quantizer is an n-bit quantizer, and the quantizer includes 2n-1 comparator; wherein n is more than or equal to 2 and is an integer. Accordingly, the first resistor string 111 includes 2n-1 output terminal, the second resistor string 112 comprising 2n-1 output. Illustratively, n ≦ 5.
On the basis of the above embodiments, optionally, the first resistor string 111 includes 2 connected in seriesn-2 first resistors R1, a first end of the 1 st first resistor R1 is electrically connected to the first output end N1 of the operational amplifier and serves as a1 st output end of the first resistor string 111; 1 st to 2 ndnThe second ends of the 2 first resistors R1 are sequentially used as the 2 nd to 2n-1 th output ends of the first resistor string 111. The second resistor string 112 includes 2 connected in seriesnA first end of the 1 st second resistor R2 is electrically connected to the second output end N2 of the operational amplifier and serves as a1 st output end of the second resistor string 112; 1 st to 2 ndnThe second ends of the 2 second resistors R2 are sequentially used as the 2 nd to 2 nd resistors of the second resistor string 112n-1 output. That is, the number of resistors connected in series in the resistor string is one less than the number of output terminals of the resistor string, and the first terminal of the first resistor and the second terminal of each resistor lead out of one output terminal of the resistor string. With this arrangement, the number of resistors to be added for supplying the reference voltage group can be minimized, and the circuit area can be reduced as much as possible. Illustratively, the resistance of each first resistor R1 is the same, the resistance of each second resistor R2 is the same, and the resistance of the first resistor R1 and the resistance of the second resistor R2 are the same; by the arrangement, the voltage values of the output ends of the resistor strings are distributed in an equal difference mode, and the calculation logic of the quantizer is simplified.
In the following, a specific structure of the resistor string and a quantization implementation procedure of the quantizer will be specifically described by taking n as an example of 3, but the present invention is not limited thereto.
Fig. 5 is a schematic structural diagram of a quantizer according to an embodiment of the present invention. In conjunction with fig. 4 and 5, the 3-bit quantizer illustratively includes 7 comparators CMP0 through CMP6, respectively. The output end of the first resistor string 111 is electrically connected with the first input ends of all the comparators in reverse sequence; the output terminal of the second resistor string 112 is electrically connected to the second input terminals of all the comparators in sequence. That is, the reference voltages OUTP <0> to OUTP <6> outputted from the respective output terminals of the first resistor string 111 are sequentially transmitted to the first input terminals of the comparators CMP6 to CMP 0; the reference voltages OUTN <0> to OUTN <6> output from the respective output terminals of the second resistor string 112 are sequentially transmitted to the second input terminals of the comparators CMP0 to CMP 6.
The first resistor string 111 includes 6 first resistors R1 connected in series; along the direction from the first output terminal N1 of the operational amplifier to the power supply, the first resistors R1 from 1 st to 6 th are arranged in sequence, the lower end of the first resistor R1 is the first end thereof, and the upper end thereof is the second end thereof. The first end of the 1 st first resistor R1 leads out the 1 st output end of the first resistor string 111, and outputs a reference voltage OUTP <0 >; the second ends of the 1 st to 6 th first resistors R1 sequentially lead out the 2 nd to 7 th output ends of the first resistor string 111, and sequentially output the reference voltages OUTP <1> to OUTP <6 >. The second resistor string 112 includes 6 second resistors R2 connected in series, and the arrangement direction and the leading-out manner of the output end thereof can be referred to the description of the first resistor string 111, and are not described again.
Taking the resistance values of the first resistor R1 and the second resistor R2 as R, and the currents of the current source I6 and the current source I7 as Iout as an example, the working principle of the 3-bit quantizer includes:
when OUTP <6> -OUTN <0> >0, the output signal CMP _ O <0> -1 of the comparator CMP 0; equivalent to (OUTP <0> +6 × Iout × R) -OUTN <0> > 0; continuing the equivalent, when OUTP <0> -OUTN <0> > -6 × Iout × R, CMP _ O <0> -1. By analogy, the following can be obtained:
when OUTP <0> -OUTN <0> > -4 × Iout × R, CMP _ O <1> -1;
when OUTP <0> -OUTN <0> > -2 × Iout × R, CMP _ O <2> -1;
when OUTP <0> -OUTN <0> >0, CMP _ O <3> -1;
when OUTP <0> -OUTN <0> >2 × Iout × R, CMP _ O <4> -1;
when OUTP <0> -OUTN <0> >4 × Iout × R, CMP _ O <5> -1;
when OUTP <0> -OUTN <0> >6 × Iout × R, CMP _ O <6> -1.
The first output terminal N1 of the operational amplifier is directly connected to the first output terminal of the first resistor string 111, and there is no first resistor R1 therebetween, or the number of first resistors R1 between the two terminals is 0. Therefore, the reference voltage OUTP <0> substantially corresponds to the first output signal of the first integrator when the first resistor string 111 is not provided. Similarly, the reference voltage OUTN <0> substantially corresponds to the second output signal of the first integrator when the second resistor string 112 is not provided. Then, in conjunction with the derivation process described above, it can be seen that the quantizer achieves the correct quantization process and indeed the extra quantizer reference voltage generation circuitry is dispensed with.
It should be noted that the present technical idea is substantially equally applicable to the case where n is 1 (the quantizer includes only one comparator). When N is equal to 1, it is equivalent that the first resistor string 111 and the second resistor string 112 are not provided, but the output signal of the first output terminal N1 of the operational amplifier is directly transmitted to the first input terminal of the comparator, and the output signal of the second output terminal N2 of the operational amplifier is transmitted to the first input terminal of the comparator.
The embodiment of the invention also provides a Sigma Delta modulator, which comprises a quantizer and a reference voltage generating circuit provided by any embodiment of the invention, and has corresponding beneficial effects. The Sigma Delta modulator in combination with the digital filter may constitute a Sigma Delta analog to digital converter. Fig. 6 is a schematic structural diagram of a Sigma Delta modulator according to an embodiment of the present invention. Referring to fig. 6, in one embodiment, optionally, the Sigma Delta modulator includes: a reference voltage generating circuit 10, a quantizer 20, a first adder 30, and a feedback unit 40. The Sigma Delta modulator converts an input signal Vin in analog form to an output signal VDATA in digital form.
The reference voltage generating circuit 10 includes a first integrator 110; the feedback unit 40 may be a digital-to-analog converter. The first adder 30 and the first integrator 110 are connected in series with the quantizer 20, the input terminal of the feedback unit 40 is electrically connected to the output terminal of the quantizer 20, and the output terminal of the feedback unit 40 is electrically connected to the feedback input terminal of the first adder 30. The first adder 30, the first integrator 110, the quantizer 20 and the feedback unit 40 form a first order modulation loop. The first order modulation loop may directly constitute a first order single loop Sigma Delta modulator.
With continued reference to fig. 6, on the basis of the above embodiments, optionally, the Sigma Delta modulator further includes: m second adders 40 and m second integrators 50; wherein m is more than or equal to 1 and is an integer. A second adder 40 and a second integrator 50 are connected in series to form a functional unit; the m functional units are connected in series with the first adder 30, the first integrator 110 and the quantizer 20 in sequence; the output of the feedback unit 40 is also electrically connected to the feedback inputs of all second adders 40. The m second adders 40, the m second integrators 50, the first adder 30, the first integrator 110, the quantizer 20, and the feedback unit 40 form an m +1 order modulation loop, which may directly form an m +1 order single-loop Sigma Delta modulator. Fig. 6 shows the structure of a2 nd order single-loop Sigma Delta modulator by way of example, but not by way of limitation.
It should be noted that the first adder 30 and the second adder 40 are substantially the same adder, and are distinguished by names for convenience of description. It should be noted that the first integrator 110 and the second integrator 50 are not identical in structure, and for the multi-order modulation loop, the first integrator 110 is the last integrator connected in cascade. Therefore, the design idea of the embodiment of the present invention is equivalent to only adding the first resistor string and the second resistor string in the last stage of the integrator.
With continued reference to fig. 6, on the basis of the foregoing embodiments, optionally, the m +1 order modulation loop further includes: m +1 first coefficient units. The kth first coefficient unit is connected in series between the kth second adder 40 and the kth second integrator 50; wherein k is more than or equal to 1 and less than or equal to m. The (m + 1) th first coefficient unit is connected in series between the first adder 30 and the first integrator 110. As shown in fig. 6, for the 2 nd order modulation loop, the 1 st first coefficient unit 60_1 is connected between the second adder 40 and the second integrator 50, and has a coefficient of a 1; the 2 nd first coefficient unit 60_2 is connected between the first adder 30 and the first integrator 110 and has a coefficient a 2. The coefficient of the first coefficient unit can be adjusted according to actual requirements so as to achieve a better conversion effect.
With continued reference to fig. 6, on the basis of the foregoing embodiments, optionally, the m +1 order modulation loop further includes: m +1 second coefficient units. The kth second coefficient unit is connected in series between the feedback input end of the kth second adder 40 and the output end of the feedback unit 40; wherein k is more than or equal to 1 and less than or equal to m. The (m + 1) th second coefficient unit is connected in series between the feedback input terminal of the first adder 30 and the output terminal of the feedback unit 40. As shown in fig. 6, for the 2 nd order modulation loop, the 1 st second coefficient unit 70_1 is connected between the second adder 40 and the feedback unit 40, and has a coefficient of k 1; the 2 nd second coefficient unit 70_2 is connected between the first adder 30 and the feedback unit 40 and has a coefficient k 2. The coefficient of the second coefficient unit can be adjusted according to actual requirements so as to achieve a better conversion effect.
The foregoing embodiments exemplarily give the structure of the single-ring modulator, but do not limit the present invention. In other embodiments, the modulator may also be a multi-ring multi-order structure.
Fig. 7 is a schematic structural diagram of another Sigma Delta modulator according to an embodiment of the present invention. Referring to fig. 7, in one embodiment, optionally, the Sigma Delta modulator includes at least two modulation loops connected in cascade to improve the stability of the modulator on the basis of ensuring the conversion accuracy. Wherein, the output signal of the former stage modulation loop is used as the input signal of the latter stage modulation loop.
With continuing reference to fig. 7, based on the above embodiments, optionally, the Sigma Delta modulator further includes: a processing module 81; the number of the input ends of the processing module 81 is the same as that of the modulation loops, the input ends of the processing module 81 are electrically connected with all the modulation loops in a one-to-one correspondence manner, and the output end of the processing module 81 is used as the output end of the Sigma Delta modulator. The processing module 81 may process quantization noise of the modulator, etc. to improve the accuracy of the conversion result.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A reference voltage generating circuit, comprising:
a first integrator comprising an operational amplifier, a first resistor string and a second resistor string;
the first resistor string is connected between the first output end of the operational amplifier and a power supply in series; the first resistor string comprises at least two output ends; the number of resistors connected between the output end of the first resistor string and the first output end of the operational amplifier is different; the first resistor string is used for providing a first group of reference voltages for the quantizer;
the second resistor string is connected between the second output end of the operational amplifier and a power supply in series; the second resistor string comprises at least two output ends; the number of resistors connected between the output end of the second resistor string and the second output end of the operational amplifier is different; the second resistor string is used for providing a second set of reference voltages to the quantizer.
2. The reference voltage generation circuit of claim 1, wherein the quantizer is an n-bit quantizer comprising 2n-1 comparator; wherein n is more than or equal to 2 and is an integer;
the first resistor string comprises 2n-1 output terminal, the output terminal of the first resistor string being electrically connected to the first input terminals of all the comparators in reverse order;
the second resistor string comprises 2n-1 output terminal, the output terminal of the second resistor string is electrically connected with the second input terminals of all the comparators in sequence.
3. The reference voltage generation circuit of claim 1, wherein the first resistor string comprises 2 connected in seriesn2 first resistances, 1 stThe first end of each first resistor is electrically connected with the first output end of the operational amplifier and is used as the 1 st output end of the first resistor string; 1 st to 2 ndn-the second ends of the 2 first resistors are sequentially used as the 2 nd to 2 nd resistors of the first resistor stringn-1 output terminal;
the second resistor string comprises 2 connected in seriesn-2 second resistors, a first terminal of a1 st second resistor being electrically connected to the second output terminal of the operational amplifier and being a1 st output terminal of the second resistor string; 1 st to 2 ndn-the second ends of the 2 second resistors are sequentially used as the 2 nd to 2 nd ends of the second resistor stringn-1 output.
4. A Sigma Delta modulator, comprising: a quantizer and a reference voltage generation circuit as claimed in any one of claims 1-3.
5. The Sigma Delta modulator of claim 4, further comprising: a first adder and a feedback unit;
the first adder and the first integrator are connected in series with the quantizer, the input end of the feedback unit is electrically connected with the output end of the quantizer, and the output end of the feedback unit is electrically connected with the feedback input end of the first adder;
the first adder, the first integrator, the quantizer, and the feedback unit form a first order modulation loop.
6. The Sigma Delta modulator of claim 5, further comprising: m second adders and m second integrators;
one of the second adders and one of the second integrators are connected in series to form a functional unit; the m functional units are sequentially connected with the first adder, the first integrator and the quantizer in series; the output end of the feedback unit is also electrically connected with the feedback input ends of all the second adders; wherein m is more than or equal to 1 and is an integer;
the m second adders, the m second integrators, the first adder, the first integrator, the quantizer, and the feedback unit form an m +1 order modulation loop.
7. The Sigma Delta modulator of claim 6 wherein the m +1 order modulation loop further comprises: m +1 first coefficient units;
the kth first coefficient unit is connected between the kth second adder and the kth second integrator in series; wherein k is more than or equal to 1 and less than or equal to m;
the (m + 1) th first coefficient unit is connected in series between the first adder and the first integrator.
8. The Sigma Delta modulator of claim 6 wherein the m +1 order modulation loop further comprises: m +1 second coefficient units;
the kth second coefficient unit is connected between the feedback input end of the kth second adder and the output end of the feedback unit in series; wherein k is more than or equal to 1 and less than or equal to m;
the (m + 1) th second coefficient unit is connected in series between the feedback input end of the first adder and the output end of the feedback unit.
9. The Sigma Delta modulator according to any of claims 5 to 8, characterized in that the Sigma Delta modulator comprises at least two of the modulation loops connected in cascade.
10. The Sigma Delta modulator of claim 9, further comprising:
a processing module; the number of the input ends of the processing module is the same as that of the modulation loops, and the input ends of the processing module are electrically connected with all the modulation loops in a one-to-one correspondence manner.
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