CN114189687A - Over-drive controller for display screen - Google Patents

Over-drive controller for display screen Download PDF

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Publication number
CN114189687A
CN114189687A CN202111208741.5A CN202111208741A CN114189687A CN 114189687 A CN114189687 A CN 114189687A CN 202111208741 A CN202111208741 A CN 202111208741A CN 114189687 A CN114189687 A CN 114189687A
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compression
data
image
reference value
values
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郭晓旭
樊晓华
李明
边海波
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Jiangsu Jicui Intelligent Integrated Circuit Design Technology Research Institute Co ltd
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Jiangsu Jicui Intelligent Integrated Circuit Design Technology Research Institute Co ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/169—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding
    • H04N19/184—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being bits, e.g. of the compressed video stream
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
    • H04N19/119—Adaptive subdivision aspects, e.g. subdivision of a picture into rectangular or non-rectangular coding blocks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N9/00—Details of colour television systems
    • H04N9/64—Circuits for processing colour signals
    • H04N9/67—Circuits for processing colour signals for matrixing

Abstract

The invention discloses a display screen over-drive controller which can improve the compression ratio, reduce the image distortion and improve the compression performance and comprises an image compression and decompression processing unit, wherein the image compression and decompression processing unit is used for compressing and decompressing video data, the input data of the input end of the image compression and decompression processing unit is video data, the image compression and decompression processing unit is a compression/decompression data processor based on four values or a compression/decompression data processor based on three values, the four values comprise a maximum reference value, a minimum reference value, a first middle reference value and a second middle reference value, and the three values comprise a maximum reference value, a minimum reference value and an average reference value.

Description

Over-drive controller for display screen
Technical Field
The invention relates to the technical field of display screens, in particular to an overdrive controller for a display screen.
Background
Liquid Crystal Display (LCD) technology has been the most mature and widely used Display technology for more than twenty years, and the brightness of different colors in LCD is mainly realized by applying different driving control voltages, and the rotation angle of Liquid Crystal molecules is changed by applying different voltages, so as to control the amount of backlight light transmission to form the brightness of different colors. However, the conventional liquid crystal display has problems of poor display effect, motion blur, etc. because if the applied driving control voltage is changed, the reaction of the liquid crystal molecules is slowed down after the voltage is changed for a while, which is very likely to cause the image blur effect of the displayed dynamic picture. At present, a commonly used method for improving a dynamic display effect of a liquid crystal display and reducing motion blur is Overdrive Control, and particularly for video content display with a high refresh rate, an Overdrive Control (Overdrive Control) technology can effectively improve a reaction speed of liquid crystal molecules and reduce a trailing effect of a motion image, so that display of a high frame rate video can be supported.
In the overdrive control technique, in order to increase the response speed of the liquid crystal molecules, a larger overdrive voltage V + Δ V needs to be applied on the basis of the normal driving voltage V, and after a frame time, the overdrive voltage V returns to the normal driving voltage V. The Δ V voltage value required for overdrive is not only related to the gray scale currently displayed by the pixel, but also related to the gray scale of the previous frame, and usually a two-dimensional lookup table is used to calculate the overdrive voltage value Δ V by using triangular interpolation.
In order to implement the overdrive technology, a display screen controller needs to store a frame of image data in a frame buffer for implementing the enhanced calculation of the overdrive control, the buffer space of the frame of data is related to the video resolution, corresponding to a high-resolution display, the frame of image data occupies a larger storage space, the use of a larger-space storage chip and the use of a higher read-write access broadband increase the overall cost of the liquid crystal display screen, and the method for solving the problem is to introduce image data compression to save the memory space and the read-write access broadband, and the compression and decompression technology can well reduce the storage capacity of the frame buffer, thereby reducing the cost of the display controller.
The existing circuit for controlling the overdrive of the liquid crystal display generally adopts the following two compression methods: one is a complex compression algorithm, such as a compression algorithm similar to JPG, which can achieve a better compression effect in terms of performance, but results in a very complex implementation circuit, greatly increases the circuit cost, and also increases the power consumption of the display system in mobile applications; the other is a simple block coding algorithm, namely btc (block decoding) algorithm, which is the most widely used image compression algorithm in the overdrive control technology, and the principle is to map all pixel gray values to two gray values RV for a block (block) of 2x2 or 4x40And RV1In addition, a Bitmap (Bitmap) corresponding to the size of the block is used for recording the mapping relation of the gray value, and the compression method has the advantages of simple algorithm principle, small circuit implementation scale, simple structure and low power consumption and cost; but the disadvantages are that only two gray values can be supported, the distortion of the compressed image is large, the performance is poor, and the compression ratio is very low.
Disclosure of Invention
The invention provides a display screen over-drive controller, which can improve the compression ratio, reduce the image distortion and improve the compression performance.
In order to achieve the purpose, the invention adopts the following technical scheme:
a display screen overdrive controller, comprising an image compression and decompression processing unit, wherein the image compression and decompression processing unit is used for compressing and decompressing video data, the input data of the input end of the image compression and decompression processing unit is the video data, the image compression and decompression processing unit is a compression/decompression data processor based on four values or a compression/decompression data processor based on three values, the four values comprise a maximum reference value, a minimum reference value, a first middle reference value and a second middle reference value; the three values include a maximum reference value, a minimum reference value, and an average reference value.
It is further characterized in that the method further comprises the steps of,
the display screen overdrive controller also comprises a frame buffer read-write control unit, a frame buffer unit, a static image detection unit and an overdrive control circuit unit, wherein the frame buffer read-write control unit is used for read-write control of a compressed data frame, the frame buffer unit is used for storing the compressed data frame, the data frame comprises previous frame data and current frame data, the static image detection unit is used for detecting whether the decompressed previous frame data is consistent with the current frame data so as to judge whether the displayed video data is a static image, the image compression and decompression processing unit, the frame buffer read-write control unit and the frame buffer unit are sequentially connected, the image compression and decompression processing unit is further sequentially connected with the static image detection unit and the overdrive control circuit unit, and the overdrive control circuit unit is used for acquiring a required overdrive voltage value, the output data of the output end of the overdrive control circuit is processed video data;
the image compression and decompression processing unit, the frame buffer read-write control unit, the static image detection unit and the overdrive control circuit unit are integrated in the same chip circuit;
the image compression and decompression processing unit maps and encodes the 2x2 partition blocks based on a permutation and combination mode of four values, wherein the permutation and combination of four values comprises 56 combination modes, and the 56 combination modes are position distribution permutation conditions of the four values in the 2x2 partition blocks which are combined in different modes;
the image compression and decompression processing unit realizes the encoding processing of the image data in the video data based on a YCoCg color space, when the color depth of the YCoCg color space is 8 bits, the data format of encoding after 2x2 partition block compression processing is 48 bits, and the compression ratio is 2: 1;
the four-value compression/decompression data processor is used for realizing code compression of the 48-bit data format, based on the YCoCg color space, the YCoCg color space comprises Y, Co and Cg three components, the 48-bit code comprises a 6-bit mapping code and six 7-bit reference value data, and the two compressed maximum reference value and minimum reference value are 7-bit reference value data respectively stored according to the Y, Co and Cg three components;
the image compression and decompression processing unit maps and encodes the 2x2 partitioned blocks based on a permutation and combination mode of three values, wherein the permutation and combination of the three values comprises 26 combination modes, and the 26 combination modes are position distribution permutation conditions of the three values in the 2x2 partitioned blocks combined in different modes;
the image compression and decompression processing unit realizes the encoding processing of the image data in the video data based on a YCoCg color space, when the color depth of the YCoCg color space is 8 bits, the format of the encoded data after the compression processing is 32 bits, and the compression ratio is 3: 1;
the three-valued compression/decompression data processor is used for realizing the compression of 32-bit coding, based on the YCoCg color space, the YCoCg color space comprises Y, Co and Cg three components, the 32-bit coding comprises 6-bit mapping coding, the two compressed maximum reference values and minimum reference values are respectively 7-bit maximum reference values and 7-bit minimum reference values which are reserved according to the Y component, and the Co component and the Cg component respectively only store one 6-bit average reference value data;
a compression/decompression data processor in the image compression and decompression processing unit uses 48-bit compression coding or 32-bit compression coding, in image data processing, the image data is compressed based on the YUV or YCbCr color space, and the data format of the compression coding is consistent with the data format adopted by the YCoCg color space coding compression;
the display is a liquid crystal display.
By adopting the structure of the invention, the following beneficial effects can be achieved: the overdrive controller is used in the display control of a display, the overdrive controller comprises an image compression and decompression processing unit which is used for compressing and decompressing images, the image compression and decompression processing unit is a four-value based compression/decompression data processor or a three-value based compression/decompression data processor, the four-value compression/decompression data processor or the three-value compression/decompression data processor is used for compressing image data with 8-bit color depth, the compressed coded data formats are respectively 48-bit coding and 32-bit coding, the compression ratios respectively reach 2:1 and 3:1, and therefore, compared with the existing compression ratio of the maximum 1.92:1 compression mode, after the overdrive controller is adopted, the compression ratio is increased, thereby improving the image compression performance.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required to be used in the description of the embodiments are briefly introduced below, the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings may be obtained according to the drawings without creative efforts.
FIG. 1 is a system block diagram of a display screen overdrive controller in accordance with the present invention;
FIG. 2 is a block diagram of the circuit structure of the image compression and decompression processing unit of the display screen overdrive controller according to the present invention;
3a and 3b in FIG. 3 are data bit number table diagrams of four-valued block compression coding and three-valued block compression coding, respectively, according to the present invention;
FIG. 4 is a schematic diagram of a position structure of pixels arranged in a permutation and combination manner when the four-valued compression/decompression data processor of the present invention performs image compression or decompression;
FIG. 5 is a mapping code diagram of the image compression based on the four-valued compression/decompression data processor according to the present invention;
FIG. 6 is a schematic diagram of a position structure of pixels arranged in a permutation and combination manner when a three-valued compression/decompression data processor performs image compression or decompression according to the present invention;
FIG. 7 is a mapping code diagram of image compression based on a three-valued compression/decompression data processor according to the present invention.
Wherein the reference numerals include: 6-2 x2 pixel partition block, P11, P12, P21 and P22 are the four-position pixels in the partition.
Wherein the symbols in the drawings illustrate:
FIFO-first in first out queue unit
RGB2 YUV-RGB to YUV color space conversion unit
YUV2 RGB-YUV to RGB color space conversion unit
Bit-one Bit of 2-ary number representation
Bit map-value mapping coding
RV0-minimum reference value
RV1Maximum reference value
RVm0,RVm1Intermediate reference value 0 and intermediate reference value 1 in the case of four values
RVmThe intermediate reference value in the three-valued case.
Detailed Description
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "comprises" and "comprising," and any variations thereof, in the description and claims of the present invention and the above-described drawings, are intended to cover a non-exclusive inclusion, such that a process, method, apparatus, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
In one embodiment of the present invention, an overdrive display controller based on four-value block compression is provided. The overdrive display controller based on four-value block compression, see fig. 1, includes an image compression and decompression processing unit 1, a frame buffer read-write control unit 2, a frame buffer unit 3, a static image detection unit 4, and an overdrive control circuit unit 5.
The image compression and decompression processing unit 1 includes a compression/decompression data processor; the frame buffer unit 3 includes a buffer register for buffering frame data; the frame buffer read-write control unit 2 comprises a reader-writer for performing read-write control on frame data; the static image detection unit 4 comprises a comparator for comparing and judging the previous frame data and the current frame data; the overdrive control circuit unit 5 comprises an overdrive enhancement calculating circuit, the overdrive enhancement calculating circuit comprises a comparator, an adder and a table look-up device, the overdrive enhancement calculating circuit is used for calculating and comparing the current display data and the previous frame data and obtaining a required overdrive voltage value according to the calculation of the table look-up, the adder is used for enhancing the voltage, and the table look-up device is used for performing table look-up operation and obtaining the required overdrive voltage value.
The input end of the image compression and decompression processing unit 1 is the current original display input video data of the display controller, and the output end of the compressed image data is connected with the input end of the frame buffer read-write control unit 2 and is written into the frame buffer unit 3; meanwhile, the compressed image data of the previous frame is read out from the frame buffer unit 3 by the frame buffer read-write control unit 2, and then is sent to the image compression and decompression processing unit 1 for decompression processing; the decompressed image data of the previous frame and the current frame are output to the still image detection unit 4. And the frame buffer read-write control unit 2 is positioned between the image compression and decompression processing unit 1 and the frame buffer unit 3 and is used for read-write control of the compressed data frame. And the frame buffer unit 3 is used for storing the compressed data frame. And a static image detection unit 4, configured to detect whether the decompressed previous frame data is consistent with the current frame, so as to determine whether the displayed video data is a static image.
The image compression and decompression processing unit 1, see fig. 2, includes a first color space conversion module, a first line buffer, a first image compression module, a first FIFO buffer module, a first image decompression module, a second line buffer, and a second color space conversion module, which are connected in sequence; the image compression and decompression processing unit also comprises an image decompression module II, a line buffer memory III and a color space conversion module III, the output end of the first image compression module and the input end of the second image decompression module are respectively connected with a frame buffer read-write control unit, the output end of the image decompression module II is sequentially connected with the image decompression module II, the line buffer memory III and the color space conversion module III, the output ends of the color space conversion module II and the color space conversion module III are both connected with the static image detection unit, the color space conversion module I is used for realizing the conversion between the RGB color space and the YUV color space, the RGB image of each frame of data in the video data is converted into the YUV image, the color space conversion module II and the color space conversion module III are used for realizing the conversion between the YUV color space and the RGB color space, and the decompressed YUV image is converted into the RGB image.
The image compression and decompression processing unit converts the input current original display video data from RGB to YUV format, and the data code stream after image compression coding is written into the frame cache unit by the frame cache read-write control unit; meanwhile, the compressed data code stream of the previous frame of image is read out from the frame cache unit by the frame cache read-write control unit, then is sent into the image decompression processing unit, and is subjected to data decoding processing; the decompressed image data of the previous frame and the current frame are output to a static image detection unit, and whether the decompressed previous frame data and the decompressed current frame are consistent or not is detected to judge whether the displayed video data is a static image or not. And the overdrive control circuit unit (comprising an enhanced voltage calculation circuit) is used for comparing the difference between the current display data and the previous frame data and calculating the required overdrive voltage value according to the lookup table.
An image compression and decompression processing unit, referring to fig. 3, converts an input video signal into a 4-level gray signal in 2 × 2 blocks and performs map coding, wherein only a maximum reference value (denoted by RV0 in fig. 3) and a minimum reference value (denoted by RV 1) among four values remain in compression coding. On a 2 × 2 block, referring to fig. 4 and 5, four values are arranged and combined, the arrangement and combination refers to that the four values are arranged in a combination mode of pixels without intermediate reference values RVm0 and RVm1, pixels including 1 RVm0 or 1 RVm1, pixels including 2 RVm0 or 2 RVm1, and pixels including 1 RVm0 and 1 RVm1, 56 arrangement conditions are totally included, mapping coding performed by the 56 arrangement conditions can cover the position distribution arrangement condition of all the four values, see fig. 4, in fig. 4, reference numeral 6 represents the pixel arrangement condition before image compression, P11, P12, P21 and P22 represent pixels respectively, RV0, RV1, RVm0 and RVm1 represent reference values after pixel compression, and numbers in parentheses represent numbers of the arrangement and combination. Figure 5 is a diagram of an embodiment of mapping coding using the mapping coding method shown in figure 4, coding in fig. 5 represents reference values included in four values, bitmap numbers represent the above 56 arrangements, final bitmap encoding represents encoding after compression based on four values, the number of codes is 1 when all of the four values are the same value, 7 when there are no intermediate reference values RVm0 and RVm1, one RVm0 or 1 RVm1 when the four values are included, the number of codes P-24, when 2 RVm0 or 2 RVm1 are included in the four values, the number of codes P-12, when the four values include 1 RVm0 and 1 RVm1, the number of codes is 12, and as can be seen from the final bitmap, the compressed codes of the image by the four-value compression/decompression data processor of the present application are 6 bits, and all 56 position combination cases can be represented by 6-bit codes.
The image compression and decompression processing unit may also be a three-value-based compression/decompression data processor, and this case can be regarded as a specific example of four-value compression, see fig. 6 and 7. In this case, on a 2 × 2 partition, three values are arranged and combined, where the arrangement refers to that the three values are arranged in a combination manner of a pixel without average reference value RVm, a pixel including 1 average reference value RVm, and a pixel including 2 average reference values RVm, and the total includes 26 cases, see fig. 6, in fig. 6, reference numeral 6 denotes a pixel position arrangement before image compression, P11, P12, P21, and P22 denote pixels, and RV0, RV1, and RVm denote reference values after pixel compression. Fig. 7 shows a specific example of mapping Coding by using the mapping Coding method shown in fig. 6, where Coding in fig. 7 represents a reference value included in four values, bitmap numbers represent the above 26 permutations, final bitmap Coding represents Coding after compression based on three values, when all three values are the same, the Coding number is P1, when there is no intermediate reference value RVm in three values, the Coding number is P7, when three values include one RVm, the Coding number is P12, when three values include 2 RVm, the Coding number is P6, and as can be seen from the final bitmap Coding, the Coding after image compression by using the three-value compression/decompression data processor of the present application is 5 bits, and all 26 position combinations can be represented by using 5-bit Coding.
When a 48-bit compressed code stream format is used, referring to 3a in fig. 3, based on the YCoCg color space, the two compressed maximum and minimum reference values store 7-bit data according to Y, Co and Cg components, respectively, except for 6-bit mapping coding. For input image data with 8-bit color depth, the compression ratio can be 2: 1.
When a 32-bit compressed code stream format is used, referring to 3b in fig. 3, based on a YCoCg color space, 6-bit mapping coding is divided, two 7-bit reference values, namely a maximum reference value and a minimum reference value, after compression are reserved according to a Y component, and only one 6-bit average reference value data is respectively reserved for two Co and Cg components. For input image data with 8-bit color depth, the compression ratio can be 3: 1.
based on color spaces such as YCC, YUV or YCbCr, when the image compression and decompression processing unit uses a 48-bit or 32-bit compressed code stream format, the result is consistent with the above situation.
On the basis of the image compression coding mapping mode, the invention provides an image compression and decompression processing circuit based on a four-value block and an operating principle and a process of image data mapping thereof as follows:
firstly, in 2x2 partitioning, the brightness value Y of each pixel point is according to four values-RV0、RV1、RVm0And RVmlThe classification is carried out by the following process: firstly determining the maximum reference value RV1And a minimum reference value RV0And calculating the middle first reference value RV ″mlAnd a second intermediate reference value RV ″m0：
RV`m1＝RV`0+(RV`1-RV`0)×2/3 (1)
RV`m0＝RV`0+(RV`1-RV`0)/3 (2)
Then according to the principle of proximity, the pixel brightness Y is divided into the levels of corresponding values when being close to the value, and the number N of the pixels corresponding to each reference value in the 2x2 partition block is obtained after the distribution is finished0、N1、Nm0And Nm1。
On the result of luminance grading, the reference value RV needs to be recalculated in order to reduce the influence of quantization noise error of compressed data0And RV1The calculation process is shown as the following formula:
N0RV0+Nm0RVm0+Nm1RVm1+N1RV1＝(∑0Pij)+(∑m0Pij)+(∑m1Pij)+(∑1Pij) (3)
Figure RE-GDA0003487075940000091
Figure RE-GDA0003487075940000092
Figure RE-GDA0003487075940000093
wherein N is0、N1、Nm0And Nm1The number of pixels, SIG P, corresponding to each reference value in a 2x2 partition block, respectivelyijThe Y component brightness value and the Co/Cg component chromatic value of the pixel point in the same reference value range are summed, NtotalIs the number of pixel points of the 2 × 2 blocking block, which is 4 in this embodiment.
In the above-mentioned result of luminance grading, the luminance values of the pixels of the 2 × 2 partition block after grading correspond to a distribution pattern (pattern) in fig. 4, and in fig. 5, each distribution pattern (pattern) corresponds to a code of 6-bit, and the reference value RV calculated as above is added0And RV1Thus, compressed encoded data is obtained. If the Y component and the Co/Cg component adopt a 4:4:4 format, 48-bit compression coding is obtained; if the Y component and the Co/Cg component are in a 4:2:0 format, a 32-bit compression encoding is obtained.
When restoring image data from the compressed encoded data, the above-described procedure is reversed. Firstly, the distribution mode (denoted by pattern in the figure) and the reference value RV corresponding to each pixel brightness value of 2x2 partition blocks after grading are obtained from compression coding0And RV1Then using formula (1) and formula (2) to calculate RVm0And RVm1The value of (c). Then, the grading of the brightness value of each pixel is reversely deduced from the distribution mode (pattern), and then the Y component and the Co/Cg component values of each pixel are obtained according to the corresponding grading of each pixel.
The image compression and decompression processing unit provided by the invention can also be a data processor based on three-value compression/decompression, and the situation is a special case of four-value compression. The image compression and decompression processing circuit based on the three-value block and the working principle and the process of image data mapping thereof provided by the invention are as follows:
firstly, in 2x2 partitioning, the brightness value Y of each pixel point is according to three values-RV0、RV1And RVmThe classification is carried out by the following process: firstly determining the maximum reference value RV1And a minimum reference value RV0And calculating a middle reference value RVm
RV`m＝RV`0+(RV`1-RV`0)/2 (7)
Then according to the principle of proximity, the pixel brightness Y is divided into the levels of corresponding values when being close to the value, and the number N of the pixels corresponding to each reference value in the 2x2 partition block is obtained after the distribution is finished0、N1And Nm。
On the result of brightness gradingTo reduce the effect of quantization noise errors in the compressed data, the reference value RV needs to be recalculated0And RV1The calculation process is shown as the following formula:
N0RV0+NmRVm+N1RV1＝(∑0Pij)+(∑mPij)+(∑1Pij) (8)
(N0+Nm/2)RV0+(N1+Nm/2)RV1＝(∑0Pij)+(∑mPij)+(∑1Pij) (9)
Figure RE-GDA0003487075940000101
Figure RE-GDA0003487075940000102
wherein N is0、N1And NmThe number of pixels, SIG P, corresponding to each reference value in a 2x2 partition block, respectivelyijThe luminance value Y and the chromatic value Co/Cg of the pixel points in the same reference value range are summed, NtotalIs the number of pixel points of the 2 × 2 blocking block, which is 4 in this embodiment.
In the above-mentioned result of the luminance grading, the luminance values of the pixels of the 2 × 2 partition block after grading correspond to a distribution mode (pattern) in fig. 6, and in fig. 7, each distribution mode (pattern) corresponds to a code of 5-bit, and the reference value RV calculated as above is added0And RV1Thus, compressed code stream data is obtained. If the Y component and the Co/Cg component adopt a 4:4 format, a 48-bit code stream is obtained; if the Y component and the Co/Cg component adopt a 4:2:0 format, a 32-bit code stream is obtained.
When restoring image data from compressed code stream data, the above-described procedure is reversed. Firstly, obtaining the corresponding distribution mode (pattern) and distribution mode (pattern) of each pixel brightness value of 2x2 partition blocks after grading from compressed code streamReference value RV0And RV1Then using equation (7) to calculate RVmThe value of (c). Then, the grading of the brightness value of each pixel is reversely deduced from the distribution mode (pattern), and then the Y component and the Co/Cg component values of each pixel are obtained according to the corresponding grading of each pixel.
The overdrive display controller circuit based on four-value block compression or the overdrive display controller circuit based on three-value block compression provided by the invention is preferably applied to the overdrive display controller in a liquid crystal display, can be applied to the circuit controller of an image video transmission and storage system which is simple and has low signal-to-noise ratio requirement, and is particularly suitable for image compression/decompression data processing with low delay and high compression ratio, and as can be seen from fig. 4 to 7, the display screen overdrive controller not only has higher compression ratio and very low delay, but also simplifies the design complexity of the whole circuit scheme and reduces the cost of a circuit system.
The above is only a preferred embodiment of the present application, and the present invention is not limited to the above embodiments. It is to be understood that other modifications and variations directly derived or suggested to those skilled in the art without departing from the spirit and scope of the invention are to be considered as included within the scope of the invention.

Claims (10)

1. A display screen overdrive controller, comprising an image compression and decompression processing unit, wherein the image compression and decompression processing unit is used for compressing and decompressing video data, the input data of the input end of the image compression and decompression processing unit is the video data, the image compression and decompression processing unit is a compression/decompression data processor based on four values or a compression/decompression data processor based on three values, the four values comprise a maximum reference value, a minimum reference value, a first middle reference value and a second middle reference value; the three values include a maximum reference value, a minimum reference value, and an average reference value.
2. The over-drive controller according to claim 1, wherein the over-drive controller further comprises a frame buffer read-write control unit, a frame buffer unit, a static image detection unit, and an over-drive control circuit unit, the frame buffer read-write control unit is configured to control reading and writing of a compressed data frame, the frame buffer unit is configured to store a compressed data frame, the data frame includes previous frame data and current frame data, the static image detection unit is configured to detect whether the decompressed previous frame data and the current frame data are consistent to determine whether the displayed video data is a static image, the image compression and decompression processing unit, the frame buffer read-write control unit, and the frame buffer unit are sequentially connected, and the image compression and decompression processing unit is further sequentially connected to the static image detection unit, The overdrive control circuit unit is used for acquiring a required overdrive voltage value, and output data of an output end of the overdrive control circuit is processed video data.
3. The display screen overdrive controller as claimed in claim 1 or 2, wherein the image compression and decompression processing unit performs mapping coding on the basis of a permutation and combination mode of four values for the 2x2 partition, the permutation and combination mode of four values includes 56 combination modes, and the 56 combination modes are position distribution permutation conditions in which the four values in the 2x2 partition are combined in different modes.
4. A display screen overdrive controller as claimed in claim 3, wherein the image compression and decompression processing unit implements the encoding process of the image data in the video data based on the YCoCg color space, and when the color depth of the YCoCg color space is 8 bits, a 2x2 partition compression process is performed and the encoded data format is 48 bits with a 2:1 compression ratio.
5. A display screen overdrive controller as claimed in claim 4, characterised in that the four value compression/decompression data processor is arranged to effect code compression of the 48-bit data format, based on the YCoCg color space, which comprises Y, Co and Cg three components, the 48-bit code comprising a 6-bit map code, six 7-bit reference value data, two compressed maximum and minimum reference values being such that 7-bit reference value data are stored in the Y, Co and Cg three components, respectively.
6. The display screen overdrive controller as claimed in claim 1 or 2, wherein the image compression and decompression processing unit performs mapping coding on the 2x2 partition based on a three-valued permutation and combination manner, the three-valued permutation and combination includes 26 combination manners, and the 26 combination manners are position distribution permutation conditions in which the three values in the 2x2 partition are combined in different manners.
7. The display screen overdrive controller as claimed in claim 6, wherein the image compression and decompression processing unit implements the encoding process of the image data in the video data based on a YCoCg color space, when the color depth of the YCoCg color space is 8 bits, a 2x2 partition compression process is performed and the encoded data format is 32 bits with a compression ratio of 3: 1.
8. A display screen overdrive controller as claimed in claim 7, characterized in that the three-valued compression/decompression data processor is adapted to implement compression of a 32-bit code, based on the YCoCg color space, which comprises Y, Co and Cg three components, the 32-bit code comprises a 6-bit map code, the two compressed maximum and minimum reference values are respectively 7-bit maximum and minimum reference value data, which are retained according to the Y component, and the Co and Cg components respectively retain only one 6-bit average reference value data.
9. A display screen overdrive controller as claimed in claim 5 or 8, wherein the compression/decompression data processor in the image compression and decompression processing unit uses 48-bit compression coding or 32-bit compression coding, and in the image data processing, the image data is compressed based on the YUV or YCbCr color space, and the data format of the compression coding is consistent with the data format adopted by the YCoCg color space coding compression.
10. A display screen overdrive controller as claimed in claim 9, wherein the display is a liquid crystal display.
CN202111208741.5A 2021-10-18 2021-10-18 Over-drive controller for display screen Pending CN114189687A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114443513A (en) * 2022-04-08 2022-05-06 苏州浪潮智能科技有限公司 Video data reading and writing method and related device
WO2024031212A1 (en) * 2022-08-08 2024-02-15 深圳Tcl新技术有限公司 Display overdrive control method and apparatus, and terminal device and storage medium

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114443513A (en) * 2022-04-08 2022-05-06 苏州浪潮智能科技有限公司 Video data reading and writing method and related device
WO2024031212A1 (en) * 2022-08-08 2024-02-15 深圳Tcl新技术有限公司 Display overdrive control method and apparatus, and terminal device and storage medium

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