CN114188419A

CN114188419A - Memory cell of non-volatile memory

Info

Publication number: CN114188419A
Application number: CN202110917690.7A
Authority: CN
Inventors: 陈英哲; 孙文堂; 黎俊霄; 陈学威
Original assignee: eMemory Technology Inc
Current assignee: eMemory Technology Inc
Priority date: 2020-09-15
Filing date: 2021-08-11
Publication date: 2022-03-15
Also published as: US11877456B2; TWI761268B; US20220085038A1; TW202213724A

Abstract

The invention discloses a storage unit of a non-volatile memory, which comprises a storage element. The memory element is a transistor and has asymmetric spacers. In the memory element, the wider spacer has a longer channel underneath it. When the memory element is programmed, more carriers are injected into the charge trapping layer of the spacer through the longer channel. Therefore, the memory cell of the present invention can perform the programming operation more efficiently and shorten the programming operation time.

Description

Memory cell of non-volatile memory

Technical Field

The present invention relates to a memory cell of a nonvolatile memory, and more particularly, to a memory device (memory device) having an asymmetric spacer in the memory cell of the nonvolatile memory.

Background

Referring to fig. 1, a diagram of a conventional memory device for use in a non-volatile memory is shown. Such a memory element is disclosed in US patent US 7,551,494. The memory element 10 is a P-channel transistor (P-channel transistor).

As shown in fig. 1, the memory device 10 is fabricated between isolation structures 15, and the isolation structures 15 are shallow trench isolation Structures (STI). The memory element 10 includes: an N-type well region (nwell region)11, a control gate layer (gate layer)18, a gate dielectric layer (gate dielectric layer)16, an oxygen-nitrogen-oxygen spacer (ONO spacer)20, a P-type source doped region (P + source doped region)12, and a P-type drain doped region (P + drain doped region) 14.

A gate dielectric layer 16 and a control gate layer 18 are stacked over the surface of the N-well 11. Furthermore, an oxygen-nitrogen-oxygen spacer 20 surrounds sidewalls (side walls) of the gate dielectric layer 16 and the control gate layer 18. Under the surface of the N well 11, the P source doped region 12 is located on one side of the oxygen-nitrogen-oxygen spacer 20, and the P drain doped region 14 is located on the other side of the oxygen-nitrogen-oxygen spacer 20. In other words, the gate dielectric layer 16, the control gate layer 18 and the oxygen-nitrogen-oxygen spacers 20 are located above the surface of the N-well 11 between the P-type source doped region 12 and the P-type drain doped region 14.

Below the surface of the N-well 11, a channel region (channel region) is located between the P-type source doped region 12 and the P-type drain doped region 14. The channel region includes: a first channel (first channel)19, a second channel (second channel)29, and a third channel (third channel) 39. The channel lengths (channel lengths) of the first channel 19, the second channel 29 and the third channel 39 are L1, L2 and L3, respectively. The first channel 19 is located directly under the control gate layer 18, the second channel 29 is located between the P-type drain doped region 14 and the first channel 19, and the third channel 39 is located between the first channel 19 and the P-type source doped region 12.

Further, the oxygen-nitrogen-oxygen spacer 20 includes: a silicon oxide layer (22), a silicon nitride layer (24) and a silicon oxide layer (26). The silicon oxide layer 22 contacts the sidewalls of the gate dielectric layer 16 and the control gate layer 18, and the silicon oxide layer 22 contacts the surface of the N-well 11 and extends to the P-type source doped region 12 and the P-type drain doped region 14. Further, a silicon nitride layer 24 overlies the silicon oxide layer 22, and a silicon oxide layer 26 overlies the silicon nitride layer 24. Basically, the silicon nitride layer 24 is a charge-trapping layer.

Referring to fig. 2, a bias diagram of a conventional memory device performing a programming operation (program operation) is shown. During programming of the memory device 10, the P-type doped drain region 14 receives a drain voltage V_DThe P-type source doped region 12 is floating, and the N-well 11 receives a ground voltage (i.e., V)_NW0V), the control gate layer 18 receives a gate voltage V_G. For example, the drain voltage V_D-3V to-5V, gate voltage V_G0 to 2V. Under the bias conditions described above, the first channel 19 under the control gate layer 18 is turned off. Furthermore, electron-hole pairs (electron-hole pairs) are generated at the junction (junction) between the N-well 11 and the P-type drain doped region 14, and a band-to-band hot electron injection (BBHE) effect is generated, so that electrons are injected from the second channel 29 into the silicon nitride layer 24 on the drain side (drain side).

Of course, other biasing schemes may be used to program the memory element 10 in addition to the BBHE effect. For example, providing a gate voltage V_GTo turn on the first channel 19 and cause a channel hot hole induced hot electron injection (CHHIHE) effect, so that electrons are injected from the second channel 29 into the drain side silicon nitride layer 24. In addition, since electrons are injected from the second channel 29 into the silicon nitride layer 24, the ratio between the length of the injected channel and the total channel length is

In other words, controlling the injection or non-injection of electrons into the silicon nitride layer 24 over the second channel 29 during the programming action allows the memory element 10 to assume two different memory states (storage states). Furthermore, other bias voltages can be provided to perform an erase operation (erase operation) and a read operation (read operation) on the memory device 10, and the detailed operation principle is not described again.

In the present semiconductor process for manufacturing the memory device 10, the oxygen-nitrogen-oxygen spacers 20 contacting the sidewalls of the control gate layer 18 are symmetrical. Therefore, the lengths of the second channel 29 and the third channel 39 in the memory element 10 are almost the same.

Disclosure of Invention

The invention provides a memory cell of a nonvolatile memory, wherein a memory element in the memory cell has an asymmetric spacer. During the programming operation, more carriers can be injected into the charge-trapping layer of the wider spacer. Furthermore, the invention designs a special structure of the memory cell. For example, a longer second channel is designed to increase the ratio between the implanted channel length and the total channel length. Therefore, the programming operation can be performed more efficiently.

The invention relates to a storage unit of a non-volatile memory, which is provided with a storage element, wherein the storage element comprises: a well region; a gate structure formed on a surface of the well region, the gate structure including at least one protrusion; a spacer surrounding a sidewall of the gate structure and contacting the surface of the well region, wherein the spacer comprises a first portion and a second portion; a first doped region and a second doped region formed below the surface of the well region, wherein a channel region is formed between the first doped region and the second doped region, and the channel region comprises a first channel and a second channel; wherein the sidewall of the gate structure comprises a plurality of surfaces, and a first surface of the at least one protrusion is parallel to a channel length direction in the channel region; wherein the first channel is located below the gate structure, the second channel is located between the first channel and the second doped region, and the spacer of the first portion is located above the second channel; during a programming operation, a plurality of carriers are injected into a charge trapping layer in the spacer of the first portion through the second channel.

The invention relates to a memory cell of a non-volatile memory, which comprises: a memory element, comprising: a well region, a first gate structure, a first spacer, a first doped region and a second doped region; the first gate structure is formed on a surface of the well region and includes at least one protrusion; the first spacer surrounds a sidewall of the first gate structure, the first spacer contacts the surface of the well region, and the first spacer includes a first portion and a second portion; the first doped region and the second doped region are formed below the surface of the well region, and a channel region is formed between the first doped region and the second doped region and comprises a first channel and a second channel; the sidewall of the first gate structure includes a plurality of surfaces, and a first surface of the at least one protrusion is parallel to a channel length direction in the channel region; the first channel is located below the first gate structure, the second channel is located between the first channel and the second doped region, and the first spacer of the first portion is located above the second channel; and, a select transistor comprising: the well region, a second gate structure, a second spacer and a third doped region; the second gate structure is formed on the surface of the well region; the second gap wall surrounds one side wall of the second grid structure and contacts the surface of the well region; the third doped region is formed below the surface of the well region; a fourth channel is arranged between the first doped region and the third doped region and is positioned below the second gate structure; during a programming operation, carriers are injected into a charge trapping layer in the first spacer of the first portion through the second channel of the memory element.

In order that the manner in which the above recited and other aspects of the present invention are obtained can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to the appended drawings, in which:

drawings

FIG. 1 is a diagram of a conventional memory device for use in a non-volatile memory;

FIG. 2 is a schematic diagram of the bias voltage for programming a conventional memory device;

FIGS. 3A to 3F are a top view of a manufacturing process and a cross-sectional view along the direction A-B of a memory cell of a non-volatile memory according to a first embodiment of the present invention;

FIG. 3G is a schematic diagram of the bias voltages of the memory cell of the first embodiment during various operations;

FIGS. 4A and 4B are schematic diagrams illustrating a first variation memory device modified according to the first embodiment and bias voltages thereof for various operations;

FIG. 4C is a schematic view of a second variation memory element modified from the first embodiment;

FIG. 4D is a schematic view of a memory element of a third variation modified from the first embodiment;

FIG. 4E is a schematic view of a fourth variation memory element modified from the first embodiment;

FIG. 4F is a schematic view of a fifth variation memory element modified from the first embodiment;

FIGS. 5A and 5B are a top view and a cross-sectional view along the direction A-B of a memory cell of a nonvolatile memory according to a second embodiment of the present invention;

FIG. 5C is a schematic diagram of the bias voltages of the memory element in the memory cell of the second embodiment during various operations;

FIG. 5D is a schematic diagram of the bias voltages of the N-channel transistor as a memory device for various operations;

FIG. 5E is a schematic view of a second variation memory element modified from the second embodiment;

FIGS. 6A and 6B are a top view and a cross-sectional view along the direction A-B of a memory cell of a nonvolatile memory according to a third embodiment of the present invention; and

FIG. 7A and FIG. 7B are a top view and a cross-sectional view along the direction A-B of a memory cell of a nonvolatile memory according to a fourth embodiment of the present invention.

Description of the symbols

10 memory element

11: N type trap area

12,14 doped region

15 isolation structure

16 gate dielectric layer

18 control gate layer

19 first channel

20 spacer

22,26 silicon oxide layer

24 silicon nitride layer

29 second channel

39 third channel

300,300a,300c,300d,300e,300f,300g,300h,500 e storage elements

310,310a,310d,310e,310f,610 well regions

320,340,320a,340a,320c,320d,340d,320e,340e,320f,340f doped region

322,342,322d,342d,322e,342e,322f,342f,641,652 metal electrodes

330,330d,330e,330f,630,670 spacer

332,336,632,636,672,676 silicon oxide layer

334,634,674 silicon nitride layer

380,660,680 Gate Structure

380a,380b,410 projection

380c,380d,411 surface

382,662,682 Gate dielectric layer

384,384d,384e,384f,664,684 control gate layer

386 is an opening

391,691 first channel

392,692 second channel

393,693 third channel

400,622,652 extension part

502,502e,702 auxiliary electrode

504,704 dielectric layer

620,640,650 doped region

694 third channel

Detailed Description

Referring to fig. 3A to fig. 3F, a top view of a manufacturing process of a memory cell of a nonvolatile memory according to a first embodiment of the present invention and a cross-sectional view along the direction a-B are shown.

As shown in fig. 3A and 3B, a C-shaped gate structure 380 is formed over the well region 310. The gate structure 380 has two protrusions (protrusions) 380a,380b parallel to each other, and the two

protrusions

380a,380b have surface (surfaces) 380c,380d facing each other. In other words, the two

protrusions

380a,380b can form a C-shaped gate structure 380 and define an opening (notch) 386. Furthermore, the gate structure 380 includes a gate dielectric layer 382 and a control gate layer 384. The gate dielectric 382 is formed on the surface of the well 310, and the control gate layer 384 covers the gate dielectric 382. The control gate layer 384 is a polysilicon (polysilicon) control gate layer, and the gate dielectric layer 382 is a silicon oxide layer.

As shown in fig. 3C and 3D, a spacer 330 is formed around the sidewall (side wall) of the gate structure 380. Wherein the spacer 330 is an oxide-nitride-oxide spacer (ONO spacer). The spacer 330 includes: a silicon oxide layer 332, a silicon nitride layer 334, and a silicon oxide layer 336. The silicon oxide layer 332 contacts the sidewall of the gate structure 380, and the silicon oxide layer 332 contacts the surface of the well 310. A silicon nitride layer 334 overlies the silicon oxide layer 332. A silicon oxide layer 336 overlies the silicon nitride layer 334. The silicon nitride layer 334 is a charge-trapping layer (charge-trapping layer).

According to the embodiment of the present invention, during the spacer 330 process, since the material of the spacer 330 simultaneously fills and contacts three surfaces (i.e., the two surfaces 380C and 380d plus the surface between the two surfaces 380C and 380 d) of the opening 386 of the C-shaped gate structure 380, more material of the spacer 330 remains at the opening 386 of the C-shaped gate structure 380 after etching, so that asymmetric spacers 330 are formed at two sides of the gate structure 380. In other words, the spacer 330 includes a right portion and a left portion, the right portion and the left portion have different widths, and the right portion has a higher physical height than the left portion. The right partial spacer 330 is located on the two

projections

380a,380b and contacts three surfaces of the C-shaped gate structure 380 at the opening 386. Therefore, as shown in fig. 3D, the width of the right partial spacer 330 having different widths is greater than that of the left partial spacer 330.

As shown in fig. 3E and 3F, a source/drain doping process is performed to form a first doping region 320 and a second doping region 340 on two sides of the gate structure 380 and the spacer 330. The memory device 300 is completed by connecting the metal electrodes 322,342 to the first doped region 320 and the second doped region 340, respectively. The first doped region 320 and the second doped region 340 are P-type doped regions, and the well 310 is an N-type well. In other words, the memory cell of the nonvolatile memory according to the first embodiment of the present invention includes a memory element 300, the memory element 300 is a P-channel transistor (P-channel transistor), the first doped region 320 is a source (source), and the second doped region 340 is a drain (drain).

As shown in fig. 3E and 3F, a channel region (channel region) is located between the first doped region 320 and the second doped region 340 under the surface of the well region 310. Two

surfaces

380c and 380d of the gate structure 380 are parallel to the channel length direction (length direction) of the channel region. The channel region includes: a first channel 391, a second channel 392, and a third channel 393. The channel lengths of the first channel 391, the second channel 392 and the third channel 393 are L1, L2 and L3, respectively. The first channel 391 is located directly below the gate structure 380 between the second channel 392 and the third channel 393. The second channel 392 is located between the second doped region 340 and the first channel 391. The third channel 393 is located between the first doped region 320 and the first channel 391. In addition, the right-side partially wider spacers 330 are located above the second channels 392 and the left-side partially narrower spacers 330 are located above the third channels 393.

In embodiments of the present invention in which the memory element 300 has a C-shaped gate structure 380, i.e., three surfaces in the sidewalls of the gate structure 380 are adjacent to the second trench 392, more material of the spacers 330 may remain, resulting in wider spacers 330. As shown in fig. 3F, the silicon oxide layer 332 of the spacer 330 contacts the sidewall of the gate structure 380, and the silicon oxide layer 332 contacts the surface of the well 310 and extends to the first doped region 320 and the second doped region 340, respectively. An asymmetric spacer 330 is formed by etching a silicon nitride layer 334 and a silicon oxide layer 336 over a silicon oxide layer 332. The second channel 392 and the third channel 393 have different lengths due to the spacers 330 having different widths formed on both sides of the gate structure 380. According to an embodiment of the present invention, the length of the second channel 392 is greater than the length of the third channel 393, and the length of the second channel 392 is equal to or less than three times the length of the third channel 393. That is, the width of the right spacer 330 is greater than the width of the left spacer 330, and the width of the right spacer 330 is less than 3 times the width of the left spacer 330. Furthermore, since the right spacer 330 is wider, the right spacer 330 has a longer silicon nitride layer 334 for storing more electrons.

Accordingly, since the right-side partial spacer 330 is physically higher, more dopant ions (dopants) are blocked during the source/drain doping process to prevent formation of the second doped region 340 below the silicon oxide layer 332, thereby increasing the length of the second channel 392 and providing the memory device 300 with a longer second channel 392, the ratio of the implanted channel length to the total channel length (i.e.,

) It will increase. When the memory device 300 is programmed, more carriers (carriers) are injected into the silicon nitride layer 334 of the spacer 330 through the second channel 392. Therefore, the memory device 300 of the present invention can perform the programming operation more efficiently and shorten the programming operation time.

Referring to fig. 3G, a schematic diagram of bias voltages of the memory cell of the first embodiment during various operations is shown. Wherein the first doped region 320 receives the source line voltage V_SLThe second doped region 340 receives the bit line voltage V_BLThe control gate layer 384 receives a gate voltage V_GThe well 310 receives a well voltage (V)_NW). It is noted that fig. 3E and 3F are simplified diagrams and are connected to the control gate layer 384 for receiving the gate voltage V_GThe contact points are omitted.

When the memory element 300 is programmed by the band-to-band hot electron injection effect (BBHE effect), the source line voltage V is set to be equal to the source line voltage V_SLIs floating, the gate voltage V_GA bit line voltage V of 0V or more_BLis-6V, well region voltage V_NWIs 0V. Due to the gate voltage V_GGreater than the bit line voltage V_BLThe first channel 391 under the gate structure 380 is turned off. Furthermore, electron-hole pairs (electron-hole pairs) are generated at the junction (junction) between the well region 310 and the second doped region 340, and a BBHE effect occurs, so that electrons are injected from the second channel 392 into the silicon nitride layer 334 on the drain side (drain side). That is, electrons are injected from the second channel 392 into the charge trapping layer in the wider spacer 330 near the second doped region 340 side.

When programming the memory element 300 using channel hot electron injection (CHE) effect, the source line voltage V is applied_SL Is 0V, gate voltage V_Gis-1V, bit line voltage V_BLis-6V, well region voltage V_NWIs 0V. Due to the gate voltage V_GIs smaller than the source line voltage V_SLThe first channel 391 under the gate structure 380 is turned on (turn on), and a channel region between the first doped region 320 and the second doped region 340 is turned on (channel region), so as to generate a programming current (programming current). The CHE effect occurs when electrons pass through the second channel 392, so that electrons are injected from the second channel 392 into the silicon nitride layer 334 on the drain side (drain side). That is, electrons are injected from the second channel 392 into the charge trapping layer in the wider spacer 330 near the second doped region 340 side.

When erasing operation (ERS) is performed on the memory device 300 by using channel hot hole injection (CHH effect), the source line voltage V is set_SL Is 0V, gate voltage V_Gis-6V, bit line voltage V_BLis-6V, well region voltage V_NWIs 0V. Due to the gate voltage V_GIs smaller than the source line voltage V_SLThe first channel 391 under the gate structure 380 is turned on (turn on), and the channel region between the first doped region 320 and the second doped region 340 is turned on (channel region). When the holes pass through the second channel 392, CHH effect occurs, such that the holes are injected from the second channel 392 into the silicon nitride layer 334 on the drain side (Drainside), and the electrons and holes in the silicon nitride layer 334 are combined to complete the erase operation (ERS).

By usingWhen performing an erase operation (ERS) on the memory device 300 by Fowler-Nordheim Tunneling (FN effect)_SLIs +6V, gate voltage V_Gis-6V, bit line voltage V_BLIs +6V, well region voltage V_NWIs + 6V. Due to the gate voltage V_GLess than well region voltage V_NWThe FN effect occurs, causing electrons in the silicon nitride layer 334 to exit (project) from the silicon nitride layer 334 to the well 310 to complete the erase operation (ERS).

When the memory device 300 is Erased (ERS) by band-to-band hot hole injection (BBHH effect)_SLIs a floating, gate voltage V_Gis-6V, bit line voltage V_BLis-6V, well region voltage V_NWIs 0V. Due to the gate voltage V_GAnd bit line voltage V_BLat-6V, the first channel 391 under the gate structure 380 is turned off. Furthermore, the junction (junction) between the well region 310 and the second doped region 340 generates electron-hole pairs (electron-hole pairs) and generates the interband hot hole injection effect (BBHH effect). Therefore, holes are injected into the silicon nitride layer 334 on the drain side (drain side) from the second trench 392, so that electrons and holes in the silicon nitride layer 334 are combined to complete the erase operation (ERS).

When a READ operation (READ) is performed on the memory device 300, the source line voltage V_SLis-1V, the gate voltage V_Gis-1V, bit line voltage V_BLIs 0V, well region voltage V_NWIs 0V. At this time, a channel region (channel region) between the first and

second doping regions

320 and 340 is turned on and a read current (read current) is generated. Basically, when electrons are stored in the silicon nitride layer 334 of the memory device 300, the read current is relatively large and may be considered as the first memory state of the memory device 300. Conversely, when no electrons/holes are stored in the silicon nitride layer 334 of the memory device 300, the read current is relatively small and is considered as the second memory state of the memory device 300. In other words, the storage state of the memory element 300 can be determined according to the magnitude of the read current.

Basically, the biasing provided by the various operations of the memory element 300 in the memory cell described above is only exemplary and not intended to limit the present invention. One skilled in the art can modify the bias voltages for various operations and perform programming, erasing, and reading operations on the memory device 300.

The memory element in the memory cell according to the first embodiment of the present invention is not limited to a P-channel transistor (P-channel transistor), and the memory element in the memory cell according to the first embodiment may be an N-channel transistor (N-channel transistor).

Referring to fig. 4A, a first variation memory device modified according to a first embodiment is shown. The first change type memory element 300a in the memory cell is an N-channel transistor. Fig. 4B is a schematic diagram of the bias voltages for the first variation memory device performing various operations. The memory element 300a is similar to the memory element 300 in structure, and will be described below.

As shown in fig. 4A, the memory element 300a in the memory cell includes: well 310a, gate dielectric 382, control gate 384, spacers 330, first doped region 320a and second doped region 340 a. The spacer 330 includes: a silicon oxide layer 332, a silicon nitride layer 334, and a silicon oxide layer 336. In addition, the first doped region 320a and the second doped region 340a are N-type doped regions, and the well 310a is a P-type well. Similarly, a channel region (channel region) is located between the first doped region 320a and the second doped region 340a under the surface of the well region 310 a. The channel region includes: a first channel 391, a second channel 392, and a third channel 393.

Since the memory element 300a has a C-shaped gate structure, three surfaces of the sidewall of the gate structure are adjacent to the second channel 392. Therefore, spacers 330 having different widths may be formed on both sides of the gate structure, so that the lengths of the second channel 392 and the third channel 393 are different. According to an embodiment of the present invention, the length of the second channel 392 is greater than the length of the third channel 393, and the length of the second channel 392 is equal to or less than three times the length of the third channel 393.

As shown in FIG. 4B, the first doped region 320a receives the source line voltage V_SLThe second doped region 340a receives the bit line voltage V_BLThe control gate layer 484 receives a gate voltage V_GThe well 310a receives a well voltage V_PW。

When the memory cell 300a is programmed by the band-to-band hot hole injection (BBHH) effect, the source line voltage V is applied_SLIs floating, the gate voltage V_GA voltage of 0V or less, a bit line voltage V_BLIs +6V, well region voltage V_PWIs 0V. Due to the gate voltage V_GLess than the bit line voltage V_BLThe first channel 391 is turned off. Furthermore, electron-hole pairs (electron-hole pairs) are generated at the junction (junction) between the well region 310a and the second doped region 340a, and the BBHH effect occurs, so that holes are injected from the second channel 392 into the silicon nitride layer 334 on the drain side (drain side). That is, holes are injected from the second channel 392 into the charge trapping layer in the wider spacer 330 near the second doped region 340 side.

When the memory device 300a is Erased (ERS) by channel hot electron injection (CHE), the source line voltage V is set_SL Is 0V, gate voltage V_GIs +6V, bit line voltage V_BLIs +6V, well region voltage V_PWIs 0V. Due to the gate voltage V_GGreater than the source line voltage V_SLThe first channel 391 is turned on, and a channel region between the first doped region 320a and the second doped region 340a is turned on. When electrons pass through the second channel 392, the CHE effect occurs, so that electrons are injected from the second channel 392 into the silicon nitride layer 334 on the drain side (drain side), and the electrons and holes in the silicon nitride layer 334 are combined to complete the erasing operation.

When a READ operation (READ) is performed on the memory element 300a, the source line voltage V_SLIs +1V, gate voltage V_GIs +1V, bit line voltage V_BLIs 0V, well region voltage V_PWIs 0V. At this time, a channel region (channel region) between the first and

second doping regions

320a and 340a is turned on and a read current (read current) is generated. Therefore, the storage state of the storage element 300a can be determined according to the magnitude of the read current.

Furthermore, the gate structure of the memory element in the first embodiment of the memory cell of the present invention is not limited to a C-shaped (C-shaped) gate structure, and those skilled in the art can modify the C-shaped gate structure into other gate structures and fabricate an asymmetric spacer.

Referring to fig. 4C, a second variation memory device modified according to the first embodiment is shown. Compared to the memory device 300 in fig. 3F, the first doped region 320C in the memory device 300C in fig. 4C further includes an extension portion 400, which is a Lightly Doped Drain (LDD) region. That is, a Lightly Doped Drain (LDD) process is additionally performed on the narrow spacer 300 side. When the extension 400 of the first doped region 320c is completed, the third channel under the narrower spacer 300 will disappear, such that the ratio between the implanted channel length and the total channel length (i.e.,

) And (4) increasing. Thus, the memory device 300c can be programmed more efficiently. Notably, the side of the wider spacer 300 may be left without LDD process, i.e., the second channel 392 may be present without disappearance. Since the second channel 392 is still present, electrons are injected into the drain side silicon nitride layer 334 through the second channel 392.

Referring to fig. 4D, a third variation memory device modified according to the first embodiment is shown. The memory element 300d has an L-shaped control gate layer 384d, i.e., the memory element 300d has an L-shaped gate structure. The gate structure has a protrusion 410, and a surface 411 of the protrusion 410 is parallel to a channel region length direction of the channel region. Furthermore, the spacer 330d surrounds the sidewall of the gate structure. After the source/drain doping process, the first doped region 320d and the second doped region 340d formed in the well 310d are respectively located at two sides of the spacer 330 d. The

metal electrodes

322d,342d are connected to the first doped region 320d and the second doped region 340d, respectively, thereby completing the memory device 300 d.

Basically, when the spacer 330d is formed, the material of the spacer 330d is filled in the corner (corner) of the L-shaped gate structure, so that more material of the spacer 330d remains at the corner of the L-shaped gate structure after etching. That is, the spacer 330d formed on the right side portion contacts the surface 411 of the protrusion 410 and contacts the other sidewall surface perpendicular to the surface 411 in the L-shaped gate structure. Therefore, spacers 330d having different widths are formed on the left and right sides of the L-shaped gate structure.

In addition, the cross-sectional view of the memory element 300d along the line A-B is similar to that of FIG. 3F and will not be described again. Furthermore, since the memory device 300d has an L-shaped gate structure, two surfaces of the sidewall of the gate structure are adjacent to the second channel.

Referring to fig. 4E, a fourth variation memory device according to the first embodiment is shown. In contrast to the memory element 300 of FIG. 3E, the gate structure of the memory element 300E also extends to the neighboring

memory elements

300g,300 h. That is, the

memory elements

300e,300 g,300h share (shared) the control gate layer 384e, and the structures of the

memory elements

300e,300 g,300h are identical.

Similarly, more material of the spacer 330e remains at the opening of the control gate layer 384e of the memory element 300e, so that spacers 330e with different widths are formed at two sides of the gate structure. Furthermore, the first doped region 320e and the second doped region 340e formed after the source/drain doping process are respectively located at two sides of the spacer 330 e. The

metal electrodes

322e,342e are connected to the first doped region 320e and the second doped region 340e, respectively, completing the memory element 300 e.

In addition, the cross-sectional view of the memory element 300e along the line A-B is similar to that of FIG. 3F and will not be described again. Furthermore, since the memory element 300e has a gate structure of the C-type, three surfaces of the sidewall of the gate structure are adjacent to the second channel.

Referring to fig. 4F, a fifth variation memory device according to the first embodiment is shown. The channel width (channel width) of the memory element 300f is narrower than that of the memory element 300 of fig. 3E. That is, the present invention can design a narrower channel according to the process specification of the semiconductor to reduce the size (size) of the memory element 300 f.

Similarly, more material of the spacer 330f remains at the opening of the control gate layer 384f of the memory element 300f, so that spacers 330f with different widths are formed at two sides of the gate structure. Furthermore, the first doped region 320f and the second doped region 340f formed after the source/drain doping process are respectively located at two sides of the spacer 330 f. The

metal electrodes

322f,342f are connected to the first doped region 320f and the second doped region 340f, respectively, completing the memory element 300 f.

In addition, the cross-sectional view of the memory element 300F along the line A-B is similar to that of FIG. 3F and will not be described again. Furthermore, since the memory element 300f has a gate structure of the C-type, three surfaces of the sidewall of the gate structure are adjacent to the second channel.

As can be seen from the above description, in order to provide the memory device with asymmetric spacers 330. The memory device of the present invention has a specially shaped gate structure with multiple sides on the sidewalls of the gate structure, and the gate structure 380 is designed such that at least two surfaces of the sidewalls of the gate structure are adjacent to the second channel, thereby forming a wider spacer above the second channel.

Referring to fig. 5A and 5B, a top view and a cross-sectional view along the direction a-B of a memory cell of a nonvolatile memory according to a second embodiment of the present invention are shown. The memory cell of the second embodiment includes a memory device 500. the memory device 500 is based on the memory device 300 of the first embodiment and further includes an auxiliary electrode 502 for enhancing the programming and erasing efficiency of the memory device 500. That is, the memory element 500 of the second embodiment memory cell further has an auxiliary electrode 502. Only the auxiliary electrode 502 is described below, and the other structures of the memory element will not be described.

The auxiliary electrode 502 is located over the spacer 330 between the gate structure 380 and the second doped region 340. That is, the auxiliary electrode 502 is located above the wider spacer 330. Furthermore, a dielectric layer (dielectric layer)504 is located between the auxiliary electrode 502 and the spacer 330, and the dielectric layer 504 may be a Resistance Protection Oxide layer (RPO layer). In addition, the dielectric layer 504 is not shown in fig. 5A for simplicity of drawing.

Fig. 5C is a schematic diagram showing bias voltages of the memory element in the memory cell of the second embodiment during various operations. The difference is only that the auxiliary voltage V is increased compared to FIG. 3G_A. In the following, only the auxiliary voltage V will be explained_AOther biases will not be described in detail.

As shown in FIG. 5C, when the memory element 500 is a P-channel transistor, the auxiliary electrode 502 receives an auxiliary voltage V_A. During programming operation, the auxiliary voltage V_AElectron injection into the silicon nitride layer 334 may be controlled. In addition, during the erasing operation, the auxiliary voltage V_AHole injection into silicon nitride layer 334 may be controlled or electrons may be controlled to exit silicon nitride layer 334.

As shown in FIG. 5C, when programming operation (PGM) is performed using the BBHE effect for the memory element 500 of the P-channel transistor, the auxiliary voltage V is set to be higher than the reference voltage V_AIs + 3V. When programming operation (PGM) is performed by using CHE effect, the auxiliary voltage V is set_Ais-3V. When performing an erase operation (ERS) by using the CHH effect, the auxiliary voltage V_Ais-3V. When performing an erase operation (ERS) by FN tunneling effect, the auxiliary voltage V_Ais-6V. When performing an erase operation (ERS) using the BBHH effect, the auxiliary voltage V_Ais-3V. During read operation, the auxiliary voltage V_Ais-1V.

Basically, the biasing provided by the various operations of the memory element 500 in the memory cell described above is only exemplary and not intended to limit the present invention. One skilled in the art can modify the bias voltages for various operations and perform programming, erasing, and reading operations on the memory device 500.

In addition, the memory element according to the second embodiment of the present invention is a P-channel transistor (P-channel transistor). Those skilled in the art can also modify the first variation memory element according to the second embodiment. For example, the first variation storage element is an N-channel transistor (N-channel transistor). Since the structure of the memory element of the N-channel transistor is the same as that of fig. 5B, the description thereof is omitted.

Referring to FIG. 5D, an N-channel transistor is shown as a memory deviceBias diagrams for various operations. When Programming (PGM) is performed using BBHH effect for a memory element of an N-channel transistor, an auxiliary voltage V is applied_ALess than or equal to 0V; when using CHE effect to perform erase operation (ERS), the auxiliary voltage V_AIs + 6V; during read operation, the auxiliary voltage V_AIs + 1V.

Referring to fig. 5E, a second variation memory device modified according to the second embodiment is shown. In contrast to the memory device 500 of FIG. 5B, the auxiliary electrode 502e of the memory device 500e directly contacts the spacer 330. For example, the auxiliary electrode 502e may directly contact the silicon oxide layer 332, the silicon nitride layer 334 and the silicon oxide layer 336 of the spacer 330. Since the material of the spacer 330 is non-conductive. Therefore, when the auxiliary electrode 502e contacts the spacer 330, the memory device 500e can still perform the programming operation, the erasing operation and the reading operation. The bias voltages for the various operations are similar to those in fig. 5C and 5D, and are not described again here.

Of course, the present invention may also modify the second embodiment storage element. For example, the gate structure is modified so that the storage element has an L-shaped gate structure as shown in FIG. 4C, or a gate structure extending to an adjacent storage element as shown in FIG. 4D. Of course, the channel width of the storage element may also be modified as shown in FIG. 4E. In addition, the auxiliary electrodes 520 and 520E in fig. 5B and 5E may be in contact with the control gate layer 384.

Referring to fig. 6A and 6B, a top view and a cross-sectional view along the direction a-B of a memory cell of a nonvolatile memory according to a third embodiment of the present invention are shown. Compared to the first embodiment memory cell having only a single memory element 300, the third embodiment memory cell includes a memory element and a select transistor (select transistor). Basically, the manufacturing process of the third embodiment is similar to that of the first embodiment, and is not repeated here.

The memory element includes: well region 610, first doped region 620, second doped region 640, gate structure 680 and spacers 630. The gate structure 680 includes: gate dielectric layer 682, control gate layer 684. The spacer 630 is an oxygen-nitrogen-oxygen spacer (ONO spacer) including: silicon oxide layer 632, silicon nitride layer 634 and silicon oxide layer 636.

In the memory device, a well region (well region)610 has a first doped region 620 and a second doped region 640 under the surface, and a metal electrode 642 contacts the second doped region 640. The gate structure and the spacers 630 are formed above the surface of the well 610 and between the first doped region 620 and the second doped region 640. A C-shaped (C-shaped) gate structure contacts the upper surface of the well 610. The spacer 630 surrounds the sidewall (side wall) of the gate structure. The silicon oxide layer 632 contacts the sidewall of the gate structure, and the silicon oxide layer 632 contacts the surface of the well 610 and extends to the first doped region 620 and the second doped region 640. A silicon nitride layer 634 overlies the silicon oxide layer 632. A silicon oxide layer 636 overlies the silicon nitride layer 634. The silicon nitride layer 334 is a charge-trapping layer (charge-trapping layer).

Furthermore, a channel region (channel region) is located between the first doped region 620 and the second doped region 640 under the surface of the well 610. The channel region includes: a first channel 691, a second channel 692, and a third channel 693. The first channel 691 is located directly below the gate structure, the second channel 692 is located between the second doped region 640 and the first channel 691, and the third channel 693 is located between the first doped region 620 and the first channel 691. In addition, the right wider portion of the spacer 630 is located above the second channel 692, and the left narrower portion of the spacer 630 is located above the third channel 693.

According to the embodiment of the invention, since the three surfaces of the sidewall of the C-shaped gate structure are adjacent to the second channel 692, spacers 630 with different widths are formed on two sides of the gate structure, so that the length of the second channel 692 is greater than the length of the third channel 693, and the length of the second channel 692 is less than or equal to three times the length of the third channel 693.

The selection transistor includes: well region 610, first doped region 620, third doped region 650, gate structure 660 and spacer 670. The gate structure includes: gate dielectric layer 662, and select gate layer 664. The spacer 670 is an oxygen-nitrogen-oxygen spacer (ONO spacer) that includes: silicon oxide layer 672, silicon nitride layer 674, and silicon oxide layer 676.

A Lightly Doped Drain (LDD) process is added during the fabrication of the select transistor, such that the first doped region 620 and the third doped region 650 each include an

extension portion

622 and 652, and the

extension portions

622 and 652 are located below the spacer 670. The

extensions

662 and 652 are lightly doped drain (LDD regions).

Thus, in the select transistor, the well region (well region)610 has the first doped region 620 and the third doped region 650 under the surface, and the metal electrode 652 contacts the third doped region 650. The gate structure is formed over the surface of the well 610, between the first doped region 620 and the third doped region 650. The gate structure contacts the upper surface of the well 610. Spacers 670 surround the sidewalls (side walls) of the gate structure and contact the surface of the well. Furthermore, a fourth trench 694 is formed between the first doped region 620 and the second doped region 650 under the surface of the well 610.

According to the third embodiment of the present invention, after the selection transistor is turned on by providing a proper bias voltage, the memory device can be programmed, erased and read. Furthermore, since there is no channel under the spacer 670 of the select transistor, no carriers are injected into the spacer 670 of the select transistor during the programming operation.

Similarly, the memory element and the selection transistor in the memory cell according to the third embodiment of the present invention may be both P-channel transistors (P-channel transistors) or both N-channel transistors (N-channel transistors).

Of course, the present invention can also modify the memory element in the third embodiment. For example, the gate structure is modified so that the storage element has an L-shaped gate structure as shown in FIG. 4C, or a gate structure extending to an adjacent storage element as shown in FIG. 4D. Of course, the channel width of the storage element may also be modified as shown in FIG. 4E.

Referring to fig. 7A and 7B, a top view and a cross-sectional view along the direction a-B of a memory cell of a nonvolatile memory according to a fourth embodiment of the present invention are shown. The memory cell of the fourth embodiment includes a selection transistor and a memory element, and an auxiliary electrode (assisted electrode)702 is further designed on the basis of the memory cell of the third embodiment to enhance the programming and erasing efficiency of the memory element. Only the auxiliary electrode 702 is described below, and other structures of the memory cell are not described in detail. In addition, the dielectric layer 704 is not shown in fig. 7A for simplicity of drawing.

The auxiliary electrode 702 is located over the spacer 630 between the gate structure of the memory element and the second doped region 640. That is, the auxiliary electrode 702 is located above the wider spacers 630. Furthermore, a dielectric layer (dielectric layer)704 is located between the auxiliary electrode 702 and the spacer 630, and the dielectric layer 704 may be a Resistance Protection Oxide layer (RPO layer).

According to the fourth embodiment of the present invention, after the selection transistor is turned on by providing an appropriate bias voltage, the memory device can be programmed, erased and read. Furthermore, since there is no channel under the spacer 670 of the select transistor, no carriers are injected into the spacer 670 of the select transistor during the programming operation.

Similarly, the memory element and the selection transistor in the memory cell according to the fourth embodiment of the present invention may be both P-channel transistors (P-channel transistors) or both N-channel transistors (N-channel transistors).

Of course, the present invention can also modify the memory element in the fourth embodiment. For example, the gate structure is modified so that the storage element has an L-shaped gate structure as shown in FIG. 4C, or a gate structure extending to an adjacent storage element as shown in FIG. 4D. Of course, the channel width of the storage element may also be modified as shown in FIG. 4E. In addition, the auxiliary electrode 702 may be in contact with the control gate layer 684. Alternatively, the auxiliary electrode 702 may contact the spacer 630.

In summary, the present invention provides a memory cell of a non-volatile memory. The memory element in the memory cell is a transistor and the memory element has asymmetric spacers. In the memory element, the wider spacer has a longer channel underneath it. When the memory element is programmed, more carriers are injected into the charge trapping layer of the spacer through the longer channel. Therefore, the memory cell of the present invention can perform the programming operation more efficiently and shorten the programming operation time.

Furthermore, the memory device of the present invention has a specially shaped gate structure having a sidewall with a plurality of sides, and the gate structure is designed such that at least two surfaces of the sidewall of the gate structure are adjacent to the second trench to form a wider spacer.

In view of the above, while the present invention has been disclosed in connection with preferred embodiments, it is not intended to be limited thereto. Various modifications and alterations can be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the protection scope of the present invention should be subject to the definition of the appended claims.

Claims

1. A memory cell of a non-volatile memory, the memory cell having a memory element, the memory element comprising:

a well region;

a gate structure formed on the surface of the well region and including at least one protrusion;

a spacer surrounding a sidewall of the gate structure and contacting the surface of the well region, wherein the spacer comprises a first portion and a second portion; and

a first doped region and a second doped region formed below the surface of the well region, wherein a channel region is formed between the first doped region and the second doped region, and the channel region comprises a first channel and a second channel;

wherein the sidewall of the gate structure comprises a plurality of surfaces, and the first surface of the at least one protrusion is parallel to a channel length direction in the channel region;

wherein the first channel is located below the gate structure, the second channel is located between the first channel and the second doped region, and the spacer of the first portion is located above the second channel;

during programming, a plurality of carriers are injected into the charge trapping layer in the spacer of the first portion through the second channel.

2. The memory cell of claim 1, wherein the channel region further comprises a third channel, the third channel is located between the first channel and the first doped region, the spacer of the second portion is located above the third channel, and the length of the second channel is greater than the length of the third channel.

3. The memory cell of claim 1, wherein the spacer of the first portion surrounds the at least one protrusion, the spacer of the first portion has a first width, the spacer of the second portion has a second width, the first width is greater than the second width, and the first width is less than or equal to three times the second width.

4. The memory cell of claim 1, wherein the spacer comprises a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer, the first silicon oxide layer is in contact with the surface of the well region and the sidewall of the gate structure, the first silicon oxide layer is over the second channel, the silicon nitride layer covers the first silicon oxide layer, the second silicon oxide layer covers the silicon nitride layer, and the silicon nitride layer is the charge trapping layer.

5. The memory cell of claim 1, wherein the sidewall of the gate structure has two surfaces adjacent to the second channel.

6. A memory cell of a non-volatile memory as claimed in claim 1, wherein the memory element further comprises: the auxiliary electrode is located above the spacer of the first portion, and the dielectric layer is located between the auxiliary electrode and the spacer of the first portion.

7. The memory cell of claim 6, wherein the auxiliary electrode contacts the control gate layer on the gate structure.

8. A memory cell of a non-volatile memory as claimed in claim 1, wherein the memory element further comprises: the auxiliary electrode is in contact with the spacer of the first portion.

9. The memory cell of claim 8, wherein the auxiliary electrode contacts the control gate layer on the gate structure.

10. The memory cell of claim 1, wherein the gate structure comprises a first protrusion and a second protrusion, a surface of the first protrusion and a surface of the second protrusion face each other and define an opening of the gate structure, and the spacer of the first portion contacts the surface of the first protrusion and the surface of the second protrusion.

11. A memory cell of a non-volatile memory, the memory cell comprising:

a memory element, comprising: the semiconductor device comprises a well region, a first gate structure, a first gap wall, a first doped region and a second doped region; the first gate structure is formed on the surface of the well region and comprises at least one protruding part; the first spacer surrounds a sidewall of the first gate structure, the first spacer contacts the surface of the well region, and the first spacer includes a first portion and a second portion; the first doped region and the second doped region are formed below the surface of the well region, and a channel region is formed between the first doped region and the second doped region and comprises a first channel and a second channel; the sidewall of the first gate structure includes a plurality of surfaces, and a first surface of the at least one protrusion is parallel to a channel length direction in the channel region; the first channel is located below the first gate structure, the second channel is located between the first channel and the second doped region, and the first spacer of the first portion is located above the second channel; and

a select transistor, comprising: the well region, the second gate structure, the second spacer and the third doped region; the second gate structure is formed on the surface of the well region; the second gap wall surrounds the side wall of the second gate structure, and the second gap wall contacts the surface of the well region; the third doped region is formed below the surface of the well region; a fourth channel is arranged between the first doped region and the third doped region and is positioned below the second grid structure;

during programming, a plurality of carriers are injected into the charge trapping layer in the first spacer of the first portion through the second channel of the memory element.

12. The memory cell of claim 11, wherein the channel region further comprises a third channel, the third channel is located between the first channel and the first doped region, the spacer of the second portion is located above the third channel, and the length of the second channel is greater than the length of the third channel.

13. The memory cell of claim 11, wherein the first spacer of the first portion surrounds the at least one protrusion, the first spacer of the first portion has a first width, the first spacer of the second portion has a second width, the first width is greater than the second width, and the first width is less than or equal to three times the second width.

14. The memory cell of claim 11, wherein the first spacer comprises a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer, the first silicon oxide layer is in contact with the surface of the well region and the sidewall of the first gate structure, the first silicon oxide layer is located above the second channel, the silicon nitride layer covers the first silicon oxide layer, the second silicon oxide layer covers the silicon nitride layer, and the silicon nitride layer is the charge trapping layer.

15. The memory cell of claim 11, wherein the sidewall of the first gate structure has two surfaces adjacent to the second channel.

16. A memory cell of a non-volatile memory as claimed in claim 11, wherein the memory element further comprises: an auxiliary electrode and a dielectric layer, wherein the auxiliary electrode is located above the first spacer of the first portion, and the dielectric layer is located between the auxiliary electrode and the first spacer of the first portion.

17. The memory cell of claim 16, wherein the auxiliary electrode contacts a control gate layer on the first gate structure.

18. A memory cell of a non-volatile memory as claimed in claim 11, wherein the memory element further comprises: the auxiliary electrode is in contact with the first spacer of the first portion.

19. The memory cell of claim 18, wherein the auxiliary electrode contacts a control gate layer on the first gate structure.

20. The memory cell of claim 11, wherein the first gate structure comprises a first protrusion and a second protrusion, a surface of the first protrusion and a surface of the second protrusion face each other and define an opening of the first gate structure, and the first spacer of the first portion contacts the surface of the first protrusion and the surface of the second protrusion.