CN114188344A - Semiconductor memory device and method for manufacturing semiconductor memory device - Google Patents

Semiconductor memory device and method for manufacturing semiconductor memory device Download PDF

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Publication number
CN114188344A
CN114188344A CN202110606127.8A CN202110606127A CN114188344A CN 114188344 A CN114188344 A CN 114188344A CN 202110606127 A CN202110606127 A CN 202110606127A CN 114188344 A CN114188344 A CN 114188344A
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layer
semiconductor
wiring
memory device
wiring layer
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吉水康人
中木宽
中岛一明
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Kioxia Corp
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Kioxia Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/46—Structure, shape, material or disposition of the wire connectors prior to the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region

Abstract

The present disclosure provides a semiconductor memory device having a low contact resistance of a channel and a method of manufacturing the same. A semiconductor memory device according to an embodiment includes a plurality of 1 st wiring layers, 1 st pillars, 2 nd wiring layers, a semiconductor-containing layer, and 1 st insulating layers. A plurality of 1 st wiring layers are laminated in a1 st direction. The 1 st column extends in the 1 st direction inside the plurality of 1 st wiring layers, and includes a1 st semiconductor layer. The 2 nd wiring layer is disposed above an upper end of the 1 st semiconductor layer and extends in a2 nd direction intersecting the 1 st direction. The semiconductor containing layer has a1 st portion, a2 nd portion, and a 3 rd portion. The 1 st portion is disposed between an upper end of the 1 st semiconductor layer and a bottom surface of the 2 nd wiring layer. The 2 nd portion is adjacent to the 1 st portion and is disposed along a side surface of the 2 nd wiring layer. The 3 rd part is connected with the upper end of the 2 nd part and extends along the direction crossed with the 1 st direction. The 1 st insulating layer is disposed between the 1 st portion and the 2 nd wiring layer and between the 2 nd portion and the 2 nd wiring layer. At least the upper surface of part 3 comprises a metal.

Description

Semiconductor memory device and method for manufacturing semiconductor memory device
This application is entitled to the priority of application based on Japanese patent application No. 2020 and 153733 (application date: 9/14/2020). The present application incorporates the entire contents of the base application by reference thereto.
Technical Field
Embodiments of the present invention relate to a semiconductor memory device and a method of manufacturing the semiconductor memory device.
Background
A NAND type flash memory in which memory cells are three-dimensionally stacked is known.
Disclosure of Invention
The present invention addresses the problem of providing a semiconductor memory device having a low channel contact resistance.
A semiconductor memory device according to an embodiment includes a plurality of 1 st wiring layers, 1 st pillars (pilars), 2 nd wiring layers, semiconductor-containing layers, and 1 st insulating layers. A plurality of 1 st wiring layers are laminated in a1 st direction. The 1 st column extends in the 1 st direction inside the 1 st wiring layers and includes a1 st semiconductor layer. The 2 nd wiring layer is disposed above an upper end of the 1 st semiconductor layer and extends in a2 nd direction intersecting the 1 st direction. The semiconductor containing layer has a1 st portion, a2 nd portion, and a 3 rd portion. The 1 st portion is disposed between an upper end of the 1 st semiconductor layer and a bottom surface of the 2 nd wiring layer. The 2 nd portion is adjacent to the 1 st portion and is disposed along a side surface of the 2 nd wiring layer. The 3 rd part is connected with the upper end of the 2 nd part and extends along the direction crossed with the 1 st direction. The 1 st insulating layer is disposed between the 1 st portion and the 2 nd wiring layer and between the 2 nd portion and the 2 nd wiring layer. At least the upper surface of part 3 comprises a metal.
Drawings
Fig. 1 is a block diagram showing a circuit configuration of a semiconductor memory device according to embodiment 1.
Fig. 2 is a circuit diagram of a memory cell array of the semiconductor memory device according to embodiment 1.
Fig. 3 is a plan view of a memory cell array of the semiconductor memory device according to embodiment 1.
Fig. 4 is a cross-sectional view of a memory cell array of the semiconductor memory device according to embodiment 1.
Fig. 5 is a cross-sectional view of a characteristic portion of a memory cell array of the semiconductor memory device according to embodiment 1.
Fig. 6 is a perspective view of the vicinity of a selection transistor of a memory cell array of the semiconductor memory device according to embodiment 1.
Fig. 7 to 18 are diagrams for explaining an example of a method for manufacturing a semiconductor memory device according to embodiment 1.
Fig. 19 is a cross-sectional view of a characteristic portion of a memory cell array of the semiconductor memory device according to modification 1.
Fig. 20 is a cross-sectional view of a characteristic portion of a memory cell array of the semiconductor memory device according to modification 2.
Fig. 21 is a cross-sectional view of a characteristic portion of a memory cell array of the semiconductor memory device according to modification 3.
Description of the reference symbols
1 a semiconductor memory device; 24. 35 a wiring layer; 29 a semiconductor layer; 33a semiconductor-containing layer; 33cA, 33dA upper surface; 33cB, 33dB lower surface; 33a layer 1; 33b layer 2; 33c layer 3; 34 an insulating layer; 37 an electrical conductor; 50 metal layers; MP storage column
Detailed Description
Hereinafter, a semiconductor memory device according to an embodiment will be described with reference to the drawings. In the following description, components having the same or similar functions are denoted by the same reference numerals. Moreover, a repetitive description of those configurations may be omitted. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the sizes of the parts, and the like are not necessarily limited to those in reality. In the present specification, "connected" is not limited to a case of physical connection, and includes a case of electrical connection. In the present specification, "extend in the a direction" means, for example, that the dimension in the a direction is larger than the smallest dimension among the dimensions in the X direction, the Y direction, and the Z direction, which will be described later. The "a direction" is an arbitrary direction.
The X direction, the Y direction, and the Z direction are defined. The X direction and the Y direction are directions substantially parallel to the surface of the semiconductor substrate 20 (see fig. 4) described later. The Y direction is a direction in which a slit SLT described later extends. The X direction is a direction intersecting (e.g., substantially orthogonal to) the Y direction. The Z direction is a direction intersecting (e.g., substantially orthogonal to) the X direction and the Y direction and away from the semiconductor substrate 20. However, these expressions are expressions for convenience, and do not specify the direction of gravity. In the present embodiment, the Z direction is an example of the "1 st direction".
(embodiment 1)
Fig. 1 is a block diagram showing a system configuration of a semiconductor memory device 1. The semiconductor storage device 1 is a nonvolatile semiconductor storage device, and is, for example, a NAND flash memory. The semiconductor memory device 1 includes, for example, a memory cell array 10, a command register 11, an address register 12, a sequencer 13, a driver module 14, a row decoder module 15, and a sense amplifier module 16.
The memory cell array 10 includes a plurality of blocks BLK0 to BLKn (n is an integer of 1 or more). The block BLK is a set of nonvolatile memory cell transistors MC0 to MC7 (see fig. 2). The memory cell array 10 has a plurality of bit lines and a plurality of word lines. The memory cell transistors MC0 to MC7 are connected to one bit line and one word line, respectively. When the memory cell transistors MC0 to MC7 are not distinguished from each other, they are sometimes referred to as memory cell transistors MC. The detailed configuration of the memory cell array 10 will be described later.
The command register 11 holds a command CMD received by the semiconductor memory apparatus 1 from the memory controller 2. The command CMD includes, for example, a command for causing the sequencer 13 to execute a read operation, a write operation, an erase operation, and the like.
The address register 12 holds address information ADD received by the semiconductor memory apparatus 1 from the memory controller 2. The address information ADD includes, for example, a block address BA, a page address PA, and a column address CA. For example, a block address BA, a page address PA, and a column address CA are used for selection of the block BLK, the word line, and the bit line, respectively.
The sequencer 13 controls the operation of the entire semiconductor memory device 1. For example, the sequencer 13 controls the driver module 14, the row decoder module 15, the sense amplifier module 16, and the like based on the command CMD held in the command register 11, and executes a read operation, a write operation, an erase operation, and the like.
The driver module 14 generates a voltage used for a read operation, a write operation, an erase operation, and the like. The driver block 14 applies the generated voltage to the signal line corresponding to the selected word line, for example, based on the page address PA held in the address register 12.
The row decoder block 15 selects a block BLK in the corresponding memory cell array 10 based on the block address BA held in the address register 12. The row decoder block 15 transfers, for example, a voltage applied to a signal line corresponding to the selected word line in the selected block BLK.
In the write operation, the sense amplifier module 16 applies a voltage to each bit line in accordance with write data DAT received from the memory controller 2. In the read operation, the sense amplifier module 16 determines data stored in the memory cell based on the voltage of the bit line, and transmits the determination result to the memory controller 2 as read data DAT.
The communication between the semiconductor memory device 1 and the memory controller 2 supports, for example, the NAND interface standard. For example, in communication between the semiconductor memory apparatus 1 and the memory controller 2, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, a read enable signal REn, a ready/busy signal RBn, and an input/output signal I/O are used.
The input/output signal I/O is, for example, a signal having a length of 8 bits, and may include a command CMD, address information ADD, data DAT, and the like.
The command latch enable signal CLE is a signal indicating that the input/output signal I/O received by the semiconductor memory apparatus 1 is a command CMD.
The address latch enable signal ALE is a signal indicating that the signal I/O received by the semiconductor memory apparatus 1 is the address information ADD.
The write enable signal WEn is a signal that instructs input of the input/output signal I/O to the semiconductor memory apparatus 1.
The read enable signal REn is a signal commanding the output of the input/output signal I/O to the semiconductor memory apparatus 1.
The ready/busy signal RBn is a signal that notifies the memory controller 2 whether the semiconductor memory device 1 is in a ready state to accept a command from the memory controller 2 or in a busy state to not accept a command.
The semiconductor memory device 1 and the memory controller 2 described above may be combined to form one semiconductor device. Examples of such a semiconductor device include a memory card such as an SDTM card, and an SSD (solid state drive).
Next, an electrical structure of the memory cell array 10 will be described.
Fig. 2 is a diagram showing an equivalent circuit of the memory cell array 10, and one block BLK is extracted and shown. The block BLK includes a plurality of (e.g., 4) string units SU0 to SU 3.
The plurality of NAND strings NS are associated with bit lines BL0 to BLm (m is an integer of 1 or more), respectively. Each NAND string NS includes, for example, memory cell transistors MC0 to MC7, and select transistors ST1 and ST 2.
The memory cell transistor MC includes a control gate and a charge storage layer, and holds data in a nonvolatile manner. The selection transistors ST1 and ST2 are used for selecting the string unit SU in various operations.
The memory cell transistor MC may be a MONOS type using an insulating film for a charge storage layer or an FG type using a conductive layer for a charge storage layer. Hereinafter, the present embodiment will be described by taking MONOS type as an example.
In each NAND string NS, the drain of the select transistor ST1 is connected to the associated bit line BL, and the source of the select transistor ST1 is connected to one end of the memory cell transistors MC0 to MC7 connected in series. In the same block BLK, the gates of the select transistors ST1 in the string units SU0 to SU3 are commonly connected to the select gate lines SGD0 to SGD3, respectively. The select gate lines SGD 0-SGD 3 are connected to the row decoder module 15.
In each NAND string NS, the drain of the select transistor ST2 is connected to the other end of the memory cell transistors MC0 to MC7 connected in series. In the same block BLK, sources of the selection transistors ST2 are commonly connected to a source line SL, and gates of the selection transistors ST2 are commonly connected to a selection gate line SGS. The select gate line SGS is connected to the row decoder block 15.
The bit line BL commonly connects one NAND string NS included in each of the string units SU0 to SU3 in each block BLK. The source lines SL are connected in common to a plurality of blocks BLK, for example.
A set of a plurality of memory cell transistors MC connected to a common word line WL within one string unit SU is referred to as a cell unit CU, for example. For example, the storage capacity of a cell group CU including memory cell transistors MC each storing 1 bit (bit) data is defined as "1 page data". The cell group CU may have a storage capacity of 2 pages or more of data according to the number of bits of data stored in the memory cell transistor MC.
The circuit configuration of the memory cell array 10 included in the semiconductor memory device 1 according to embodiment 1 is not limited to the above-described configuration. For example, the number of memory cell transistors MC and the number of selection transistors ST1 and ST2 included in each NAND string NS may be designed to be arbitrary. The number of string units SU included in each block BLK may be designed to be any number.
Fig. 3 is a plan view of the memory cell array 10 included in the semiconductor memory device 1 according to embodiment 1. Fig. 3 shows an example of a top view of a block BLK. In this embodiment, a case where one block BLK includes 8 string units SU0 to SU7 will be described. In addition, a part of the insulating layer is omitted for simplification of explanation.
As shown in fig. 3, both side surfaces in the Y direction of the word line WL have slits SLT, respectively. The slit SLT extends in the X direction. In the present embodiment, the select gate line SGS and the word lines WL0 to WL7 are sequentially stacked above the semiconductor substrate 20 (see fig. 4). Also, the slot SLT separates the selection gate line SGS and the word line WL by, for example, a block BLK.
As shown in fig. 3, the string units SU0 to SU7 are arranged in the Y direction, for example. The string units SU each have a plurality of storage pillars MP. When the string units SU0 to SU7 are not distinguished, they are referred to as string units SU.
The memory pillar MP corresponds to the NAND string NS. The memory pillar MP has memory cell transistors MC0 to MC7 and a select transistor ST2 in the NAND string NS. The memory pillars MP penetrate (pass) the select gate line SGS and the word lines WL0 to WL7, and extend in the Z direction. The details of the structure of the storage column MP will be described later.
For example, each string unit SU has two banks arranged in the Y direction. In each string unit SU, a plurality of memory pillars MP are arranged in a zigzag manner in the X direction. One block BLK has 16 columns of banks extending in the X direction and arranged in the Y direction.
For example, the memory pillar MP1 of the string unit SU1 and the memory pillar MP2 of the string unit SU2 are adjacent in the Y direction. The bank MP3 of the string unit SU2 and the bank MP4 of the string unit SU3 are adjacent in the Y direction. The bank MP5 of the string unit SU1 and the bank MP6 of the string unit SU2 are adjacent in the Y direction. The storage pillar MP1 and the storage pillar MP5 are adjacent in the X direction, and the storage pillar MP2 and the storage pillar MP6 are adjacent in the X direction. In the X direction, the storage pillars MP3 and MP4 are disposed between the storage pillar MP1 (and MP2) and the storage pillar MP5 (and MP 6). In the Y direction, the storage pillar MP3 is disposed between the storage pillar MP1 (and MP5) and the storage pillar MP2 (and MP 6). In addition, in the Y direction, the storage pillars MP2 and MP6 are disposed between the storage pillar MP3 and the storage pillar MP 4. In addition, the arrangement of the memory pillars MP can be arbitrarily set.
Each memory column MP has a selection transistor ST 1. The gates of the plurality of selection transistors ST1 of each string unit SU are commonly connected to the selection gate line SGD. The select gate lines SGD0 to SGD7 are referred to as select gate lines SGD without distinction. In the example of fig. 3, the select gate lines SGD are respectively located between the memory pillars MP adjacent in the Y direction, extending in the X direction. For example, in the string unit SU2, there is a select gate line SGD2 extending in the X direction between the select transistor ST1 on the memory pillar MP3 and the select transistor ST1 on the memory pillar MP2 (and MP 6).
In the following description, for example, in an XY plane substantially parallel to the semiconductor substrate, a direction connecting the center of the memory pillar MP1 and the center of the memory pillar MP2 is referred to as an a direction, and a direction connecting the center of the memory pillar MP6 and the center of the memory pillar MP4 is referred to as a B direction. The a direction is substantially parallel to the semiconductor substrate and is different from the X direction and the Y direction. The B direction is a direction substantially parallel to the semiconductor substrate and intersecting the a direction.
In this embodiment, in two adjacent string units SU, the selection transistors ST1 of two memory pillars MP adjacent in the a direction or the B direction are commonly connected to one bit line BL via contact plugs CP1 and CP 2. In other words, two select transistors ST1 disposed between two select gate lines SGD and adjacent in the a direction or the B direction are commonly connected to one contact plug CP 1. Contact plug CP1 is an example of a "1 st conductor".
For example, the semiconductor containing layer 33 of the memory pillar MP1 of the string unit SU1 and the semiconductor containing layer 33 of the memory pillar MP3 of the string unit SU2 adjacent in the a direction are connected to one contact plug CP 1. Similarly, for example, the semiconductor containing layer 33 of the memory pillar MP6 of the string unit SU2 and the semiconductor containing layer 33 of the memory pillar MP4 of the string unit SU3 adjacent in the B direction are connected to one contact plug CP 1.
A contact plug CP2 is provided on the contact plug CP 1. The contact plug CP2 connects one of the plurality of bit lines BL extending in the Y direction with the contact plug CP 1.
Fig. 4 is a cross-sectional view of the memory cell array 10 included in the semiconductor memory device 1 according to embodiment 1. Fig. 4 is a sectional view taken along line a 1-a 2 of fig. 3.
As shown in fig. 4, an insulating layer 21 is provided on the semiconductor substrate 20. The insulating layer 21 is, for example, a silicon oxide film (SiO)2). Further, a circuit such as the row decoder module 15 or the sense amplifier module 16 may be provided in a region where the insulating layer 21 is formed, that is, between the semiconductor substrate 20 and the wiring layer 22.
The insulating layer 21 has a wiring layer 22 extending in the X direction and functioning as a source line SL. The wiring layer 22 is formed of a conductive material, for example, an n-type semiconductor, a p-type semiconductor, or a metal material is used.
The wiring layer 22 has an insulating layer 23 thereon. The insulating layer 23 is, for example, SiO2。
On the insulating layer 23, 9 wiring layers 24 and 9 insulating layers 25 functioning as the select gate lines SGS and the word lines WL0 to WL7 are alternately stacked from the lower layer. The insulating layer 25 is between the adjacent wiring layers 24. The wiring layer 24 is an example of "1 st wiring layer".
The wiring layer 24 is formed of a conductive material, for example, an n-type semiconductor, a p-type semiconductor, or a metal material is used. A case where a laminated structure of titanium nitride (TiN) and tungsten (W) is used as the wiring layer 24 will be described below. TiN has a function of preventing W and SiO in film formation of W by CVD (chemical vapor deposition)2A barrier layer for reaction of (3), or a close-contact layer for improving the close contact property of W. In addition, the insulating layer 25 may be made of, for example, SiO2。
The memory pillar MP is provided in the laminated body of the wiring layer 24 and the insulating layer 25. The storage column MP is an example of "column 1" and "column 2". The memory pillars MP penetrate the 9-layer wiring layer 24 and reach the wiring layer 22 at the bottom surface. The memory pillar MP includes a block insulating film 26, a charge storage layer 27, a tunnel insulating film 28, a semiconductor layer 29, a core layer 30, and a cap layer 31. The semiconductor layer 29 is an example of the "1 st semiconductor layer".
The storage column MP is located in the hole. The holes penetrate the plurality of wiring layers 24 and the plurality of insulating layers 25, and reach the wiring layer 22 at the bottom surface. The block insulating film 26, the charge storage layer 27, and the tunnel insulating film 28 are laminated in this order from the inner peripheral surface of the hole to the inside. The side surface of the semiconductor layer 29 is in contact with the tunnel insulating film 28, and the bottom surface is in contact with the wiring layer 22. The semiconductor layer 29 is a region where channels of the selection transistor ST2 and the memory cell transistor MC are formed. The semiconductor layer 29 functions as a signal line connecting current paths of the selection transistor ST2 and the memory cell transistors MC0 to MC 7. The core layer 30 is located inside the semiconductor layer 29. The semiconductor layer 29 and the core layer 30 have a cap layer 31 on their side surfaces in contact with the tunnel insulating film 28, and the memory column MP includes the semiconductor layer 29 passing through the inside of the plurality of wiring layers 24 and extending in the Z direction.
The bulk insulating film 26, the tunnel insulating film 28, and the core layer 30 are, for example, SiO2. The charge storage layer 27 is, for example, a silicon nitride film (SiN). The semiconductor layer 29 and the cap layer 31 are, for example, polysilicon.
The memory cell transistors MC0 to MC7 each include a memory cell MP and an 8-layer interconnect layer 24 functioning as word lines WL0 to WL7, respectively. Similarly, the selection transistor ST2 includes a memory pillar MP and a wiring layer 24 functioning as a selection gate line SGS.
Above the memory column MP, the selection transistor ST1 is configured by the semiconductor containing layer 33, the insulating layer 34, and the wiring layer 35. The channel regions of the selection transistor ST1 are the 1 ST layer 33a and the 2 nd layer 33b of the semiconductor containing layer 33 along the side and bottom surfaces of the wiring layer 35.
The semiconductor containing layer 33 has a1 st layer 33a, a2 nd layer 33b, and a 3 rd layer 33 c. Layer 1 33a is an example of "part 1" and "part 4". Layer 2 33b is an example of "part 2" and "part 5". Layer 3, 33c, is an example of "part 3". The semiconductor-containing layer 33 electrically connects a conductor 37 described later to the semiconductor layer 29.
The 1 st layer 33a extends in a certain direction in the XY plane. The 1 st layer 33a extends in the Y direction, for example. The 1 st layer 33a is between the upper end of the semiconductor layer 29 and the bottom surface of the wiring layer 35. As shown in fig. 4, a cap layer 31 may be provided between the semiconductor layer 29 and the 1 st layer 33 a. The 2 nd layer 33b connects the 1 st layer 33a with the 3 rd layer 33 c. The 2 nd layer 33b extends from the 1 st layer 33a substantially in the Z direction. The 2 nd layer 33b is formed along the side of the wiring layer 35. The 3 rd layer 33c is in contact with the upper end of the 2 nd layer 33b, and extends in one direction in the XY plane. The 3 rd layer 33c extends in the a direction or the B direction, for example. The 3 rd layer 33c is located above the upper surface of the wiring layer 35. The 3 rd layer 33c connects the two 2 nd layers 33B adjacent to the two storage pillars MP adjacent in the a direction or the B direction. The 3 rd layer 33c connects the adjacent two selection transistors ST 1. The 1 st layer 33a and the 2 nd layer 33b are, for example, polysilicon or amorphous silicon.
Fig. 5 is a cross-sectional view of a characteristic portion of the memory cell array 10 included in the semiconductor memory device 1 according to embodiment 1. Fig. 5 is an enlarged view of the vicinity of the semiconductor containing layer 33 in fig. 4. The upper surface 33cA of the 3 rd layer 33c further contains a metal on the basis of a semiconductor. The surface 33cA of the 3 rd layer 33c is, for example, Silicide (Silicide). Silicides are compounds of silicon and metals. The metal forming the silicide is, for example, nickel or cobalt. As shown in fig. 5, the 3 rd layer 33c has, for example, the 1 st region 33c1 and the 2 nd region 33c 2. The 2 nd region 33c2 is located above the 1 st region 33c1 in the Z direction. The 1 st region 33c1 is polysilicon or amorphous silicon and the 2 nd region 33c2 is a silicide.
The thickness of the 3 rd layer 33c is thicker than the thickness of the 2 nd layer 33b, for example. The thickness is the thickness in the direction orthogonal to the plane in which the layer expands. The perimeter of the upper surface 33cA of the 3 rd layer 33c is, for example, equal to or greater than the perimeter of the lower surface 33 cB. When the thickness of the 3 rd layer 33c is large, the 3 rd layer 33c can be prevented from penetrating when an opening is formed to form the conductor 37. Semiconductors expand in volume when combined with metals (e.g., silicides). The thickness of the 3 rd layer 33c becomes thicker than the thickness of the 2 nd layer 33b by the combination with the metal. The thickness of the 3 rd layer 33c may be formed thicker than the thickness of the 2 nd layer 33b by selectively growing a semiconductor on the 3 rd layer 33 c.
The insulating layer 34 is between the semiconductor containing layer 33 and the wiring layer 35. The insulating layer 34 is an example of the "1 st insulating layer". Insulating layer 34 is along semiconductor containing layer 33. The insulating layer 34 functions as a gate insulating film of the selection transistor ST 1. The insulating layer 34 includes, for example, a1 st portion on the 1 st layer 33a, and a2 nd portion on the 2 nd layer 33 b. That is, the insulating layer 34 has, for example, a structure extending in the Y directionAnd a2 nd portion extending substantially in the Z direction. The insulating layer 34 is, for example, SiO2. The insulating layer 34 may have a stacked structure, or may have a MONOS structure (more specifically, a stacked structure of an insulating layer, a charge storage layer, and an insulating layer) that can perform threshold control, for example.
The wiring layer 35 is above the memory pillars MP. The wiring layer 35 functions as a select gate line SGD. The wiring layer 35 extends in the X direction, for example. For example, the center position of the wiring layer 35 in the Y direction is different from the center position of the memory pillar MP. The wiring layer 35 is disposed above the upper end of the semiconductor layer 29 in the Y direction. The wiring layer 35 is formed of a conductive material, and for example, an n-type semiconductor, a p-type semiconductor, or a metal material can be used. The wiring layer 35 has a single-layer structure of W or a laminated structure of TiN/W, for example. The wiring layer 35 may also be silicide.
Above the memory pillars MP, there are insulating layers 32 extending in the X direction and the Y direction between the layers of the insulating layer 25. The insulating layer 32 functions as an etching stopper layer when processing a trench TR (i.e., a groove pattern) described later. The insulating layer 32 is an insulating material having an etching selectivity with respect to the insulating layer 25, and is, for example, SiN. In addition, the insulating layer 32 may also be omitted. The trench TR penetrates the insulating layer 25 and the insulating layer 32, reaches the memory pillar MP at the bottom surface, and extends in the X direction. A wiring layer 35 is formed in the trench TR.
A semiconductor containing layer 33 and an insulating layer 34 are stacked on the side and bottom surfaces of the trench TR above the memory pillar MP. The insulating layer 36 is provided on the side surfaces and the bottom surfaces of the trenches TR except for the region where the semiconductor containing layer 33 and the insulating layer 34 are provided, and the region between the upper surfaces of two trenches TR adjacent in the Y direction. The insulating layer 36 is, for example, SiO2. The height position of the upper surface of the wiring layer 35 in the Z direction is lower than the upper surface of the trench TR (close to the semiconductor substrate 20). That is, the height position of the upper surface of the wiring layer 35 in the Z direction is lower than the upper surfaces of the semiconductor containing layer 33 and the insulating layer 34. Further, the insulating layer 36 provided in the region between the upper surfaces of two adjacent trenches TR in the Y direction may also be omitted.
The 3 rd layer 33c has a conductor 37 functioning as a contact plug CP 1. Conductor 37 is an example of a "1 st conductor". The conductor 37 has a conductor 38 functioning as a contact plug CP 2. The conductor 38 has a wiring layer 39 that functions as a bit line BL and extends in the Y direction. The conductor 37, the conductor 38, and the wiring layer 39 are formed of a conductive material, and for example, a metal material can be used.
Next, an example of the arrangement of the selection transistor ST1 and the selection gate line SGD will be described with reference to fig. 6. Fig. 6 is a perspective view showing the arrangement of the upper portion of the memory column MP, the select transistor ST1, the select gate line SGD, the contact plugs CP1 and CP2, and the bit line BL. In the example of fig. 6, a part of the insulating layer is omitted for the sake of simplifying the description. In addition, the selection transistor ST1 is simplified.
As shown in fig. 6, for example, two storage pillars MP1 and MP3 are arranged in positions inclined with respect to the X direction and the Y direction. The wiring layer 35 (select gate line SGD1) extends in the X direction so as to pass over a partial region of the memory pillar MP 1. Similarly, the wiring layer 35 (the select gate line SGD2) extends in the X direction so as to pass over a partial region of the memory pillar MP 3. The wiring layer 35 is not provided between the memory pillar MP1 and the memory pillar MP 3. A semiconductor containing layer 33 and an insulating layer 34 are provided on the memory pillars MP1 and MP3 and between the memory pillar MP1 and the memory pillar MP 3. The semiconductor-containing layer 33 is connected to a wiring layer 39 via conductors 37 and 38. In the example of fig. 6, the insulating layer 25 between the memory pillar MP1 and the memory pillar MP3 is omitted to show the connection between the semiconductor containing layer 33 and the conductor 37.
Next, a method for manufacturing the semiconductor memory device 1 according to embodiment 1 will be described. Fig. 7 to 18 respectively show a plane of the memory cell array 10 and a cross section (B1-B2 cross section) along the line B1-B2 in the manufacturing process.
Hereinafter, a description will be given of a case where, as a method for forming the wiring layer 24, a method (hereinafter, referred to as "replacement") in which a structure corresponding to the wiring layer 24 is formed using a sacrificial layer and then the sacrificial layer is removed and replaced with a conductive material (the wiring layer 24) is used.
As shown in fig. 7, an insulating layer 21, a wiring layer 22, and an insulating layer 23 are formed in this order on a semiconductor substrate 20. Next, 9 sacrificial layers 40 and 9 insulating layers 25 corresponding to the wiring layers 24 are alternately stacked. The sacrificial layer 40 may use a material that can obtain a selectivity ratio of wet etching with respect to the insulating layer 25. For example, the sacrificial layer 40 is SiN.
Next, the memory pillars MP are formed. First, a hole is formed through the 9-layer insulating layer 25, the 9-layer sacrificial layer 40, and the insulating layer 23 so that the bottom surface reaches the wiring layer 22. Next, the block insulating film 26, the charge storage layer 27, and the tunnel insulating film 28 are stacked in this order. Then, the block insulating film 26, the charge storage layer 27, and the tunnel insulating film 28 on the bottom surface of the hole are removed, and the wiring layer 22 is exposed on the bottom surface of the hole. Next, the semiconductor layer 29 and the core layer 30 are formed to fill the hole. Next, the semiconductor layer 29 and the core layer 30 on the uppermost insulating layer 25 are removed. At this time, the semiconductor layer 29 and the core layer 30 above the hole are also removed. Next, the cap layer 31 is formed to fill the upper portion of the hole.
As shown in fig. 8, after the insulating layer 25 is formed, the insulating layer 32 is formed so as to cover the upper surface of the memory pillar MP. At this time, the insulating layer 32 in the region where the slit SLT is formed is removed later. Next, the insulating layer 25 is formed over the insulating layer 32.
As shown in fig. 9, a trench TR having a bottom surface reaching the memory pillar MP is formed. At this time, the trench TR may be processed in two stages by using the insulating layer 32 as an etching stopper, for example, so that processing damage to the upper surface of the memory pillar MP may be reduced. In the bottom of the trench TR, a part of the upper surface of each memory pillar MP arranged in zigzag in 2 columns is exposed.
Next, the semiconductor containing layer 33, the insulating layer 34A, and the insulating layer 41 are stacked in this order. The insulating layer 41 functions as a protective layer for the insulating layer 34A, for example. For the insulating layer 41, a material having a selectivity of wet etching with respect to the insulating layer 34A can be used, for example. The insulating layer 41 is, for example, SiN.
Next, as shown in fig. 10, between the two trenches TR, a mask pattern covering the upper portions of the adjacent two memory pillars MP is formed.
As shown in fig. 11, the insulating layer 34A and the insulating layer 41 are removed in a region not covered with the resist 42, for example, by CDE (chemical dry etching).
As shown in fig. 12, after the resist 42 is removed, a part of the semiconductor containing layer 33 is oxidized to form an insulating layer 36. At this time, the semiconductor containing layer 33 in the region whose surface is covered with the insulating layer 34A and the insulating layer 41 is not oxidized. In addition, the end region of the semiconductor containing layer 33 whose surface is covered with the insulating layer 34A and the insulating layer 41 may be oxidized. Then, the insulating layer 41 is removed by, for example, wet etching.
As shown in fig. 13, an insulating layer 34B and an insulating layer 34C are sequentially stacked over the insulating layer 34A and the insulating layer 36. The insulating layer 34B is, for example, silicon nitride, and the insulating layer 34C is, for example, silicon oxide. Then, after a conductive layer is stacked in the trench TR, an unnecessary portion is etched back (etch back), thereby forming the wiring layer 35.
As shown in fig. 14, the insulating layers 34A, 34B, and 34C stacked on the upper surface of the semiconductor-containing layer 33 are removed to expose the upper surface of the semiconductor-containing layer 33. A portion of the insulating layers 34A, 34B, 34C is removed, for example, by Chemical Mechanical Polishing (CMP). The semiconductor may be selectively grown on the exposed semiconductor layer-containing layer 33 to increase the thickness of the semiconductor layer-containing layer 33.
As shown in fig. 15, a metal layer 43 is laminated on the upper surface of the laminated body. The metal layer 43 is, for example, nickel. By heating the stacked body after stacking the metal layer 43, the semiconductor and the metal are combined in the upper surface of the semiconductor containing layer 33. For example, the exposed surface of the semiconductor containing layer 33 is silicided. This process is referred to as a salicidation process. When the wiring layer 35 is formed of a semiconductor, the wiring layer 35 is also silicided. Then, the metal layer 43 that is not silicided is removed.
As shown in fig. 16, the insulating layer 25 is formed on the upper surface 33cA of the semiconductor-containing layer 33. The insulating layers 34A, 34B, and 34C become the insulating layer 34.
As shown in fig. 17, after the slit SLT is processed, the sacrificial layer 40 is removed from the side surface of the slit SLT by wet etching, and a gap AG is formed.
As shown in fig. 18, TiN and W are formed to fill the voids, and then the TiN and W formed in the slit SLT and on the uppermost insulating layer 25 are removed to form the wiring layer 24.
As shown in fig. 18, next, the slit SLT is filled with the insulating layer 44. Next, the conductor 37 is formed with its bottom surface in contact with the semiconductor containing layer 33. Next, after the insulating layer 25 is formed, the conductive body 38 and the wiring layer 39 are formed.
Through the above steps, the semiconductor memory device 1 according to the present embodiment is manufactured. The manufacturing steps shown here are examples, and other steps may be inserted between the steps. Although the example in which the wiring layer 35 and the semiconductor containing layer 33 are simultaneously silicided has been described above, the wiring layer 35 may be a laminated film of W, W and TiN, for example. In this case, after the state of fig. 13 is obtained, an insulating layer is stacked on the wiring layer 35 to fill the trench TR. Then, as in fig. 14, the insulating layers 34A, 34B, and 34C stacked on the upper surface of the semiconductor-containing layer 33 are removed to expose the upper surface of the semiconductor-containing layer 33, and the semiconductor and the metal are combined with each other on the upper surface of the semiconductor-containing layer 33.
In the semiconductor memory device 1 according to the present embodiment, the upper surface 33cA of the 3 rd layer 33c of the semiconductor-containing layer 33 contains a metal, for example, a silicide. The metal-containing region (for example, silicide) of the upper surface 33cA of the 3 rd layer 33c suppresses the opening from penetrating the 3 rd layer 33c when the opening for forming the conductor 37 is formed. In addition, by previously combining the metal with the upper surface 33cA of the 3 rd layer 33c (silicidizing the same in a self-aligned manner), the contact resistance between the 3 rd layer 33c and the conductor 37 is reduced.
(modification 1)
A description will be given of a1 st modification of the semiconductor memory device 1 according to embodiment 1. Fig. 19 is a cross-sectional view of a characteristic portion of the memory cell array 10 included in the semiconductor memory device 1 according to modification 1. Fig. 19 is an enlarged view of the vicinity of the semiconductor containing layer 33. In the semiconductor memory according to modification 1, configurations other than the configuration described below are the same as those of the semiconductor memory device 1 according to embodiment 1.
The semiconductor containing layer 33 has a1 st layer 33a, a2 nd layer 33b, and a 3 rd layer 33 d. The 3 rd layer 33d is different from the 3 rd layer 33c of the semiconductor-containing layer 33 according to embodiment 1 in structure. The entire region of the 3 rd layer 33d in the thickness direction contains metal. All of the 3 rd layer 33d is, for example, a fully silicided compound in the thickness direction with a metal, for example. The thickness of the 3 rd layer 33d is, for example, greater than the thickness 33b of the 2 nd layer, and the circumference of the upper surface 33dA of the 3 rd layer 33d is, for example, equal to or greater than the circumference of the lower surface 33 dB.
The same effects as those of embodiment 1 can be obtained with the configuration according to modification 1.
(modification 2)
A2 nd modification of the semiconductor memory device 1 according to embodiment 1 will be described. Fig. 20 is a cross-sectional view of a characteristic portion of the memory cell array 10 included in the semiconductor memory device 1 according to modification 2. Fig. 20 is an enlarged view of the vicinity of the semiconductor containing layer 33. In the semiconductor memory device according to modification 2, the configuration other than the configuration described below is the same as that of the semiconductor memory device 1 according to embodiment 1.
The semiconductor memory device according to modification 2 further includes a metal layer 50 on an upper surface 33cA of the 3 rd layer 33c of the semiconductor containing layer 33. The metal layer 50 contains, for example, titanium, tantalum, tungsten. As shown in fig. 14, the metal layer 50 is formed by selective growth on the exposed conductive surface after exposing the upper surface 33cA of the 3 rd layer 33 c. Selective growth of the metal layer 50 may use, for example, a regioselective Atomic Layer Deposition (ALD) method, an electroless plating method, or the like.
The same effects as those of embodiment 1 can be obtained with the configuration according to modification 2. Further, by providing the metal layer 50, the 3 rd layer 33c can be further prevented from penetrating through the opening for forming the conductor 37. In addition, titanium, tantalum, and tungsten used for the metal layer 50 are less likely to cause contamination in the subsequent process than nickel and cobalt used for silicidation. For example, nickel and cobalt are difficult to remove when mixed in an etching apparatus for an insulating layer used in a subsequent process, but titanium, tantalum, and tungsten are easy to remove compared with nickel and cobalt.
(modification 3)
A modification 3 of the semiconductor memory device 1 according to embodiment 1 will be described. Fig. 21 is a cross-sectional view of a characteristic portion of the memory cell array 10 included in the semiconductor memory device 1 according to the modification example 3. Fig. 21 is an enlarged view of the vicinity of the semiconductor containing layer 33. The semiconductor memory according to modification 1 has the same configuration as that of the semiconductor memory device 1 according to embodiment 1 except for the configuration described below.
The semiconductor device according to modification 3 further includes a metal layer 50 on an upper surface 33dA of the 3 rd layer 33d according to modification 1. The metal layer 50 is the same as in modification 2.
With the configuration according to modification 3, the same effects as those of embodiment 1 can be obtained.
Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the spirit of the invention. These embodiments and/or modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalent scope thereof.

Claims (9)

1. A semiconductor memory device includes:
a plurality of 1 st wiring layers which are laminated in a1 st direction;
a1 st column extending in the 1 st direction inside the plurality of 1 st wiring layers and including a1 st semiconductor layer;
a2 nd wiring layer which is arranged above an upper end of the 1 st semiconductor layer and extends in a2 nd direction intersecting the 1 st direction;
a semiconductor-containing layer having a1 st portion, a2 nd portion, and a 3 rd portion, the 1 st portion being disposed between an upper end of the 1 st semiconductor layer and a bottom surface of the 2 nd wiring layer, the 2 nd portion being in contact with the 1 st portion and being provided along a side surface of the 2 nd wiring layer, the 3 rd portion being in contact with an upper end of the 2 nd portion and extending in a direction intersecting the 1 st direction; and
a1 st insulating layer disposed between the 1 st portion and the 2 nd wiring layer and between the 2 nd portion and the 2 nd wiring layer,
at least the upper surface of the 3 rd portion comprises a metal.
2. The semiconductor memory device according to claim 1,
the portion 3 comprises a silicide.
3. The semiconductor storage device according to claim 1 or 2,
the semiconductor device further includes a metal layer laminated on an upper surface of the 3 rd portion.
4. The semiconductor storage device according to claim 1 or 2,
the thickness of the 3 rd portion is thicker than the thickness of the 2 nd portion.
5. The semiconductor storage device according to claim 1 or 2,
the perimeter of the upper surface of the 3 rd part is greater than or equal to the perimeter of the lower surface of the 3 rd part.
6. The semiconductor storage device according to claim 1 or 2,
further comprising a1 st conductor, the 1 st conductor being electrically connected to the 3 rd portion and extending in the 1 st direction above the 3 rd portion,
the perimeter of the upper surface of the 3 rd portion is longer than the perimeter of the 1 st conductor.
7. The semiconductor memory device according to claim 1 or 2, further comprising:
a2 nd column extending in the 1 st direction inside the plurality of 1 st wiring layers and including a2 nd semiconductor layer; and
a 3 rd wiring layer which is arranged above an upper end of the 2 nd semiconductor layer and extends in the 2 nd direction,
the semiconductor-containing layer further has a 4 th portion and a 5 th portion, the 4 th portion being disposed between an upper end of the 2 nd semiconductor layer and a bottom surface of the 3 rd wiring layer, the 5 th portion extending from the 4 th portion toward the 3 rd portion along a side surface of the 2 nd wiring layer.
8. A method of manufacturing a semiconductor memory device, comprising:
alternately laminating the conductive layer or the sacrificial layer and the insulating layer in the 1 st direction;
forming a hole extending in a1 st direction in a stacked body formed by stacking, and forming a1 st pillar including a1 st semiconductor layer in the hole;
a step of stacking a1 st insulating layer on the 1 st pillar and forming a trench in the 1 st insulating layer;
forming a2 nd semiconductor layer in the groove, and then oxidizing a part of the 2 nd semiconductor layer to form a semiconductor-containing layer over the 1 st semiconductor layer;
forming a2 nd wiring layer in the groove; and
and exposing a part of the semiconductor-containing layer, and combining the exposed part of the semiconductor with the metal.
9. The method for manufacturing a semiconductor memory device according to claim 8,
the 2 nd wiring layer and the semiconductor containing layer are simultaneously combined with a metal.
CN202110606127.8A 2020-09-14 2021-05-26 Semiconductor memory device and method for manufacturing semiconductor memory device Pending CN114188344A (en)

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