CN114188276A - Method for forming semiconductor structure - Google Patents

Method for forming semiconductor structure Download PDF

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Publication number
CN114188276A
CN114188276A CN202010963310.9A CN202010963310A CN114188276A CN 114188276 A CN114188276 A CN 114188276A CN 202010963310 A CN202010963310 A CN 202010963310A CN 114188276 A CN114188276 A CN 114188276A
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forming
dielectric layer
initial
isolation structure
layer
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纪世良
肖杏宇
张海洋
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN202010963310.9A priority Critical patent/CN114188276A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A method of forming a semiconductor structure, comprising: providing a substrate; forming a plurality of discrete nanostructures on a substrate, with a groove between adjacent nanostructures; forming a first dielectric layer and an initial isolation structure on a substrate, wherein the top surface of the first dielectric layer is lower than the top surface of the nano structure, the first dielectric layer is positioned on the partial side wall surface of the initial isolation structure, and the initial isolation structure is positioned in at least one groove; and etching the initial isolation structure exposed out of the first dielectric layer to form an isolation structure. The performance of the semiconductor structure formed by the method is improved.

Description

Method for forming semiconductor structure
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure.
Background
The semiconductor Integrated Circuit (IC) industry has experienced exponential growth. In the course of IC evolution, the functional density (i.e., the number of interconnected devices per chip area) has generally increased, while the geometry (i.e., the smallest component or line that can be produced using a fabrication process) has decreased. Such a scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. This scaling down also increases the complexity of handling and manufacturing the IC.
In some IC designs, as technology nodes shrink, one advantage achieved is: with shrinking feature sizes, typical polysilicon gates are replaced with metal gates to improve device performance. One process of forming a metal gate is referred to as a replacement gate or "gate last" process, in which the metal gate is fabricated "last", which allows for a reduction in the number of subsequent processes, including high temperature processing, that must be performed after the gate is formed.
However, implementing these IC fabrication processes also has a number of challenges, particularly for scaled-down IC components in advanced process nodes, such as N10, N5, and the like. One challenge, among others, is how to effectively isolate the metal gate after replacement.
Disclosure of Invention
The invention provides a method for forming a semiconductor structure to improve the performance of the semiconductor structure.
To solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming a plurality of discrete nanostructures on a substrate, with a groove between adjacent nanostructures; forming a first dielectric layer and an initial isolation structure on a substrate, wherein the top surface of the first dielectric layer is lower than the top surface of the nano structure, the first dielectric layer is positioned on the partial side wall surface of the initial isolation structure, and the initial isolation structure is positioned in at least one groove; and etching the initial isolation structure exposed out of the first dielectric layer to form an isolation structure.
Optionally, the method for forming the initial isolation structure and the first dielectric layer includes: forming an initial first dielectric layer on the substrate, wherein the initial first dielectric layer is positioned in the groove; forming a patterned mask structure on the initial first dielectric layer, wherein the mask structure exposes a part of the surface of the initial first dielectric layer in the groove; etching the initial first dielectric layer by taking the mask structure as a mask until the surface of the substrate is exposed, and forming an isolation opening in the initial first dielectric layer; forming the initial isolation structure within an isolation opening; and after the initial isolation structure is formed, etching the initial first dielectric layer back to form a first dielectric layer, wherein part of the initial isolation structure is exposed out of the first dielectric layer, and the top surface of the first dielectric layer is lower than that of the nano structure.
Optionally, the initial isolation structures have a first dimension in the alignment direction of the nanostructures, and the isolation structures have a second dimension in the alignment direction of the nanostructures, the second dimension being smaller than the first dimension.
Optionally, the first size ranges from greater than 10 nanometers; the second dimension is in a range of 1 nanometer to 5 nanometers.
Optionally, the process for etching the initial isolation structure includes an isotropic dry etching process or an isotropic wet etching process.
Optionally, the etching gas of the isotropic dry etching process includes: carbon tetrafluoride and argon, or carbon tetrafluoride and helium.
Optionally, the nanostructure comprises: a first region, a second region located on the first region, and a third region located on the second region; the first area comprises bottom layer nanowires, the first dielectric layer is positioned on the side wall of the first area and is lower than the bottom plane of the second area; the second area comprises a plurality of composite layers, and each composite layer comprises a sacrificial layer and nanowires positioned on the sacrificial layer; the third region includes a top sacrificial layer.
Optionally, the thickness of the top sacrificial layer is greater than that of the sacrificial layer; the thickness of the top sacrificial layer is 3-10 nanometers larger than that of the sacrificial layer.
Optionally, after the forming the isolation structure, the method further includes: forming a gate structure on the substrate, the gate structure spanning the nanostructures, and the isolation structure isolating adjacent gate structures.
Optionally, the material of the gate structure includes a metal.
Optionally, the forming method of the gate structure includes: after the isolation structure is formed, forming a dummy gate structure on the first dielectric layer, wherein the dummy gate structure spans the nano structure and the isolation structure; forming a second dielectric layer on the side wall of the pseudo gate structure; removing the pseudo gate structure, and forming a first opening in the second dielectric layer; removing the sacrificial layer and the top sacrificial layer exposed by the first opening, and forming second openings between adjacent nanowires and between the bottom nanowire and the nanowire; a gate structure is formed within the first opening and within the second opening.
Optionally, the forming method of the gate structure includes: forming a dummy gate structure on the first dielectric layer before forming the isolation structure, wherein the dummy gate structure spans the nano-structure and the initial isolation structure; forming a second dielectric layer on the side wall of the pseudo gate structure; and removing the pseudo gate structure, and forming a first opening in the second dielectric layer, wherein the first opening exposes the initial isolation structure.
Optionally, the forming method of the gate structure includes: after the isolation structure is formed, removing the sacrificial layer and the top sacrificial layer exposed by the first opening, and forming second openings between adjacent nanowires and between the bottom nanowire and the nanowire; a gate structure is formed within the first opening and within the second opening.
Optionally, the etching rate of the material of the initial first dielectric layer is different from that of the material of the initial isolation structure.
Optionally, the material of the initial first dielectric layer includes a dielectric material, and the dielectric material includes silicon oxide.
Optionally, the material of the initial isolation structure comprises a dielectric material, and the dielectric material comprises silicon nitride.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
according to the semiconductor structure forming method, the initial isolation structure with a large size is formed, and then the initial isolation structure is etched to form the isolation structure. The isolation structure formed by the method has smaller size, can break through the limit of photoetching limit, and on one hand, the isolation structure with smaller size can be obtained to meet the requirement of a semiconductor structure; on the other hand, the size precision of the formed isolation structure is high, and meanwhile, the position of the isolation structure can be adjusted, so that the isolation structure can be positioned between adjacent nano structures, and the size uniformity and the performance of a subsequently formed grid structure are good and uniform.
Further, the thickness of the top sacrificial layer is larger than that of the sacrificial layer, so that after the gate structure is formed subsequently, the height of the isolation structure can be higher than that of the nano structure, and the isolation effect of the isolation structure on the adjacent gate structure is better. Therefore, the situation that the adjacent gate structures are short-circuited when the height of the isolation structures is lower than that of the nano structures is avoided when the loss of the isolation structures in the process of forming the gate structures is more.
Drawings
FIG. 1 is a schematic cross-sectional view of a semiconductor structure in one embodiment;
FIGS. 2-7 are schematic cross-sectional views of semiconductor structures according to embodiments of the present invention;
fig. 8 and 9 are schematic cross-sectional views of a semiconductor structure in another embodiment of the invention.
Detailed Description
As described in the background, the current state of the art metal gate fabrication process presents numerous challenges. The analysis will now be described with reference to specific examples.
FIG. 1 is a cross-sectional view of a semiconductor structure according to an embodiment.
Please refer to fig. 1, which includes: a substrate 100; a first nanostructure on a substrate 100, the first nanostructure comprising a number of first nanowires 101 arranged in a stack; a second nanostructure on the substrate 100, the second nanostructure comprising a plurality of second nanowires 102 arranged in a stack, the first nanostructure and the second nanostructure being adjacent; a dielectric layer 103 on the substrate 100, the dielectric layer 103 being on the first nanostructure sidewall and the second nanostructure sidewall; first gate structures 104 on the substrate, the first gate structures 104 surrounding the first nanostructures, and the first gate structures 104 being located between the first nanowires 101; second gate structures 105 on the substrate, the second gate structures 105 surrounding the second nanostructures, and the second gate structures 105 being located between the second nanowires 102; an isolation structure 106 located between the first nanostructure and the second nanostructure.
In the semiconductor structure, the isolation structure 106 is used to electrically isolate the first gate structure 104 from the second gate structure 105, and the isolation structure 106 may be formed before a gate last process or after the gate last process. Due to the smaller size of the semiconductor structure, it is desirable to form isolation structures 106 that are smaller in size. However, due to the limitation of lithography limits, the conventional lithography technology cannot form the pattern of the isolation structure 106 with a required small size, and thus the size of the formed isolation structure 106 is large, which cannot meet the device requirements.
Furthermore, the position of the isolation structure 106 formed by the conventional photolithography technique is easily shifted, so that the uniformity of the sizes of the first gate structure 104 and the second gate structure 105 is poor, and the problem of uneven pressure is also caused, so that the first gate structure 104 and the second gate structure 105 have different electrical properties, which affects the performance of the semiconductor structure.
In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, in which an initial isolation structure with a large size is formed first, and then the initial isolation structure is etched to form an isolation structure. The isolation structure formed by the method has smaller size, can break through the limit of photoetching limit, and can obtain the isolation structure with smaller size so as to meet the requirement of a semiconductor structure.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 2 to 7 are schematic cross-sectional views of semiconductor structures according to embodiments of the present invention.
Referring to fig. 2, a substrate 200 is provided.
In this embodiment, the material of the substrate 200 is silicon.
In other embodiments, the substrate material comprises silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multielement semiconductor material formed by III-V group elements comprises InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.
With continued reference to fig. 2, a plurality of discrete nanostructures are formed on a substrate 200, with grooves 205 between adjacent nanostructures.
The nanostructure includes: a first region, a second region located on the first region, and a third region located on the second region; the first region comprises bottom layer nanowires 201, the second region comprises a plurality of composite layers, and the composite layers comprise a sacrificial layer 202 and nanowires 203 positioned on the sacrificial layer 202; the third region includes a top sacrificial layer 204.
The method for forming the nano-structure and the groove 205 comprises the following steps: forming a nanostructure material layer on the substrate 200, wherein the nanostructure material layer comprises a bottom fin material layer (not shown), a plurality of composite structures on the bottom fin material layer, the composite structures comprise a sacrificial material layer (not shown), a fin material layer (not shown) on the sacrificial material layer, and a top sacrificial material layer (not shown) on the composite structures; forming a patterned mask layer (not shown) on the nanostructure material layer; and etching the nanostructure material layer by using the patterned mask layer as a mask to form the nanostructure and the groove 205 on the substrate 200.
The bottom fin material layer provides a material layer for forming the bottom nanowire 201; the fin material layer provides a material layer for forming the nanowires 203; the sacrificial material layer provides a material layer for forming the sacrificial layer 202; the top sacrificial material layer provides a material layer for forming the top sacrificial layer 204. The bottom fin material layer and the fin material layer are made of silicon or silicon germanium; the material of the sacrificial material layer and the top sacrificial material layer comprises silicon or silicon germanium.
In this embodiment, the material of the bottom fin material layer and the fin material layer includes silicon; the material of the sacrificial material layer and the top sacrificial material layer comprises silicon germanium. The silicon germanium and the silicon have a larger etching selection ratio, so that the bottom layer nanowires 201 and the nanowires 203 are less damaged by the removal process when the sacrificial layer 202 and the top layer sacrificial layer 204 are removed later.
In this embodiment, the thickness of the top sacrificial layer 204 is greater than that of the sacrificial layer 202, so that after a gate structure is formed subsequently, the height of the formed isolation structure can be higher than that of the nano structure, so as to ensure that the isolation effect of the isolation structure on an adjacent gate structure is good. Therefore, the situation that the adjacent gate structures are short-circuited when the height of the isolation structures is lower than that of the nano structures is avoided when the loss of the isolation structures in the process of forming the gate structures is more.
In this embodiment, the thickness of the top sacrificial layer 204 is greater than the thickness of the sacrificial layer 202 by 3 nm to 10 nm.
In other embodiments, the thickness of the top sacrificial layer is the same as the thickness of the sacrificial layer.
Next, a first dielectric layer and an initial isolation structure are formed on the substrate 200, wherein the top surface of the first dielectric layer is lower than the top surface of the nano-structure, the first dielectric layer is located on the partial sidewall surface of the initial isolation structure, and the initial isolation structure is located in at least one of the grooves. Please refer to fig. 3 and fig. 4 for the formation process of the first dielectric layer and the initial isolation structure.
Referring to fig. 3, an initial first dielectric layer 206 is formed on the substrate 200, wherein the initial first dielectric layer 206 is located in the recess 205; an initial isolation structure 207 is formed within the initial first dielectric layer 206.
The method for forming the initial first dielectric layer 206 includes: forming a layer of dielectric material (not shown) over the substrate 200 and within the recess 205; the dielectric material layer is planarized until the nanostructure top surface is exposed, forming the initial first dielectric layer 206.
The material of the initial first dielectric layer 206 comprises a dielectric material comprising a combination of one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon oxycarbonitride. In this embodiment, the material of the initial first dielectric layer 206 includes silicon oxide.
The method for forming the initial isolation structure 207 comprises the following steps: forming a patterned mask structure (not shown) on the initial first dielectric layer 206, wherein the mask structure exposes a portion of the surface of the initial first dielectric layer 206 in the recess 205; etching the initial first dielectric layer 206 by using the mask structure as a mask until the surface of the substrate 200 is exposed, and forming an isolation opening (not shown) in the initial first dielectric layer 206; forming a layer of spacer material (not shown) within the spacer openings and on the initial first dielectric layer 206; planarizing the isolation material layer until the surface of the initial first dielectric layer 206 is exposed, and forming the initial isolation structure 207.
The material of the initial isolation structure 207 comprises a dielectric material comprising one or a combination of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon oxycarbonitride. In the present embodiment, the material of the initial isolation structure 207 includes silicon nitride.
The initial isolation structure 207 is used for subsequently forming an isolation structure for isolating subsequently formed adjacent gate structures.
The initial isolation structures 207 have a first dimension in the alignment direction of the nanostructures.
In this embodiment, the first dimension is in a range of greater than 10 nanometers.
Referring to fig. 4, after the initial isolation structure 207 is formed, the initial first dielectric layer 206 is etched back to form a first dielectric layer 208, a portion of the initial isolation structure 207 is exposed by the first dielectric layer 208, and the top surface of the first dielectric layer 208 is lower than the top surface of the nano structure.
In this embodiment, the first dielectric layer 208 is located on the sidewall of the first region, and the first dielectric layer 208 is lower than the bottom plane of the second region, that is, the first dielectric layer 208 is located on the sidewall of the bottom nanowire 201 and the first dielectric layer 208 is lower than the bottom plane of the sacrificial layer 202 at the bottom of the second region. So that the first dielectric layer 208 does not block the removal process when the sacrificial layer 202 and the top sacrificial layer 204 are subsequently removed.
The etching rate of the initial isolation structure 207 material by the process of etching back the initial first dielectric layer 206 is less than the etching rate of the initial first dielectric layer 206, so that the process of etching back the initial first dielectric layer 206 to form the first dielectric layer 208 has a larger etching selectivity ratio for the initial isolation structure 207, and thus the initial isolation structure 207 is less damaged.
Referring to fig. 5, the initial isolation structure 207 exposed by the first dielectric layer 208 is etched to form an isolation structure 209.
The isolation structures 209 have a second dimension in the direction of alignment of the nanostructures, the second dimension being smaller than the first dimension.
In this embodiment, the second dimension is in a range of 1 nm to 5 nm.
The process for etching the initial isolation structure 207 includes an isotropic dry etching process or an isotropic wet etching process.
In this embodiment, the process for etching the initial isolation structure 207 includes an isotropic dry etching process, and etching gases of the isotropic dry etching process include: carbon tetrafluoride and argon, or carbon tetrafluoride and helium.
The etching rate of the process for etching the initial isolation structure 207 on the material of the first dielectric layer 208 is less than the etching rate on the material of the initial isolation structure 207, so that the process for etching the initial isolation structure 207 has less damage on the first dielectric layer 208.
Thus, the isolation structure 209 is formed by first forming the initial isolation structure 207 with a larger size and then etching the initial isolation structure 207 to form the isolation structure 209. The isolation structure 209 formed by the method has smaller size, and can break through the limit of the photoetching limit, so that on one hand, the isolation structure 209 with smaller size can be obtained to meet the requirement of a semiconductor structure; on the other hand, the size accuracy of the formed isolation structure 209 is high, and meanwhile, the position of the isolation structure 209 can be adjusted, so that the isolation structure 209 can be positioned between adjacent nanostructures, and consequently, the size uniformity and the performance of a subsequently formed gate structure are good and uniform.
Next, after forming the isolation structure 209, the method further includes: gate structures are formed on the substrate 200, the gate structures spanning the nanostructures, and the isolation structures 209 isolating adjacent gate structures. Please refer to fig. 6 and fig. 7 for a process of forming the gate structure.
In this embodiment, the gate structure is a metal gate.
In other embodiments, the material of the gate structure may also be a polysilicon gate.
Referring to fig. 6, a dummy gate structure 211 is formed on the first dielectric layer 208, wherein the dummy gate structure 211 crosses over the nano-structure and the isolation structure 209; a second dielectric layer 212 is formed on the sidewalls of the dummy gate structure.
The dummy gate structure 211 includes a dummy gate dielectric layer (not shown) and a dummy gate layer (not shown) on the dummy gate dielectric layer.
The material of the pseudo gate dielectric layer comprises silicon oxide or low-K (K is less than 3.9) material; the material of the dummy gate layer comprises polysilicon.
The material of the second dielectric layer 212 includes a dielectric material including one or a combination of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon oxycarbonitride. In this embodiment, the material of the second dielectric layer 212 includes silicon oxide.
Referring to fig. 7, the dummy gate structure 211 is removed, and a first opening (not shown) is formed in the second dielectric layer 212; removing the sacrificial layer 202 and the top sacrificial layer 204 exposed by the first opening, and forming second openings (not shown) between adjacent nanowires 203 and between the nanowires 203 and the bottom nanowire 201; a gate structure 213 is formed within the first opening and within the second opening.
The process for removing the dummy gate structure 211 includes one or more of a dry etching process and a wet etching process.
The gate structure 213 includes: a gate dielectric layer (not shown) and a gate layer (not shown) on the gate dielectric layer. In this embodiment, the gate structure further includes a work function layer (not shown), and the work function layer is located between the gate dielectric layer and the gate electrode layer.
The gate dielectric layer comprises a high dielectric constant material, the dielectric constant of the high dielectric constant material is greater than 3.9, and the high dielectric constant material comprises aluminum oxide or hafnium oxide; the material of the gate layer comprises a metal, and the metal comprises tungsten; the material of the work function layer comprises an N-type work function material or a P-type work function material, the N-type work function material comprises titanium aluminum, and the P-type work function material comprises titanium nitride or tantalum nitride.
The method of forming the gate structure 213 within the first opening and within the second opening includes: forming a layer of gate structure material (not shown) within the first opening, within the second opening, on the nanostructures, and on the isolation structures 209; the gate structure material layer is planarized until the top surface of the isolation structure 209 is exposed, forming the gate structure 213.
Since the thickness of the top sacrificial layer 204 is greater than that of the sacrificial layer 202, it can be ensured that the height of the isolation structure 209 formed after the gate structure 213 is formed can be higher than that of the nano structure, so as to ensure that the isolation effect of the isolation structure 209 on the adjacent gate structure 213 is good. Thereby avoiding the situation that the isolation structure 209 is damaged too much in the process of planarizing the gate structure material layer, so that the adjacent gate structure 213 is short-circuited when the height of the isolation structure 209 is lower than that of the nano structure.
Fig. 8 and 9 are schematic cross-sectional views of a semiconductor structure in another embodiment of the invention.
In this embodiment, after forming the dummy gate structure and the first opening, the initial isolation structure 207 is etched to form an isolation structure.
Referring to fig. 8, fig. 8 is a schematic structural diagram based on fig. 4, wherein a dummy gate structure 311 is formed on the first dielectric layer 208, and the dummy gate structure 311 crosses over the nano-structure and the initial isolation structure 207; a second dielectric layer 312 is formed on the sidewall of the dummy gate structure 311.
Please refer to fig. 6 for a method, a process and a material in the process of forming the dummy gate structure 311 and the second dielectric layer 312, which are not described herein again.
Referring to fig. 9, the dummy gate structure 311 is removed, a first opening 313 is formed in the second dielectric layer 312, and the initial isolation structure 207 is exposed by the first opening 313; etching the first opening 313 exposing the initial isolation structure 207 to form an isolation structure 307.
The process of removing the dummy gate structure 311 includes one or more of a dry etching process and a wet etching process.
Please refer to fig. 5 for a process and a step of etching the initial isolation structure 207 to form the isolation structure 307, which will not be described herein again.
After the isolation structure 307 is formed, the method further includes: removing the sacrificial layer 202 and the top sacrificial layer 204 exposed by the first opening 313 to form second openings between the adjacent nanowires 203 and between the nanowires 203 and the bottom nanowires 201; a gate structure is formed within the first opening and within the second opening. Please refer to fig. 7 for the steps, processes and materials for removing the sacrificial layer 202 and the top sacrificial layer 204 and forming the gate structure, which are not described herein again.
In other embodiments, after removing the sacrificial layer exposed by the first opening and the top sacrificial layer, the initial isolation structure may be etched to form an isolation structure. The isolation structure can be formed in different process steps, so that the process for forming the isolation structure is high in flexibility and good in compatibility with other processes, and the production efficiency is improved.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (16)

1. A method of forming a semiconductor structure, comprising:
providing a substrate;
forming a plurality of discrete nanostructures on a substrate, with a groove between adjacent nanostructures;
forming a first dielectric layer and an initial isolation structure on a substrate, wherein the top surface of the first dielectric layer is lower than the top surface of the nano structure, the first dielectric layer is positioned on the partial side wall surface of the initial isolation structure, and the initial isolation structure is positioned in at least one groove;
and etching the initial isolation structure exposed out of the first dielectric layer to form an isolation structure.
2. The method of forming a semiconductor structure of claim 1, wherein the method of forming the initial isolation structure and the first dielectric layer comprises: forming an initial first dielectric layer on the substrate, wherein the initial first dielectric layer is positioned in the groove; forming a patterned mask structure on the initial first dielectric layer, wherein the mask structure exposes a part of the surface of the initial first dielectric layer in the groove; etching the initial first dielectric layer by taking the mask structure as a mask until the surface of the substrate is exposed, and forming an isolation opening in the initial first dielectric layer; forming the initial isolation structure within an isolation opening; and after the initial isolation structure is formed, etching the initial first dielectric layer back to form a first dielectric layer, wherein part of the initial isolation structure is exposed out of the first dielectric layer, and the top surface of the first dielectric layer is lower than that of the nano structure.
3. The method of claim 1, wherein the initial isolation structure has a first dimension in the direction of alignment of the nanostructures, and wherein the isolation structure has a second dimension in the direction of alignment of the nanostructures, the second dimension being less than the first dimension.
4. The method of forming a semiconductor structure of claim 3, wherein the first dimension ranges from greater than 10 nanometers; the second dimension is in a range of 1 nanometer to 5 nanometers.
5. The method of forming a semiconductor structure of claim 1, wherein the process of etching the initial isolation structure comprises an isotropic dry etch process or an isotropic wet etch process.
6. The method of forming a semiconductor structure of claim 5, wherein the etching gas of the isotropic dry etching process comprises: carbon tetrafluoride and argon, or carbon tetrafluoride and helium.
7. The method of forming a semiconductor structure of claim 1, wherein the nanostructure comprises: a first region, a second region located on the first region, and a third region located on the second region; the first area comprises bottom layer nanowires, the first dielectric layer is positioned on the side wall of the first area and is lower than the bottom plane of the second area; the second area comprises a plurality of composite layers, and each composite layer comprises a sacrificial layer and nanowires positioned on the sacrificial layer; the third region includes a top sacrificial layer.
8. The method of forming a semiconductor structure of claim 7, wherein a thickness of the top sacrificial layer is greater than a thickness of the sacrificial layer; the thickness of the top sacrificial layer is 3-10 nanometers larger than that of the sacrificial layer.
9. The method of forming a semiconductor structure of claim 7, further comprising, after forming the isolation structure: forming a gate structure on the substrate, the gate structure spanning the nanostructures, and the isolation structure isolating adjacent gate structures.
10. The method of forming a semiconductor structure of claim 9, wherein a material of the gate structure comprises a metal.
11. The method of forming a semiconductor structure of claim 10, wherein the method of forming a gate structure comprises: after the isolation structure is formed, forming a dummy gate structure on the first dielectric layer, wherein the dummy gate structure spans the nano structure and the isolation structure; forming a second dielectric layer on the side wall of the pseudo gate structure; removing the pseudo gate structure, and forming a first opening in the second dielectric layer; removing the sacrificial layer and the top sacrificial layer exposed by the first opening, and forming second openings between adjacent nanowires and between the bottom nanowire and the nanowire; a gate structure is formed within the first opening and within the second opening.
12. The method of forming a semiconductor structure of claim 10, wherein the method of forming a gate structure comprises: forming a dummy gate structure on the first dielectric layer before forming the isolation structure, wherein the dummy gate structure spans the nano-structure and the initial isolation structure; forming a second dielectric layer on the side wall of the pseudo gate structure; and removing the pseudo gate structure, and forming a first opening in the second dielectric layer, wherein the first opening exposes the initial isolation structure.
13. The method of forming a semiconductor structure of claim 12, wherein the method of forming the gate structure comprises: after the isolation structure is formed, removing the sacrificial layer and the top sacrificial layer exposed by the first opening, and forming second openings between adjacent nanowires and between the bottom nanowire and the nanowire; a gate structure is formed within the first opening and within the second opening.
14. The method of forming a semiconductor structure of claim 1, wherein a material of the initial first dielectric layer has a different etch rate than a material of the initial isolation structure.
15. The method of forming a semiconductor structure of claim 14, wherein a material of the initial first dielectric layer comprises a dielectric material comprising silicon oxide.
16. The method of forming a semiconductor structure of claim 14, wherein the material of the initial isolation structure comprises a dielectric material comprising silicon nitride.
CN202010963310.9A 2020-09-14 2020-09-14 Method for forming semiconductor structure Pending CN114188276A (en)

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