CN114187948A - Read-only memory array structure, chip, electronic equipment and coding method - Google Patents

Abstract

The application provides a read-only memory array structure, which comprises m × n memory cells arranged in a matrix, m word lines and n bit lines, wherein m and n are natural numbers which are larger than or equal to 1. Each memory cell comprises a grid electrode, a source electrode and a drain electrode; the m word lines correspond to the m rows of storage units one by one; the n bit lines correspond to the n columns of storage units one by one, and each bit line is connected with the drain electrode of the storage unit in the corresponding column; wherein, the source electrode of each memory cell is grounded; the gate of each memory cell is connected to a corresponding word line or grounded, depending on whether the data stored in the memory cell is "0" or "1". The application also provides a chip and an electronic device comprising the chip. The application also provides an encoding method. The load of the word line can be effectively reduced, and the storage performance is improved.

Description

Read-only memory array structure, chip, electronic equipment and coding method

Technical Field

The present disclosure relates to the field of chip technologies, and in particular, to a read only memory array structure, a chip, an electronic device, and an encoding method.

Background

At present, with the development of technology, electronic devices (such as smart phones, tablet computers, personal computers, and the like) and the like have been widely used. The memory is an indispensable part of the electronic equipment as an information storage device of the electronic equipment, and the memory and storage technology also becomes one of the key technical fields for promoting the development of the information age. Among the most widely used memories, a typical Memory is a Read Only Memory (ROM). The read-only memory is an N-type fet read-only memory. Generally, the array arrangement structure of the read only memory has a significant influence on the performance of the memory. How to provide an array arrangement structure of a read-only memory to improve the performance of the memory becomes a problem to be solved.

Disclosure of Invention

The embodiment of the application provides a read-only memory array structure, a chip, electronic equipment and an encoding method, which can effectively reduce word line load and improve the performance of a memory.

In a first aspect, an embodiment of the present application provides a rom array structure, which includes m × n memory cells arranged in a matrix, m word lines, and n bit lines, where m and n are natural numbers greater than or equal to 1. Each memory cell comprises a grid electrode, a source electrode and a drain electrode; the m word lines correspond to the m rows of storage units one by one; the n bit lines correspond to the n columns of storage units one by one, and each bit line is connected with the drain electrode of the storage unit in the corresponding column; wherein, the source electrode of each memory cell is grounded; the gate of each memory cell is connected to a corresponding word line or grounded, depending on whether the data stored in the memory cell is "0" or "1".

In a second aspect, embodiments of the present application provide a chip including a read only memory array structure. The read-only memory array structure comprises m × n memory cells arranged in a matrix, m word lines and n bit lines, wherein m and n are natural numbers larger than or equal to 1. Each memory cell comprises a grid electrode, a source electrode and a drain electrode; the m word lines correspond to the m rows of storage units one by one; the n bit lines correspond to the n columns of storage units one by one, and each bit line is connected with the drain electrode of the storage unit in the corresponding column; wherein, the source electrode of each memory cell is grounded; the gate of each memory cell is connected to a corresponding word line or grounded, depending on whether the data stored in the memory cell is "0" or "1".

In a third aspect, an embodiment of the present application provides an electronic device, which includes a chip including a read-only memory array structure. The read-only memory array structure comprises m × n memory cells arranged in a matrix, m word lines and n bit lines, wherein m and n are natural numbers larger than or equal to 1. Each memory cell comprises a grid electrode, a source electrode and a drain electrode; the m word lines correspond to the m rows of storage units one by one; the n bit lines correspond to the n columns of storage units one by one, and each bit line is connected with the drain electrode of the storage unit in the corresponding column; wherein, the source electrode of each memory cell is grounded; the gate of each memory cell is connected to a corresponding word line or grounded, depending on whether the data stored in the memory cell is "0" or "1".

It can be seen that, in the embodiment of the present application, since the word line is connected to only a portion of the memory cells, the number of the memory cells connected to the word line can be effectively reduced, and the load of the word line can be reduced while data "0" or "1" is stored as required, thereby improving the overall performance of the rom array structure.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and other modifications can be obtained by those skilled in the art without creative efforts.

Fig. 1 is a schematic structural diagram of a rom array structure according to an embodiment of the present application.

FIG. 2 is a schematic diagram of a memory cell connected to a word line according to an embodiment of the present application.

Fig. 3 is a schematic diagram illustrating a memory cell connected to a second ground according to an embodiment of the present application.

Fig. 4 is a schematic plan view illustrating a multi-layer structure of a rom array structure according to an embodiment of the present invention.

FIG. 5 is a side view of a multi-layer structure illustrating a read-only memory array structure according to an embodiment of the present application.

FIG. 6 is a top view of a read-only memory array structure illustrating the structure of a memory cell according to an embodiment of the present application.

Fig. 7 is a block diagram of a chip according to an embodiment of the present application.

Fig. 8 is a block diagram of an electronic device according to an embodiment of the present application.

Fig. 9 is a flowchart of an encoding method in an embodiment of the present application.

Detailed Description

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The terms "first," "second," "third," and "fourth," etc. in the description and claims of this application and in the accompanying drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions.

Here, "connected" in the present application mainly means "electrically connected" unless otherwise specified.

The electronic device in the present application may include a handheld device including a memory, such as a Mobile phone and a tablet computer, and may also include a vehicle-mounted device, a wearable device, a computing device or other processing devices connected to a wireless modem, and various forms of User Equipment (UE) including a memory, a Mobile Station (MS), a terminal device (terminal device), and the like.

Please refer to fig. 1, which is a schematic structural diagram of a rom array structure 1 according to an embodiment of the present application. As shown in fig. 1, the rom array structure 1 includes m × n memory cells 11 arranged in a matrix, m word lines WL, and n bit lines BL, where m and n are natural numbers greater than or equal to 1. Each memory cell 11 includes a gate G, a source S and a drain D; the m word lines WL correspond to the m rows of memory cells 11 one by one; the n bit lines correspond to the n columns of memory cells 11 one by one, and each bit line is connected with the drain of the memory cell 11 in the corresponding column; wherein, the source S of each memory cell 11 is grounded; here, the gate G of each memory cell 11 is connected to the corresponding word line WL or grounded according to whether the data stored in each memory cell 11 is "0" or "1".

Therefore, in the present application, since the word lines WL are connected to only some of the memory cells 11, the number of memory cells 11 to which the word lines WL are connected can be effectively reduced, and the load on the word lines WL is reduced while data "0" or "1" is stored as needed, thereby improving the overall performance of the rom array structure 1. Among other things, improving the overall performance of the read only memory array structure 1 may include performance improvements such as reduced power consumption.

In some embodiments, as shown in fig. 1, each word line WL extends in the row direction across a corresponding row of memory cells 11; each bit line BL extends in the column direction past a corresponding column of memory cells 11. That is, in some embodiments, m word lines WL correspond to m rows of memory cells 11 one-to-one as follows: each word line WL extends in the row direction through a corresponding row of memory cells 11, corresponding to the location of the memory cells 11 of the corresponding row; the one-to-one correspondence between the n bit lines BL and the n columns of memory cells 11 is: each bit line extends in the column direction through a corresponding column of memory cells corresponding to the location of the memory cells 11 of the corresponding column.

As shown in fig. 1, the rom array structure 1 further includes n first ground lines VSS1 and n second ground lines VSS2, where each first ground line VSS1 extends through a corresponding column of memory cells 11 along the column direction and is connected to the sources of the corresponding column of memory cells 11 to ground the source of each memory cell 11; each second ground VSS2 extends in the column direction across a corresponding column of memory cells 11. Here, the gate G of each memory cell 11 is connected to the corresponding word line WL or connected to the corresponding second ground VSS2 and grounded according to whether the data stored in each memory cell 11 is "0" or "1".

Wherein m and n can be any natural number greater than or equal to 1, and m and n can be equal or unequal. The rom array 1 in fig. 1 only illustrates three rows and three columns of memory cells 11, i.e., m ═ n ═ 3, and it is obvious that the number of memory cells 11 included in the rom array 1 can be determined according to the size of the total data stored.

Here, the positions where the word line WL intersects the bit line BL, the first ground line VSS1 and the second ground line VSS2 shown in fig. 1 are not connected positions but positions overlapping in projection. The second ground VSS2 shown in fig. 1 extends through the gate G of each column of memory cells 11, which does not mean that the second ground VSS2 is connected to the gate G of each column of memory cells 11, and as mentioned above, the gate G of each memory cell 11 is connected to the corresponding word line WL or the corresponding second ground VSS2 according to whether the data stored in each memory cell 11 is "0" or "1". In order to avoid too many lines, the first ground line VSS1 is symbolized in fig. 1.

Here, the "row direction" in the present application refers to the arrangement direction of the memory cells 11 in one row, and the "column direction" in the present application refers to the arrangement direction of the memory cells 11 in one column.

Fig. 1 is an equivalent schematic diagram, not an actual schematic diagram, of the rom array structure 1.

The one-to-one correspondence between the m word lines WL and the m rows of memory cells 11 mainly means that the m word lines WL are respectively used for the m rows of memory cells 11, and the one-to-one correspondence between the n bit lines BL and the n columns of memory cells 11 means that the n bit lines BL are respectively used for the n columns of memory cells 11. Obviously, the m word lines WL may be disposed at any position, but when the gates G of some memory cells 11 in a certain row need to be connected to the word lines WL, the m word lines WL are connected to the word lines WL corresponding to the memory cells 11 in the row through electrical connectors such as wires and flexible printed circuit boards. In other embodiments, the n bit lines BL may also be disposed at any position, and each bit line may be further connected to the drain D of the corresponding column of memory cells 11 through an electrical connection component such as a conductive wire or a flexible circuit board.

In other embodiments, the rom array structure may not include the n first ground lines VSS1 and the n second ground lines VSS 2. The source of each memory cell 11 can be directly connected to ground through electrical connectors such as wires and flexible circuit boards, and when the gates G of some memory cells 11 need to be grounded, the sources can be directly connected to ground through electrical connectors such as wires and flexible circuit boards.

Referring to fig. 2 and 3 together, fig. 2 is a schematic diagram illustrating the connection of the memory cell 11 to the word line WL, and fig. 3 is a schematic diagram illustrating the connection of the memory cell 11 to the second ground VSS 2. As shown in fig. 2 and 3, when data stored in a certain memory cell 11 is "0", the gate G of the memory cell 11 is connected to the corresponding word line WL, and when data stored in a certain memory cell 11 is "1", the gate G of the memory cell 11 is connected to the corresponding second ground VSS 2.

Specifically, when the data stored in a certain memory cell 11 is "0", the memory cell 11 is configured such that the gate G is connected to the corresponding word line WL, and when the data stored in a certain memory cell 11 is "1", the memory cell 11 is configured such that the gate G is connected to the corresponding second ground VSS 2.

As shown in fig. 2 and 3, the drain D of the memory cell 11 is connected to the bit line BL, and the source S is connected to the first ground line VSS 1. The first ground line VSS1 and the second ground line VSS2 are used for grounding and are at zero potential, i.e., at a low level, wherein the first ground line VSS1 and the second ground line VSS2 may be connected to the same ground or different grounds. The bit line BL is typically precharged to a high level, i.e., is typically at a high level, before being subjected to a data read. The word line WL is used to apply a high level signal, for example, the word line WL may always apply the high level signal or apply the high level signal when data reading is performed.

In the present embodiment, the memory cell 11 is an N-type field effect transistor (NMOSFET, all referred to as N-channel metal oxide field effect transistor). Accordingly, when the gate G of the memory cell 11 is connected to the corresponding word line WL, the gate G of the memory cell 11 is at a high level, so that the memory cell 11 is in a conductive state, the drain D and the source S of the memory cell 11 are equivalent to a short circuit, and therefore, the drain D of the memory cell 11 connected to the bit line BL is pulled down to a low level. When the gate G of the memory cell 11 is connected to the corresponding second ground VSS2, the gate G of the memory cell 11 is at a low level, so that the memory cell 11 is in an off state, and the drain D and the source S of the memory cell 11 are equivalent to open circuits, and therefore, the drain D of the memory cell 11 connected to the bit line BL is maintained at a high level.

The bit line BL serves as a data output terminal of the memory cell 11. Since the data corresponding to the high level is "1" and the data corresponding to the low level is "0", the data stored in the memory cell 11 can be read by reading the level of the bit line BL, that is, whether the stored one bit data (bit) is "0" or "1".

Therefore, the above-mentioned "when the data stored in a certain memory cell 11 is" 0 ", the gate G of the memory cell 11 is connected to the corresponding word line WL, and when the data stored in a certain memory cell 11 is" 1 ", the gate G of the memory cell 11 is connected to the corresponding second ground VSS 2", and actually: when it is required that data stored in a certain memory cell 11 is "0", the memory cell 11 is configured such that the gate G is connected to the corresponding word line WL, so that the memory cell 11 outputs a low level through the bit line BL and is read as data "0"; when it is required that a certain memory cell 11 stores data "1", the memory cell 11 is configured such that the gate G is connected to the corresponding second ground VSS2, so that the memory cell 11 outputs a high level through the bit line BL and is read as data "1".

The rom array 1 is not writable, but only readable. And the process of reading data from the rom array 1 may be performed by line scanning. In some embodiments, the specific scanning pattern is as follows.

Referring back to fig. 1, the m word lines WL are distributed in m rows, including WL0, wl1.. WLm, where fig. 1 only illustrates three rows of word lines: WL0, WL1, and WL2, wherein the plurality of bit lines BL are distributed in a plurality of columns, including BL0, bl1.. BLn, wherein fig. 1 only illustrates three columns of bit lines: BL0, BL1, and BL 2. Here, when a high level is applied to a plurality of rows of word lines WL in sequence, the gate G of a memory cell 11 whose data is "0" stored in a memory cell 11 in a row corresponding to the row of word lines WL is connected to the row of word lines WL, so that the bit line BL in the corresponding column outputs a low level and is read as "0", and the gate of a memory cell 11 whose data is "1" stored in the memory cell 11 in the row is connected to the second ground line VSS2, so that the bit line BL in the corresponding column outputs a high level and is read as "1". Since the intersection position of a row word line WL and a column bit line BL is the position of the memory cell 11, the row position can be known from the word line WL currently applying a high level, and the column position can be known from the bit line BL currently outputting a high level or a low level, so that the identity of the memory cell 11 and the data read from the memory cell 11 can be uniquely determined. Therefore, the read one-bit data of the memory cells 11 in each row and each column can be known, and the corresponding multi-bit data can be combined according to the position of the memory cells 11 in each row and each column in one multi-bit data.

Accordingly, in the manufacturing process of the rom array 1, it can be determined whether the data to be stored in each memory cell is "1" or "0" according to the multi-bit data corresponding to the specific content to be stored in the rom array and the position of the memory cell in each row and column of the multi-bit data.

The multi-bit data may be one or more bytes, each byte including 8-bit (bit) data, or the multi-bit data may be a data string including any number of bits, for example, 4-bit data, 9-bit data, and so on. The specific content may be a product serial number, factory information, and other read-only content of the electronic device in which the rom array structure 1 is located.

Referring to the drawings together with fig. 4 and 5, fig. 4 is a schematic plan view illustrating a multi-layer structure of the rom array structure 1 in an embodiment of the present application, and fig. 5 is a schematic side view illustrating the multi-layer structure of the rom array structure 1 in an embodiment of the present application. Fig. 4 only shows 4 memory cells 11 arranged in a 2 × 2 matrix, and fig. 5 shows a side view of a row of memory cells, i.e. 2 memory cells 11 on the same row.

In some embodiments of the present application, the gate G of the memory cell 11 is connected to the corresponding word line WL through the formed first conductive via K1, and the gate G of the memory cell 11 is connected to the corresponding second ground VSS2 through the formed second conductive via K2.

That is, when it is required that a certain memory cell 11 stores data of "0", the gate G of the memory cell 11 is connected to the corresponding word line WL by forming the first conductive via K1; when it is required that a certain memory cell 11 stores data of "1", the gate G is connected to the corresponding second ground VSS2 through the formed second conductive via K2.

As shown in fig. 4 and fig. 5, the rom array structure 1 further includes n word line connection bars 12, each word line connection bar 12 also extends through a corresponding row of memory cells 11 along the row direction, and the n word line connection bars 12 and the n second ground lines VSS2 are disposed in parallel and alternately on the same layer, wherein each memory cell 11 further includes a gate connection line GL, the gate connection line GL is connected to the gate G of the memory cell 11, the n word line connection bars 12 and the n second ground lines VSS2 are disposed on a side of the memory cell 11 where the gate connection line GL is disposed, and the m word lines WL are specifically disposed on a side of the n word line connection bars 12 away from the memory cell 11.

When the data stored in a memory cell 11 is "0", a first conductive sub-via K11 is opened on a corresponding word line WL, and a second conductive sub-via K12 is opened on a corresponding word line connecting bar 12 at a position crossing the gate connecting line GL, and the first conductive sub-via K11 is connected to the second conductive sub-via K12 to form the first conductive via K1, so that the word line WL is connected to the gate connecting line GL through the first conductive sub-via K11 and the second conductive sub-via K12, and the gate G of the memory cell 11 is connected to the corresponding word line WL; when data stored in a memory cell 11 is "1", the second conductive via K2 is opened at a position on the corresponding second ground VSS2, which crosses the gate line GL, so that the second ground VSS2 is connected to the gate line GL, and the gate G of the memory cell 11 is connected to the corresponding second ground VSS.

As shown in fig. 5, the word line connecting bar 12 and the gate connecting line GL are disposed at different layers, the second ground VSS2 is disposed at the same layer as the word line connecting bar 12, and the second ground VSS2 is also disposed at different layers from the gate connecting line GL. The position of the second ground line VSS2 intersecting the gate connection line GL means a position of the second ground line VSS2 where a projection onto the memory cell 11 coincides with the gate connection line GL.

Each of the word lines WL, the second ground lines VSS2, and the word line connecting bars 12 are conductive lines wrapped with an insulating material, and the gate connecting lines GL are exposed conductive lines, i.e., conductive lines not including an insulating material but exposed from a conductive material. When the word line WL opens the first conductive sub-via K11, the word line WL can be electrically connected through the first conductive sub-via K11, that is, the conductive material of the word line WL is exposed through the first conductive sub-via K11 and can be electrically connected to other conductive objects, for example, the second conductive sub-via K12. When the word line connection bar 12 is provided with the second conductive sub-via K12, the word line connection bar 12 can be electrically connected through the second conductive sub-via K12, that is, the conductive material of the word line connection bar 12 is exposed through the second conductive sub-via K12 and can be electrically connected to other conductive objects, for example, the first conductive sub-via K11 and the gate connection line GL. When the second conductive via K2 is opened on the second ground VSS2, the second ground VSS2 can be electrically connected through the second conductive via K2, that is, the conductive material of the second ground VSS2 is exposed through the second conductive via K2 and can be electrically connected to other conductive objects, for example, the gate link GL.

As shown in fig. 5, the first conductive sub via K11 is located opposite to the second conductive sub via K12, i.e., the projection of the first conductive sub via K11 on the word line connecting bar 12 completely coincides with the second conductive sub via K12. Obviously, in another embodiment, the projection of the first conductive sub-via K11 on the word line connection bar 12 may partially coincide with the second conductive sub-via K12. Thus, a conductive path is formed by the contact of the overlapped area of the first conductive sub via K11 and the second conductive sub via K12.

In other embodiments, the projection of the first conductive sub-via K11 on the word line connection bar 12 is not overlapped with the second conductive sub-via K12 completely, i.e. there is no overlapped area, the first conductive sub-via K1 may further include a third conductive sub-via (not shown), which is opened on the word line connection bar 12 and corresponds to the position of the first conductive sub-via K11 and is electrically connected to the first conductive sub-via K11, the third conductive sub-via and the second conductive sub-via K12 are electrically connected through the conductive material of the word line connection bar 12, and then electrically connected to the gate connection line GL through the second conductive sub-via K12.

In order to better show the respective structures, word lines WL in fig. 4 are indicated by dashed boxes. As mentioned above, the word lines WL are arranged on the side of the word line connecting bar 12 facing away from the memory cells 11. In the 2 x 2 matrix shown in fig. 4, the gate G of the memory cell 11 in the first row and the first column (i.e., the upper left corner in the figure) of the memory cell 11 is connected to the corresponding second ground VSS2 through the second conductive via K2, and the memory cell 11 stores data "1"; the gates G of the memory cells 11 in the first row and the second column (i.e., the upper right corner in the figure) of the memory cells 11 are connected with the corresponding word lines WL and the word line connecting bars 12 through the first conductive vias K1, and the memory cells 11 store data "0"; the gates G of the memory cells 11 in the second row and the second column of the memory cells 11 (i.e., the lower left corner in the figure) are connected to the corresponding word lines WL and the word line connecting bars 12 through the first conductive vias K1, and the data stored in the memory cells 11 is "0"; the gate G of the memory cell 11 in the second row and the second column (i.e., the lower right corner in the figure) of the memory cell 11 is connected to the corresponding second ground VSS2 through the second conductive via K2, and the memory cell 11 stores data "1".

As shown in fig. 4 and 5, each memory cell 11 further includes a substrate layer 111, the source S and the drain D of the memory cell 11 are formed on the substrate layer 111 at intervals, and the source G of the memory cell 11 is stacked above the source S and the drain D and connected to both the source S and the drain D. The source connection line GL is drawn from the source S to extend a predetermined distance in a row direction.

Fig. 5 is a schematic side view of a row of memory cells 11 of the rom array 1 viewed from the side, and is not a sectional view, but only for illustrating the spatial stacking relationship of the structures in the rom array 1. It should be noted that fig. 5 is also only an example, and the lamination relationship of the partial structures is not limited thereto, for example, the bit line BL and the first ground line VSS1 may be disposed below the gate line GL or above the gate line GL.

As shown in fig. 4, the memory cells 11 in the same column share the same substrate layer 111, that is, the substrate layer 111 may be arranged in multiple columns, and the source S and the drain D of each column of memory cells 11 are formed on the substrate layer 111 in the corresponding column.

In some embodiments, each bit line BL and the drain D of the corresponding column of memory cells 11 may be connected by means of a via, for example, by means of the aforementioned conductive via. Each source connection to a corresponding column of memory cells 11 may also be by way of a via, for example by way of the aforementioned conductive via. As shown in fig. 4, each bit line BL is connected to the drain D of the memory cell 11 of the corresponding column through a conductive via V1, and each first ground line VSS1 is connected to the source of the memory cell 11 of the corresponding column through a conductive via V2.

As shown in fig. 4, the gate connection lines GL extend in a row direction, and the read only memory array structure 1 further includes a gate disconnection layer 13 extending in a column direction for separating the gate connection lines GL of different memory cells 11.

Wherein the gate break layer 13 is an insulating material layer. The number of the gate break layers 13 is n-1, and each gate break layer 13 is located between two adjacent columns of the memory cells 11. In the manufacturing process, the gate connecting lines GL of the memory cells 11 in the same row are a whole line, and the gate disconnecting layer 13 is disposed between two adjacent rows of the memory cells 11, so that the whole row of the gate connecting lines GL can be divided into n independent gate connecting lines GL. More specifically, a portion of the conductive material of the gate connection line GL corresponding to the location of the gate break layer 13 may be removed, and then the gate break layer 13 may be disposed at the portion.

Each word line WL extends through a corresponding row of memory cells 11 in the row direction, each bit line extends through a corresponding column of memory cells in the column direction, each first ground line VSS1 extends through a corresponding column of memory cells 11 in the column direction, and each second ground line VSS2 extends through a corresponding column of memory cells 11 in the column direction, which is mainly convenient for the electrical connection with the memory cells 11 by opening conductive vias as shown in fig. 4 and 5.

Obviously, as mentioned above, in other embodiments, the m word lines WL may be disposed at any position, but when the gates G of some memory cells 11 in a certain row need to be connected to a word line WL, the m word lines WL are connected to the word line WL corresponding to the memory cells 11 in the row through electrical connectors such as wires and flexible circuit boards. In other embodiments, the n bit lines BL may also be disposed at any position, and each bit line may be further connected to the drain D of the corresponding column of memory cells 11 through an electrical connection component such as a conductive wire or a flexible circuit board. The read only memory array structure may not include the n first ground lines VSS1 and the n second ground lines VSS 2. The source of each memory cell 11 can be directly connected to ground through electrical connectors such as wires and flexible circuit boards, and when the gates G of some memory cells 11 need to be grounded, the sources can be directly connected to ground through electrical connectors such as wires and flexible circuit boards. That is, in other embodiments, the gate G, the drain D, and the source S of each memory cell 11 may be connected to the corresponding word line WL or ground, the bit line BL, and the ground without opening a conductive via, but may be connected to a conductive wire, a flexible circuit board, or other electrical connection components.

Fig. 6 is a schematic top view of a memory cell 11 of the rom array structure 1 according to an embodiment of the present invention. In fig. 6, a 3 × 3 matrix structure is exemplified.

As shown in fig. 6, the sources S and the drains D of the memory cells 11 arranged in the same column are arranged in a staggered manner, that is, the sources S and the drains D of the same memory cells 11 are respectively arranged on two opposite sides of the substrate layer 111 in a predetermined direction, and projections of the sources S and the drains D in the predetermined direction do not overlap, that is, the sources S and the drains D of the same memory cells 11 are distributed diagonally in a region of the substrate layer 111 corresponding to the memory cells 11. Wherein the preset direction is a row direction.

As shown in fig. 6, the sources S of two adjacent memory cells 11 are shared, and/or the drains D of two adjacent memory cells 11 are shared. Specifically, as shown in fig. 6, when a certain memory cell 11 is not a memory cell 11 located in the first row or the last row, the memory cell 11 is located between two memory cells 11, the source S of the memory cell 11 is shared with the source S of an adjacent memory cell 11, and the drain D of the memory cell 11 is shared with the drain D of another adjacent memory cell 11 on the other side. As shown in fig. 6, the drain D of the memory cell 11 in the first row is an independent drain, and only the source S is shared with the source S of the memory cell 11 in the adjacent second row, while the source S of the memory cell 11 in the last row is an independent source, and only the drain D is shared with the drain D of the memory cell 11 in the adjacent second row.

That is, in the present application, the common use of the sources S of two adjacent memory cells 11 and/or the common use of the drains D of two adjacent memory cells 11 also means: when there is an adjacent memory cell 11 on the source S side of each memory cell 11, it is shared with the source S of the adjacent memory cell 11, and when there is an adjacent memory cell 11 on the drain D side of each memory cell 11, it is shared with the drain D of the adjacent memory cell 11.

Therefore, in the present application, the source S of two adjacent memory cells 11 is shared, and/or the drain D of two adjacent memory cells 11 is shared, so that the size of the rom array structure 1 can be effectively reduced.

Therefore, the read-only memory array structure 1 of the present application can effectively reduce the number of the memory cells 11 connected to the word lines WL, reduce the load of the word lines WL, and improve the overall performance of the read-only memory array structure 1 while realizing the storage of data "0" or "1" as required. And because the sources S of two adjacent memory cells 11 are shared and/or the drains D of two adjacent memory cells 11 are shared, the size of the rom array structure 1 can be effectively reduced.

Fig. 7 is a block diagram of a chip 100 according to an embodiment of the present application. The chip 100 includes the aforementioned read only memory array structure 1.

The chip 100 may be any chip including a read-only memory device, such as a processor chip, a memory chip, a graphics card chip, and the like.

Please refer to fig. 8, which is a block diagram illustrating an electronic device 200 according to an embodiment of the present disclosure. The electronic device 200 comprises the chip 100.

The electronic device 200 may be a mobile phone, a tablet computer, a personal computer, a server, a wireless network device, a vehicle-mounted device, or the like, and the electronic device 200 includes the chip 100 having the read-only memory device.

Please refer to fig. 9, which is a flowchart illustrating an encoding method according to an embodiment of the present application. The encoding method can be used for encoding the storage data for generating the read-only memory array structure. The encoding method includes the steps of:

data to be stored in each storage unit of the read only memory array structure is determined (S901).

The gate of each memory cell is controlled to be connected to a corresponding word line or grounded according to whether the data stored in each memory cell is '0' or '1' (S903).

The rom array structure includes m × n columns of memory cells, where m and n are natural numbers greater than or equal to 1, and the step S901 may include: and determining whether the data to be stored in each storage unit is 1 or 0 according to the multi-bit data corresponding to the specific content to be stored in the read-only memory array structure and the position of the storage unit in each row and each column of the multi-bit data. The multi-bit data may be one or more bytes, each byte including 8-bit (bit) data, or the multi-bit data may be a data string including any number of bits, for example, 4-bit data or 9-bit data.

In some embodiments, the read only memory array structure further includes m word lines, n bit lines, n first ground lines, and n second ground lines. Each memory cell comprises a grid electrode, a source electrode and a drain electrode; each word line extends in a row direction through a corresponding row of memory cells; each bit line extends through a corresponding column of memory cells along the column direction and is connected with the drain electrode of the memory cell of the corresponding column; each first ground wire extends through the corresponding column of storage units along the column direction and is connected with the source electrode of the storage unit of the corresponding column; each second ground line extends through a corresponding column of memory cells in the column direction. Wherein the step S903 includes: when data stored in a certain memory cell is "0", the gate of the memory cell is connected to the corresponding word line, and when data stored in a certain memory cell is "1", the gate of the memory cell is connected to the corresponding second ground.

Wherein, the "when the data stored in a certain memory cell is" 0 ", the gate of the memory cell is connected to the corresponding word line" may further include: when data stored in a certain memory cell is '0', the gate of the memory cell is connected with a corresponding word line by forming a first conductive via. The "when data stored in a certain memory cell is" 1 ", the gate of the memory cell is connected to the corresponding second ground" may further include: when the data stored in a certain memory cell is required to be 1, the gate is connected with the corresponding second ground through the formed second conductive through hole.

Wherein the first and second conductive vias may be formed by chemical or physical means, such as by laser drilling.

In some embodiments, the rom array structure further includes n word line connection bars, each word line connection bar extends through a corresponding row of the memory cells along a row direction, and the n word line connection bars and the n second ground are parallel and alternately disposed on the same layer, wherein each memory cell further includes a gate connection line, the gate connection line is connected to the gate of the memory cell, the n word line connection bars and the n second ground are disposed on one side of the memory cell where the gate connection line is disposed, and the m word lines are disposed on one side of the n word line connection bars away from the memory cell.

Wherein, the step of connecting the gate of a certain memory cell to the corresponding word line by forming the first conductive via when the data stored in the memory cell is "0" may further specifically include: when data stored in a certain memory cell is '0', a first conductive sub-through hole is formed in a corresponding word line WL, and a second conductive sub-through hole is formed in a position, which is intersected with the gate connection line, on a corresponding word line connection bar, and the second conductive sub-through hole is connected with the first conductive sub-through hole to form the first conductive through hole, so that the word line is connected with the gate connection line through the first conductive sub-through hole and the second conductive sub-through hole, and the gate of the memory cell is connected with the corresponding word line.

The "when data stored in a certain memory cell is required to be" 1 ", the connecting the gate electrode to the corresponding second ground through the formed second conductive via" may specifically include: when the data stored in a certain memory cell is "1", the second conductive through hole is formed in the position, which is crossed with the gate connecting line, on the corresponding second ground line, so that the second ground line is connected with the gate connecting line, and the gate of the memory cell is connected with the corresponding second ground line.

Therefore, in the manufacturing process of the rom array structure 1, whether data to be stored in each memory cell is "0" or "1" can be determined according to the multi-bit data corresponding to specific content to be stored in the rom array structure and the position of the memory cell in each row and each column of the multi-bit data, and then the gate of the memory cell can be connected to a corresponding word line to store data "0" by forming the first conductive via or the second conductive via, or the gate of the memory cell can be connected to a corresponding second ground to store data "1".

The encoding method of the present application can be specifically used for manufacturing and generating the aforementioned rom array structure 1, and the content of the encoding method and the content of the rom array structure 1 can be referred to each other, and more specific content can be referred to the aforementioned description about the rom array structure 1.

Embodiments of the present application also provide a computer storage medium, where the computer storage medium stores a computer program for electronic data exchange, the computer program enabling a computer to execute part or all of the steps of any one of the methods described in the above method embodiments, and the computer includes an electronic device.

Embodiments of the present application also provide a computer program product comprising a non-transitory computer readable storage medium storing a computer program operable to cause a computer to perform some or all of the steps of any of the methods as described in the above method embodiments. The computer program product may be a software installation package, the computer comprising an electronic device.

It should be noted that, for simplicity of description, the above-mentioned method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present application is not limited by the order of acts described, as some steps may occur in other orders or concurrently depending on the application. Further, those skilled in the art should also appreciate that the embodiments described in the specification are preferred embodiments and that the acts and modules referred to are not necessarily required in this application.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus may be implemented in other manners. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, the above-described division of the units is only one type of division of logical functions, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of some interfaces, devices or units, and may be an electric or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The integrated unit may be stored in a computer readable memory if it is implemented in the form of a software functional unit and sold or used as a stand-alone product. Based on such understanding, the technical solution of the present application may be substantially implemented or a part of or all or part of the technical solution contributing to the prior art may be embodied in the form of a software product stored in a memory, and including several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the above-mentioned method of the embodiments of the present application. And the aforementioned memory comprises: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.

Those skilled in the art will appreciate that all or part of the steps in the methods of the above embodiments may be implemented by associated hardware instructed by a program, which may be stored in a computer-readable memory, which may include: flash Memory disks, Read-Only memories (ROMs), Random Access Memories (RAMs), magnetic or optical disks, and the like.

The foregoing detailed description of the embodiments of the present application has been presented to illustrate the principles and implementations of the present application, and the above description of the embodiments is only provided to help understand the method and the core concept of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims (11)

1. A read only memory array structure, comprising:

m × n memory cells arranged in a matrix, each memory cell including a gate, a source and a drain, wherein m and n are natural numbers greater than or equal to 1;

m word lines corresponding to the m rows of memory cells one to one;

the n bit lines correspond to the n columns of storage units one by one, and each bit line is connected with the drain electrode of the storage unit in the corresponding column;

wherein, the source electrode of each memory cell is grounded; the gate of each memory cell is connected to a corresponding word line or grounded, depending on whether the data stored in the memory cell is "0" or "1".

2. The rom array architecture of claim 1, wherein each word line extends in a row direction across a corresponding row of memory cells;

each bit line extends through a corresponding column of memory cells in a column direction;

the read only memory array structure further comprises:

the n first ground wires extend through the corresponding column of storage units along the column direction and are connected with the sources of the storage units of the corresponding column to realize the grounding of the source of each storage unit;

and the n second ground lines extend through the corresponding column of memory cells along the column direction, wherein the gate of each memory cell is connected with the corresponding word line or connected with the corresponding second ground line to be grounded according to whether the data stored in each memory cell is '0' or '1'.

3. The rom array architecture of claim 2, wherein the gates of the memory cells are connected to the corresponding word line when a certain memory cell stores "0" data, and the gates of the memory cells are connected to the corresponding second ground when a certain memory cell stores "1" data.

4. The ROM array structure of claim 3, wherein the gates of the memory cells are connected to the corresponding word lines through the formed first conductive vias, and the gates of the memory cells are connected to the corresponding second ground lines through the formed second conductive vias.

5. The ROM array structure of claim 4, further comprising n word line connectors, each word line connector also extending along a row direction through a corresponding column of memory cells, and the n word line connectors being parallel to the n second ground and alternately disposed on the same layer, wherein each memory cell further comprises a gate connection line connected to the gate of the memory cell, the n word line connectors and the n second ground being disposed on the side of the memory cell where the gate connection line is disposed, and the m word lines being disposed on the side of the n word line connectors away from the memory cell; when data stored in a certain memory cell is '0', a first conductive sub-through hole is formed in a corresponding word line, and a second conductive sub-through hole is formed in a position, which is intersected with the gate connecting line, on a corresponding word line connecting bar, and the second conductive sub-through hole is connected with the first conductive sub-through hole to form the first conductive through hole, so that the word line is connected with the gate connecting line through the first conductive sub-through hole and the second conductive sub-through hole, and the gate of the memory cell is connected with the corresponding word line; when the data stored in a certain memory cell is "1", the second conductive through hole is formed in the position, which is crossed with the gate connecting line, on the corresponding second ground line, so that the second ground line is connected with the gate connecting line, and the gate of the memory cell is connected with the corresponding second ground line.

6. The ROM array structure of claim 5, wherein each of the word lines, the second ground, and the word line connectors is a conductive line wrapped with an insulating material, the gate connection lines are bare conductive lines, the word lines are electrically connected through the first conductive sub-vias when the word lines are provided with the first conductive sub-vias, the word line connectors are electrically connected through the second conductive sub-vias when the word line connectors are provided with the second conductive sub-vias, and the second ground is electrically connected through the second conductive sub-vias when the second ground is provided with the second conductive sub-vias.

7. The ROM array structure of claim 5, the gate connecting lines extending in a row direction, the ROM array structure further comprising a gate break layer extending in a column direction for separating the gate connecting lines of different memory cells.

8. The ROM array structure of any one of claims 1-7, wherein the sources of two adjacent memory cells are shared and/or the drains of two adjacent memory cells are shared among the memory cells in the same column.

9. A chip comprising a rom array structure according to any of claims 1-8.

10. An electronic device, characterized in that the electronic device comprises a chip according to claim 9.

11. A method of encoding, comprising:

determining data to be stored in each storage unit;

according to whether the data stored in each memory cell is '0' or '1', the gate of each memory cell is controlled to be connected with the corresponding word line or grounded.

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