CN114186396A - Simulation test method, device, equipment and system for chip - Google Patents
Simulation test method, device, equipment and system for chip Download PDFInfo
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Abstract
The embodiment of the application provides a simulation test method, device, equipment and system of a chip. The simulation test method of the chip comprises the following steps: simulating a first part of a chip running design program by using a hardware simulation system, and sampling at least once to obtain at least one sampling data; loading at least one sampled data into the software simulation system; and the software simulation system simulation chip continues to run part of or all the rest programs of the design program based on the at least one sampling data so as to carry out simulation test on the running design program of the chip. According to the embodiment of the application, part of programs are executed in the hardware simulation system, and the software simulation system continues to execute the design programs on the basis of the collected data, so that all processes of the design programs do not need to be really executed, the hardware simulation system and the software simulation system can be combined to realize efficient analysis and debugging, and good guidance is provided for chip design.
Description
Technical Field
The present application relates to the technical field of chip simulation testing, and in particular, to a method, an apparatus, a device and a system for chip simulation testing.
Background
In the field of chip design, for example, in the field of processors, program patterns with the most typical loads in different scenarios are generally extracted, and then a better evaluation can be performed on the performance of a program run by a processor through a simulation test.
At present, the process of simulating a chip running program by a hardware simulation system is generally adopted, but the problems of poor test accuracy or lack of data details of intermediate links due to only test results exist, and the like, so that good chip design guidance cannot be provided.
Disclosure of Invention
The application provides a simulation test method, device, equipment and system of a chip aiming at the defects of the existing mode, and is used for solving the technical problems that the test accuracy is poor or only test results are obtained and data details of intermediate links are lacked in the prior art.
In a first aspect, an embodiment of the present application provides a simulation test method for a chip, including:
simulating a first part of a chip running design program by using a hardware simulation system, and sampling at least once to obtain at least one sampling data; the sampling data is information representing the running state of a hardware simulation system running design program;
loading at least one sampled data into the software simulation system;
and the software simulation system simulation chip continues to run part of or all the rest programs of the design program based on the at least one sampling data so as to carry out simulation test on the running design program of the chip.
In one possible implementation, the software simulation system simulation chip continues to run a part of or all of the remaining programs of the design program based on the at least one sampling data, and the method includes:
the software simulation system determines sampling positions corresponding to the sampling data based on the execution information of the sampling data; the sampling data comprises execution information and intermediate result information, and the sampling position is the position of the corresponding sampling moment in the design program;
determining a sampling position from the sampling positions corresponding to the sampling data as an initial position for running a design program;
and according to the intermediate result information of the sampling data corresponding to the determined sampling position, continuing to run part of or all of the rest programs of the design program from the initial position of running the design program.
In one possible implementation, the simulating a first part of the chip running design program by using the hardware simulation system includes:
selecting a part in a design program as a first part;
determining a sampling position from the sampling positions corresponding to the sampling data as a starting position for running a design program, comprising:
determining the sampling sequence of each sampling data according to the sampling position corresponding to each sampling data;
and taking the sampling position corresponding to the acquired data acquired last as the initial position of the running design program.
In one possible implementation, the simulating a first part of the chip running design program by using the hardware simulation system includes:
if the simulation chip of the hardware simulation system runs the design program and has a fault, taking the part of the hardware simulation system which runs the design program as a first part;
determining a sampling position from the sampling positions corresponding to the sampling data as a starting position for running a design program, comprising:
determining the sampling sequence of each sampling data according to the sampling position corresponding to each sampling data;
and taking the sampling position corresponding to the Nth sampling data before the last acquired sampling data as the initial position of the running design program, wherein N is a positive integer greater than or equal to 1.
In one possible implementation, the at least one sampling is performed, including:
periodically sampling at least one time according to a design time; alternatively, the first and second electrodes may be,
sampling at least once according to the design sampling position information; the design sampling position information is information for triggering sampling in a design program.
In one possible implementation manner, the operating a first part of a design program by using a hardware simulation system simulation chip, and performing at least one sampling to obtain at least one sampling data includes:
in the process that the simulation chip of the hardware simulation system runs the first part of the design program, the information of the running state of the running design program of the hardware simulation system is stored in each first storage module of the first storage unit in real time; the first storage unit comprises at least one first storage module; when sampling is carried out each time, acquiring real-time running state information of the design program from each first storage module as sampling data;
the software simulation system simulation chip continues to run part of or all of the rest programs of the design program based on at least one piece of sampling data, and the method comprises the following steps:
correspondingly storing each sampling data into a corresponding second storage module according to the corresponding relation between each first storage module of the first storage unit and each second storage module of a second storage unit of the software simulation system; the second storage unit comprises at least one second storage module;
the sampling data is obtained from the second storage module while the design program is running.
In a second aspect, an embodiment of the present application provides a simulation test method for a chip, including:
acquiring at least one sampling data; at least one sampling data is obtained by adopting a hardware simulation system simulation chip to run a first part of a design program and performing at least one sampling, wherein the sampling data is information representing the running state of the hardware simulation system running the design program;
and the simulation chip continues to run part of or all the rest programs of the design program based on the at least one sampling data so as to perform simulation test on the chip running design program.
In one possible implementation, the simulation chip continues to run a part of or all of the remaining programs of the design program based on the at least one sampling data, including:
determining a sampling position corresponding to each sampling data based on the execution information of each sampling data; the sampling data comprises execution information and intermediate result information, and the sampling position is the position of the corresponding sampling moment in the design program;
determining a sampling position from the sampling positions corresponding to the sampling data as an initial position for running a design program;
and according to the intermediate result information of the sampling data corresponding to the determined sampling position, continuing to run part of or all of the rest programs of the design program from the initial position of running the design program.
In one possible implementation manner, determining a sampling position from the sampling positions corresponding to the sampling data as a starting position for running the design program includes:
determining the sampling sequence of each sampling data according to the sampling position corresponding to each sampling data; taking the sampling position corresponding to the last acquired acquisition data as the initial position of the running design program;
or determining the sampling sequence of each sampling data according to the sampling position corresponding to each sampling data; and taking the sampling position corresponding to the Nth sampling data before the last acquired sampling data as the initial position of the running design program, wherein N is a positive integer greater than or equal to 1.
In a third aspect, an embodiment of the present application provides a simulation test apparatus for a chip, including:
an acquisition module for acquiring at least one sample data; at least one sampling data is obtained by adopting a hardware simulation system simulation chip to run a first part of a design program and performing at least one sampling, wherein the sampling data is information representing the running state of the hardware simulation system running the design program;
and the simulation test module is used for simulating the chip to continuously run part of or all the rest programs of the design program based on the at least one sampling data so as to carry out simulation test on the chip running design program.
In a fourth aspect, an embodiment of the present application provides a simulation test apparatus for a chip, including: a memory, a processor and a computer program stored on the memory, the processor executing the computer program to implement the steps of the simulation test method of the chip of the second aspect.
In a fifth aspect, an embodiment of the present application provides a simulation test system for a chip, including:
the hardware simulation system is used for sampling at least once in the process of simulating the first part of the chip running design program to obtain at least one sampling data; the sampling data is information representing the running state of a hardware simulation system running design program;
and the software simulation system is used for acquiring at least one piece of sampling data, and the simulation chip continues to run part of or all of the rest programs of the design program based on the at least one piece of sampling data so as to perform simulation test on the running design program of the chip.
In a sixth aspect, the present application provides a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the steps of the simulation test method for a chip of the second aspect.
The beneficial technical effects brought by the technical scheme provided by the embodiment of the application comprise:
the simulation test method of the chip comprises the steps of firstly simulating a first part of a chip running design program by a hardware simulation system, carrying out at least one sampling in the process of running the design program by the hardware simulation system to obtain sampling data, and continuously running part of residual programs or all residual programs of the design program by the software simulation system simulation chip based on the at least one sampling data to realize the simulation test of the chip running design program. According to the embodiment of the application, part of programs are executed in the hardware simulation system, the software simulation system continues to execute the design program on the basis of the collected data, and the whole process of the design program does not need to be executed really; the software simulation system runs the design program, so that accurate simulation can be realized, the test accuracy is ensured, the data details of the intermediate link can be stored and analyzed, and the hardware simulation system and the software simulation system are combined to realize efficient analysis and debugging, thereby providing good guidance for chip design.
Additional aspects and advantages of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the present application.
Drawings
The foregoing and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
fig. 1 is a schematic structural diagram of a simulation test system of a chip according to an embodiment of the present disclosure;
fig. 2 is a flowchart of a simulation testing method for a chip according to an embodiment of the present disclosure;
fig. 3 is a flowchart of another simulation testing method for a chip according to an embodiment of the present disclosure;
fig. 4 is a flowchart of a simulation testing method for a chip according to an embodiment of the present disclosure;
fig. 5 is a flowchart of a simulation testing method for a chip according to an embodiment of the present disclosure;
fig. 6 is a flowchart of a simulation testing method for a chip according to an embodiment of the present disclosure;
fig. 7 is a schematic frame diagram of a simulation testing apparatus for a chip according to an embodiment of the present disclosure;
fig. 8 is a schematic frame diagram of a simulation test apparatus for a chip according to an embodiment of the present disclosure.
Detailed Description
Reference will now be made in detail to the present application, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar parts or parts having the same or similar functions throughout. In addition, if a detailed description of the known art is not necessary for illustrating the features of the present application, it is omitted. The embodiments described below with reference to the drawings are exemplary only for the purpose of explaining the present application and are not to be construed as limiting the present application.
It will be understood by those within the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. Further, "connected" or "coupled" as used herein may include wirelessly connected or wirelessly coupled. As used herein, the term "and/or" includes all or any element and all combinations of one or more of the associated listed items.
The inventor of the present application has studied and found that, in the field of chip design, a large part of work is understanding and analyzing the mode of the running program, and it is difficult to have a design or architecture that can have an optimal running effect for all programs. However, the actual running program is complicated and varied, and it is impossible to complete the task by trying to traverse all possible scenes. Therefore, a standard program test set is generated, and based on experience accumulation in the past decades, the test set extracts the program mode with the most typical load in different scenes, so that a better evaluation on the performance of the processor can be realized under the limited test set.
However, for the software simulation system, the most typical loaded program is generally a very large-scale standard program test set, which is too large and takes too long to run, so the software simulation system is generally not selected to perform the simulation test of the chip running program.
At present, the test of the test set of the super-large scale standard program is mainly focused on a model or a hardware accelerator. However, both of them have more or less problems, the abstraction level of the model is high, some execution details can be ignored, and accuracy problems are caused, the hardware accelerator can accurately obtain score evaluation, but only results are obtained, and data details of intermediate links are lacked, so that a lot of good design guidance cannot be provided.
The application provides a simulation test method, device, equipment and system of a chip, and aims to solve the technical problems in the prior art.
The following describes the technical solutions of the present application and how to solve the above technical problems with specific embodiments.
An embodiment of the present application provides a simulation test system of a chip, and referring to fig. 1, the simulation test system 100 of the chip includes: a hardware simulation system 110 and a software simulation system 120.
The hardware simulation system 110 is configured to perform at least one sampling during a process of simulating a first part of a chip running design program to obtain at least one sampling data; the sampling data is information representing an operation state in which the hardware simulation system 110 operates the design program.
The software simulation system 120 is configured to obtain at least one sampling data, and the simulation chip continues to run a part of or all of the remaining programs of the design program based on the at least one sampling data, so as to perform a simulation test on the chip running design program.
The simulation test system 100 of the chip of the embodiment of the application executes the first part of the design program in the hardware simulation system 110, and the software simulation system 120 continues to execute the design program on the basis of the collected data without really executing all the processes of the design program; by running the design program through the software simulation system 120, accurate simulation can be realized, the accuracy of testing is ensured, data details of intermediate links can be stored and analyzed, and efficient analysis and debugging can be realized by combining the hardware simulation system 110 and the software simulation system 120, so that good guidance is provided for chip design.
The simulation test system 100 of the chip according to the embodiment of the application uses the collected data of the simulation test of the first part of the design program as the stimulus, so that the software simulation system 120 continues the simulation test of the design program based on the collected data, the design program can be quickly reproduced in the software simulation system 120, and the test process of the software simulation system 120 is accelerated.
The embodiment of the application combines the hardware simulation system 110 and the software simulation system 120, has dual functions of performance evaluation and pipeline detail optimization, and overcomes the problem that the hardware acceleration mode of the existing hardware simulation system 110 is too rough. Meanwhile, the software simulation system 120 can accurately check the pipeline details of the acquired data in the later time period, so that the fault where the bottleneck is located or possibly exists can be quickly found, and the design verification personnel are friendly.
Alternatively, as shown in FIG. 1, the hardware simulation system 110 and the software simulation system 120 are electrically connected, and the sampled data may be directly transmitted to the software simulation system 120. Alternatively, the sampled data may be loaded from the hardware simulation system 110 into the software simulation system 120 through an external storage device.
Alternatively, the sample data is information of an operation state in which the hardware simulation system 110 operates the design program, each sample data is a result of operating the design program in real time, and the software simulation system 120 may continue to operate a part of the remaining programs or all of the remaining programs of the design program based on a result of operating the first part of the design program without completely repeating the operation of the part of the hardware simulation system 110 that has been operated.
Alternatively, the sampled data is data generated by a snapshot.
Alternatively, the hardware simulation system 110 and the software simulation system 120 may be two relatively independent environments, with the sampled data as the key intermediate data. For example: the engineer a obtains the sampled data in the hardware simulation system 110 in the laboratory, and the engineer B performs simulation, waveform analysis, vulnerability fault location, and the like using the sampled data in the office.
Alternatively, the hardware emulation system 110 can be a hardware accelerator or other hardware for simulating a chip running a program.
Optionally, the design program is a program to be tested according to needs, the chip may be a chip applied in the processor, and since the processor has many programs to run in actual application, some mainstream program modes, such as a standard program test set, are selected when the processor is tested.
Optionally, the hardware simulation system 110 includes a sampling unit, configured to periodically perform at least one sampling according to a design time; or sampling at least once according to the design sampling position information; the design sampling position information is information for triggering sampling in a design program.
Optionally, the hardware simulation system 110 further includes a first storage unit, where the first storage unit includes at least one first storage module, and the first storage module is used to store the sampling data, and the first storage module may be a general register set, a buffer cache, an internal register, and an internal Static Random-Access Memory (SRAM), and the internal SRAM may be, for example: according to the table of the branch predictor, sampling contents can be designed in advance according to needs, sampling data of different degrees can restore an original scene to different degrees, and the sampling data can be correspondingly stored in the corresponding first storage module according to the preset design.
Alternatively, the hardware simulation system 110 and the software simulation system 120 may both simulate the chip to run the design program, for example, parameter setting sets may be formed by setting parameters, and the hardware units, the interrelations, the basic operation flow, and the like inside the chip may be simulated by using the parameter setting sets.
Alternatively, the software simulation system 120 may employ an EDA simulation system. The software simulation system 120 can obtain the information of the chip simulation test in the process of running the design program by knowing the data of all chip circuit states through waveform analysis.
Specifically, details regarding how the software simulation system 120 continues to run a part of the remaining programs or all of the remaining programs of the design program based on the sampled data are described in the simulation test method applied to the chip of the software simulation system 120.
Based on the same inventive concept, the embodiment of the present application provides a simulation test method for a chip, which is applied to a simulation test system 100 for a chip, and as shown in fig. 2, the simulation test method for a chip includes: step S201 to step S203.
S201, simulating a first part of a chip operation design program by using a hardware simulation system 110, and sampling at least once to obtain at least one sampling data; the sampling data is information representing an operation state in which the hardware simulation system 110 operates the design program.
In some embodiments, the performing at least one sampling in step S201 includes:
at least one sampling is performed periodically according to the design time. Alternatively, the first and second electrodes may be,
sampling at least once according to the design sampling position information; the design sampling position information is information for triggering sampling in a design program.
Optionally, at least one sampling is periodically performed according to the design time, one sampling may be performed at every interval of 1s, or sampling may be performed at different intervals, and the periodic sampling time is designed according to the actual situation.
Alternatively, at least one sampling is performed according to the design sampling position information, and data sampling can be performed according to a specific point specified by a design program. For example, a trigger instruction may be added to a corresponding position of a key segment that needs to be sampled in an original design program as design sampling position information, and when the trigger instruction is executed, the sampling is triggered.
S202, loading at least one sampling data to the software simulation system 120.
Optionally, at least one sampling data may be loaded to the software simulation system 120 through an external storage device, or the hardware simulation system 110 may store the collected data and then send the collected data to the software simulation system 120.
And S203, the software simulation system 120 simulates the chip to continue to run part of or all the rest programs of the design program based on the at least one sampling data so as to perform simulation test on the running design program of the chip.
In some embodiments, in step S203, the software simulation system 120 simulates the chip to continue to run part or all of the remaining programs of the design program based on the at least one sampling data, including:
the software simulation system 120 determines a sampling position corresponding to each sampling data based on the execution information of each sampling data; the sampling data comprises execution information and intermediate result information, and the sampling position is the position of the corresponding sampling time in the design program.
And determining a sampling position from the sampling positions corresponding to the sampling data as a starting position for running the design program.
And according to the intermediate result information of the sampling data corresponding to the determined sampling position, continuing to run part of or all of the rest programs of the design program from the initial position of running the design program.
Alternatively, the remaining programs of the design program are programs after the start position (i.e., the determined sampling position) of the running design program.
Alternatively, the intermediate result information is an execution result of executing the design program, and the program following the execution of the design program may continue to run toward the program following the design program based on the previous intermediate result information.
Alternatively, one sampling position is determined from the sampling positions corresponding to the respective sampling data, and may be the sampling position of any one sampling data according to the actual situation.
Alternatively, the software simulation system 120 executes part or all of the remaining programs for continuing to run the design program, and may be a program for executing part or all of the sampling positions of the entire design program corresponding to the determined sampling data.
In some embodiments, simulating a first part of a chip running design program by using the hardware simulation system 110, and performing at least one sampling to obtain at least one sampling data includes:
in the process that the hardware simulation system 110 simulates a chip to run a first part of a design program, storing information of the running state of the hardware simulation system 110 running the design program into each first storage module of a first storage unit in real time; the first storage unit comprises at least one first storage module;
and acquiring the running state information of the real-time design program from each first storage module as sampling data each time sampling is performed.
In this embodiment, the software simulation system 120 simulates a chip to continue running a part of or all of the remaining programs of the design program based on at least one sampling data, and includes:
correspondingly storing each sampling data into the corresponding second storage module according to the corresponding relationship between each first storage module of the first storage unit and each second storage module of the second storage unit of the software simulation system 120; the second storage unit comprises at least one second storage module;
the sampling data is obtained from the second storage module while the design program is running.
Optionally, a first storage module of a first storage unit of the hardware simulation system 110 is configured to store the sampled data, and the first storage module may be a general register set, a buffer cache, an internal register, and an internal Static Random-Access Memory (SRAM), where the SRAM is, for example: according to the table of the branch predictor, sampling contents can be designed in advance according to needs, sampling data of different degrees can restore an original scene to different degrees, and the sampling data can be correspondingly stored in the corresponding first storage module according to the preset design.
Optionally, the software simulation system 120 includes a second storage module corresponding to the first storage module of the first storage unit, and may store the acquired data acquired from the first storage module to the second storage module correspondingly, so as to implement resetting of the acquired data, and be used for calling the acquired data when the program is subsequently continuously run.
In some embodiments, simulating a first portion of a chip running design program with the hardware simulation system 110 includes:
a portion of the design program is selected as the first portion.
In this embodiment, the determining a sampling position from the sampling positions corresponding to the sampling data as a starting position for running the design program includes:
determining the sampling sequence of each sampling data according to the sampling position corresponding to each sampling data;
and taking the sampling position corresponding to the acquired data acquired last as the initial position of the running design program.
Alternatively, as an example, referring to fig. 3, a simulation test method of a chip is provided, which includes the following steps S301 to S307.
S301, selecting a part in the design program as a first part.
Alternatively, the design program may be divided into two parts, the first part being executed by the hardware simulation system 110 and the latter part being executed by the software simulation system 120. Alternatively, a part may be taken from the middle as the first part, the software simulation system 120 executes the program after the first part based on the sampled data of the first part, and the program before the first part may be normally executed by the software simulation system 120.
Alternatively, as an example, the initialization part in the design program may be the first part, which is the part not concerned, and the hardware simulation system 110 performs the test, and the part needing to be concerned after the initialization is performed, and the software simulation system 120 continues the simulation test.
S302, simulating a first part of a chip operation design program by using the hardware simulation system 110, and sampling at least once to obtain at least one sampling data; the sampling data is information representing an operation state in which the hardware simulation system 110 operates the design program.
Optionally, the content in step S302 is consistent with the content principle in step S201, and is not described again.
S303, loading the at least one sampling data to the software simulation system 120.
Optionally, the content in step S303 is consistent with the content principle in step S202, and is not described again.
S304, the software simulation system 120 determines sampling positions corresponding to the sampling data based on the execution information of the sampling data; the sampling data comprises execution information and intermediate result information, and the sampling position is the position of the corresponding sampling time in the design program.
Alternatively, the position of the design program can be found through the execution information of each sampling data, and the sampling position is relocated to facilitate the execution of the design program. The intermediate result information of each sample data can run the result of the design program to the sampling position, and the intermediate result information of the following sample data is the result obtained on the basis of the intermediate result information of the previous sample data, so that for each sample data, the software simulation system 120 can continue to execute the following program at the corresponding sampling position based on the intermediate result information.
And S305, determining the sampling sequence of each sampling data according to the sampling position corresponding to each sampling data.
Optionally, the sampling sequence corresponds to a sequence of the design program running and a sequence of the sampling time.
And S306, taking the sampling position corresponding to the acquired data acquired last as the initial position of the running design program.
Alternatively, if the first part is an initialization part, the last collected data may correspond to an initialization end, and the position of the initialization end is used as the starting position for running the design program, and the software simulation system 120 continues to run part of or all of the rest of the design program.
And S307, continuing to run part or all of the rest programs of the design program from the initial position of the running design program according to the intermediate result information of the sampling data corresponding to the determined sampling position.
Optionally, the intermediate result information of the sampled data is brought to the starting position for running the design program, so that the software simulation system 120 can continue to run part of or all of the remaining programs of the design program based on the intermediate result information of the collected data.
Alternatively, if no failure occurs while continuing to run the design program, all remaining programs of the design program may be run.
The simulation test method of the chip in the embodiment of the application can be used for accurately realizing the key part in the design program in the software simulation system 120, and does not need to waste a large amount of time to execute the program of the part which is not concerned, thereby providing support for the software simulation system 120 to research and test the details of the design program.
In some embodiments, simulating a first portion of a chip running design program with the hardware simulation system 110 includes:
if the hardware simulation system 110 simulates that the chip runs the design program and has a fault, the part of the hardware simulation system 110 which runs the design program is taken as a first part;
and determining a sampling position from the sampling positions corresponding to the sampling data as the initial position for running the design program, wherein the sampling position comprises the following steps:
determining the sampling sequence of each sampling data according to the sampling position corresponding to each sampling data;
and taking the sampling position corresponding to the Nth sampling data before the last acquired sampling data as the initial position of the running design program, wherein N is a positive integer greater than or equal to 1.
Alternatively, as an example, referring to fig. 4, a simulation test method of a chip is provided, which includes the following steps S401 to S407.
S401, simulating a chip running design program by using a hardware simulation system 110, and sampling at least once to obtain at least one sampling data; and if the simulation chip running design program of the hardware simulation system 110 fails, stopping sampling.
Optionally, the simulating, by the hardware simulation system 110, a case where the chip running design program fails includes: when the hardware simulation system 110 simulates a chip to run a design program, the design program is automatically exited; or when the hardware simulation system 110 simulates a chip to run a design program, the hardware simulation system enters circulation to continuously and repeatedly run; or, when the hardware simulation system 110 simulates a chip to run a design program, the fault detection module of the hardware simulation system 110 detects that the running design program has a fault and sends a prompt message.
Optionally, the hardware simulation system 110 simulates the chip running design program to have a fault, which indicates that the chip running design program has a fault, but the hardware simulation system 110 cannot find and analyze the fault itself, so that the software simulation system 120 needs to simulate the chip running design program to find and analyze the fault at the fastest speed.
Alternatively, if the hardware simulation system 110 stops sampling, the hardware simulation system 110 exits from running the design program.
S402, loading at least one sampling data to the software simulation system 120.
Optionally, the content in step S402 is consistent with the content principle in steps S303 and S202, and is not described again.
S403, the software simulation system 120 determines sampling positions corresponding to the sampling data based on the execution information of the sampling data; the sampling data comprises execution information and intermediate result information, and the sampling position is the position of the corresponding sampling time in the design program.
Optionally, the content in step S403 is consistent with the content principle in step S304, and is not described again.
And S404, determining the sampling sequence of each sampling data according to the sampling position corresponding to each sampling data.
Optionally, the content in step S404 is consistent with the content principle in step S305, and is not described again.
S405, taking a sampling position corresponding to the Nth sampling data before the last acquired sampling data as an initial position for running a design program, wherein N is a positive integer greater than or equal to 1.
Optionally, the acquisition position of the acquired data of the last acquisition is located near the fault, and a sampling position corresponding to the 1 st, 2 nd or 3 rd acquired data before the acquired data of the last acquisition may be selected according to an actual situation as an initial position for running the design program.
And S406, continuing to run part of the rest programs of the design program from the initial position of the running design program according to the intermediate result information of the sampling data corresponding to the determined sampling position.
Optionally, the content in step S406 is consistent with the content principle in step S307, and is not described again.
Optionally, since the determined sampling location is before and near the fault, the fault can be found shortly after the software simulation system 120 continues to run part of the rest of the design program, so as to locate and waveform analyze the fault and find the cause of the bug.
The simulation test method of the chip in the embodiment of the application can be used for accurately checking the pipeline details of the acquired data in the later time period when other later imitations or simulations have faults, so that the bottleneck or the faults possibly existing can be quickly found, and the method is friendly to design and verification personnel.
Based on the same inventive concept, the embodiment of the present application provides a simulation test method for a chip, which is applied to a software simulation system 120, and as shown in fig. 5, the simulation test method for the chip includes: step S501 to step S502.
S501, acquiring at least one sampling data; at least one sampling data is obtained by simulating a first part of a chip running design program by using the hardware simulation system 110 and performing at least one sampling, and the sampling data is information representing the running state of the hardware simulation system 110 running the design program.
Optionally, the sampling data is collected by the hardware simulation system 110 of the chip.
And S502, the simulation chip continues to run part of or all the rest programs of the design program based on at least one piece of sampling data so as to carry out simulation test on the chip running design program.
In some embodiments, the simulation chip continues to run a part of or all of the remaining programs of the design program based on the at least one sampled data, including:
determining a sampling position corresponding to each sampling data based on the execution information of each sampling data; the sampling data comprises execution information and intermediate result information, and the sampling position is the position of the corresponding sampling moment in the design program;
determining a sampling position from the sampling positions corresponding to the sampling data as an initial position for running a design program;
and according to the intermediate result information of the sampling data corresponding to the determined sampling position, continuing to run part of or all of the rest programs of the design program from the initial position of running the design program.
In some embodiments, determining a sampling position from the sampling positions corresponding to the sampling data as a starting position for running the design program includes:
determining the sampling sequence of each sampling data according to the sampling position corresponding to each sampling data; taking the sampling position corresponding to the last acquired acquisition data as the initial position of the running design program;
or determining the sampling sequence of each sampling data according to the sampling position corresponding to each sampling data; and taking the sampling position corresponding to the Nth sampling data before the last acquired sampling data as the initial position of the running design program, wherein N is a positive integer greater than or equal to 1.
Optionally, as an example, referring to fig. 6, a simulation testing method for a chip is provided, which is applied to the software simulation system 120, and the simulation testing method for a chip includes the following steps S601 to S605.
S601, acquiring at least one sampling data; at least one sampling data is obtained by simulating a first part of a chip running design program by using the hardware simulation system 110 and performing at least one sampling, and the sampling data is information representing the running state of the hardware simulation system 110 running the design program.
Optionally, the software simulation system 120 obtains at least one sample data; at least one sampling data is obtained by simulating a first part of a chip running design program by using the hardware simulation system 110 and performing at least one sampling.
S602, determining sampling positions corresponding to the sampling data based on the execution information of the sampling data; the sampling data comprises execution information and intermediate result information, and the sampling position is the position of the corresponding sampling time in the design program.
Alternatively, the software simulation system 120 determines the sampling position corresponding to each sampling data based on the execution information of each sampling data.
And S603, determining the sampling sequence of each sampling data according to the sampling position corresponding to each sampling data.
Optionally, the software simulation system 120 determines a sampling sequence of each sampling data according to a sampling position corresponding to each sampling data.
S604, taking the sampling position corresponding to the acquired data as the initial position of the running design program; or determining the sampling sequence of each sampling data according to the sampling position corresponding to each sampling data; and taking the sampling position corresponding to the Nth sampling data before the last acquired sampling data as the initial position of the running design program, wherein N is a positive integer greater than or equal to 1.
Optionally, the software simulation system 120 takes the sampling position corresponding to the last acquired acquisition data as the starting position for running the design program; or determining the sampling sequence of each sampling data according to the sampling position corresponding to each sampling data; and taking the sampling position corresponding to the Nth sampling data before the last acquired sampling data as the initial position of the running design program, wherein N is a positive integer greater than or equal to 1.
And S605, according to the intermediate result information of the sampling data corresponding to the determined sampling position, continuing to operate part of or all the rest programs of the design program from the initial position of the operation design program.
Optionally, the software simulation system 120 continues to run a part of or all of the remaining programs of the design program from the starting position of running the design program according to the intermediate result information of the sampling data corresponding to the determined sampling position.
Optionally, the contents of the simulation testing method applied to the chip of the software simulation system 120 are the same as the contents of the software simulation system 120 in the simulation testing method applied to the chip of the simulation testing system 100, and are not described herein again.
Based on the same inventive concept, the present application provides a simulation test apparatus for a chip, as shown in fig. 7, the simulation test apparatus 700 for a chip includes: an acquisition module 710 and a simulation test module 720.
The obtaining module 710 is configured to obtain at least one sample data; at least one sampling data is obtained by simulating a first part of a chip running design program by using the hardware simulation system 110 and performing at least one sampling, and the sampling data is information representing the running state of the hardware simulation system 110 running the design program.
The simulation testing module 720 is used for simulating the chip to continue to run part of or all of the remaining programs of the design program based on the at least one sampling data, so as to perform simulation testing on the chip running design program.
Optionally, the simulation testing module 720 is configured to determine a sampling position corresponding to each sampling data based on the execution information of each sampling data; the sampling data comprises execution information and intermediate result information, and the sampling position is the position of the corresponding sampling moment in the design program; determining a sampling position from the sampling positions corresponding to the sampling data as an initial position for running a design program; and according to the intermediate result information of the sampling data corresponding to the determined sampling position, continuing to run part of or all of the rest programs of the design program from the initial position of running the design program.
Optionally, the simulation testing module 720 is further configured to determine a sampling sequence of each sampling data according to a sampling position corresponding to each sampling data; taking the sampling position corresponding to the last acquired acquisition data as the initial position of the running design program; or determining the sampling sequence of each sampling data according to the sampling position corresponding to each sampling data; and taking the sampling position corresponding to the Nth sampling data before the last acquired sampling data as the initial position of the running design program, wherein N is a positive integer greater than or equal to 1.
Optionally, the steps of the simulation testing apparatus 700 of the chip in the embodiment of the present application are the same as those of the simulation method of the chip in the software simulation system 120, and are not described herein again.
Based on the same inventive concept, the embodiment of the present application provides a simulation test device for a chip, including: the chip simulation test system comprises a memory, a processor and a computer program stored on the memory, wherein the processor executes the computer program to realize the steps of the chip simulation test method of the embodiment of the application.
In an alternative embodiment, the present application provides a simulation test apparatus for a chip, as shown in fig. 8, the simulation test apparatus 2000 for a chip shown in fig. 8 includes: a processor 2001 and a memory 2003. The processor 2001 and memory 2003 are communicatively coupled, such as via a bus 2002, among others.
The Processor 2001 may be a CPU (Central Processing Unit), general Processor, DSP (Digital Signal Processor), ASIC (Application Specific Integrated Circuit), FPGA (Field Programmable Gate Array) or other Programmable logic device, transistor logic device, hardware component, or any combination thereof. Which may implement or perform the various illustrative logical blocks, modules, and circuits described in connection with the disclosure. The processor 2001 may also be a combination of computing functions, e.g., comprising one or more microprocessors, DSPs and microprocessors, and the like.
The Memory 2003 may be a ROM (Read-Only Memory) or other type of static storage device that can store static information and instructions, a RAM (random access Memory) or other type of dynamic storage device that can store information and instructions, an EEPROM (Electrically Erasable Programmable Read Only Memory), a CD-ROM (Compact Disc Read-Only Memory) or other optical Disc storage, optical Disc storage (including Compact Disc, laser Disc, optical Disc, digital versatile Disc, blu-ray Disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer, but is not limited to these.
Optionally, the simulation test equipment 2000 of the chip may further include a transceiver 2004. The transceiver 2004 may be used for reception and transmission of signals. The transceiver 2004 may allow the simulation test device 2000 of the chip to communicate wirelessly or wiredly with other devices to exchange data. It should be noted that the number of the transceivers 2004 is not limited to one.
Optionally, the simulation test apparatus 2000 of the chip may further include an input unit 2005. The input unit 2005 may be used to receive input numeric, character, image and/or sound information, or to generate key signal inputs related to user settings and function control of the simulation test apparatus 2000 of the chip. The input unit 2005 may include, but is not limited to, one or more of a touch screen, a physical keyboard, function keys (such as volume control keys, switch keys, etc.), a trackball, a mouse, a joystick, a camera, a microphone, and the like.
Optionally, the simulation test apparatus 2000 of the chip may further include an output unit 2006. The output unit 2006 may be used to output or show information processed by the processor 2001. The output unit 2006 may include, but is not limited to, one or more of a display device, a speaker, a vibration device, and the like.
While FIG. 8 illustrates the simulation test equipment 2000 with a chip of various devices, it is to be understood that not all of the illustrated devices are required to be implemented or provided. More or fewer devices may alternatively be implemented or provided.
Optionally, the memory 2003 is used for storing application program code for performing the disclosed aspects, and is controlled in execution by the processor 2001. The processor 2001 is used for executing the application program codes stored in the memory 2003 to implement any one of the simulation test methods of the chip provided by the embodiments of the present application.
Based on the same inventive concept, embodiments of the present application provide a computer-readable storage medium, on which a computer program is stored, and the computer program, when executed by a processor, implements the steps of the simulation test method of the chip of the embodiments of the present application.
The computer readable storage medium includes, but is not limited to, any type of disk including floppy disks, hard disks, optical disks, CD-ROMs, and magneto-optical disks, ROMs, RAMs, EPROMs (Erasable Programmable Read-Only memories), EEPROMs, flash Memory, magnetic or optical cards. That is, a readable medium includes any medium that stores or transmits information in a form readable by a device (e.g., a computer).
By applying the embodiment of the application, at least the following beneficial effects can be realized:
(1) in the embodiment of the application, the hardware simulation system 110 executes the first part of the design program, and the software simulation system 120 continues to execute the design program on the basis of the collected data without really executing all processes of the design program; by running the design program through the software simulation system 120, accurate simulation can be realized, the accuracy of testing is ensured, data details of intermediate links can be stored and analyzed, and efficient analysis and debugging can be realized by combining the hardware simulation system 110 and the software simulation system 120, so that good guidance is provided for chip design.
(2) In the embodiment of the application, the collected data of the simulation test of the first part of the design program is used as the stimulus, so that the software simulation system 120 continues to perform the simulation test of the design program based on the collected data, the design program can be quickly reproduced in the software simulation system 120, and the test process of the software simulation system 120 is accelerated.
(3) The embodiment of the application combines the hardware simulation system 110 and the software simulation system 120, has dual functions of performance evaluation and pipeline detail optimization, and overcomes the problem that the hardware acceleration mode of the existing hardware simulation system 110 is too rough. Meanwhile, the software simulation system 120 can accurately check the pipeline details of the acquired data in the later time period, so that the fault where the bottleneck is located or possibly exists can be quickly found, and the design verification personnel are friendly.
(4) The embodiment of the application can accurately realize the key part in the design program in the software simulation system 120, and does not need to waste a large amount of time to execute the program of the part which is not concerned, thereby providing support for the software simulation system 120 to research and test the design program details.
(5) The embodiment of the application can be used for accurately checking the pipeline details of the acquired data in the later time period by the software simulation system 120 in the former simulation environment when other later simulations or hardware simulations have faults, so that the faults where bottlenecks are located or may exist can be quickly found, and design and verification personnel can conveniently perform simulation tests on chips.
Those of skill in the art will appreciate that the various operations, methods, steps in the processes, acts, or solutions discussed in this application can be interchanged, modified, combined, or eliminated. Further, other steps, measures, or schemes in various operations, methods, or flows that have been discussed in this application can be alternated, altered, rearranged, broken down, combined, or deleted. Further, steps, measures, schemes in the prior art having various operations, methods, procedures disclosed in the present application may also be alternated, modified, rearranged, decomposed, combined, or deleted.
The terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless otherwise specified.
In the description herein, particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.
It should be understood that, although the steps in the flowcharts of the figures are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and may be performed in other orders unless explicitly stated herein. Moreover, at least a portion of the steps in the flow chart of the figure may include multiple sub-steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, which are not necessarily performed in sequence, but may be performed alternately or alternately with other steps or at least a portion of the sub-steps or stages of other steps.
The foregoing is only a partial embodiment of the present application, and it should be noted that, for those skilled in the art, several modifications and decorations can be made without departing from the principle of the present application, and these modifications and decorations should also be regarded as the protection scope of the present application.
Claims (13)
1. A simulation test method of a chip is characterized by comprising the following steps:
simulating a first part of the chip running design program by using a hardware simulation system, and sampling at least once to obtain at least one sampling data; the sampling data is information representing the running state of the hardware simulation system running the design program;
loading the at least one sampled data into a software simulation system;
and the software simulation system simulates the chip to continue to run part of or all of the rest programs of the design program based on the at least one sampling data so as to carry out simulation test on the chip running the design program.
2. The method for simulation test of the chip according to claim 1, wherein the simulating of the chip by the software simulation system continuing to run a part of or all of the remaining programs of the design program based on the at least one sampling data comprises:
the software simulation system determines a sampling position corresponding to each sampling data based on the execution information of each sampling data; the sampling data comprises execution information and intermediate result information, and the sampling position is the position of the corresponding sampling time in the design program;
determining a sampling position from the sampling positions corresponding to the sampling data as an initial position for running a design program;
and according to the intermediate result information of the sampling data corresponding to the determined sampling position, continuing to run part of or all of the rest programs of the design program from the initial position of the running design program.
3. The method for simulation test of the chip according to claim 2, wherein the simulating the first part of the chip running design program by the hardware simulation system comprises: selecting a part of the design program as a first part;
the determining a sampling position from the sampling positions corresponding to the sampling data as the initial position for running the design program includes:
determining the sampling sequence of each sampling data according to the sampling position corresponding to each sampling data;
and taking the sampling position corresponding to the acquired data acquired last as the initial position of the running design program.
4. The method for simulation test of the chip according to claim 2, wherein the simulating the first part of the chip running design program by the hardware simulation system comprises: if the hardware simulation system simulates the chip to run the design program and has a fault, taking the part of the hardware simulation system which runs the design program as a first part;
the determining a sampling position from the sampling positions corresponding to the sampling data as the initial position for running the design program includes:
determining the sampling sequence of each sampling data according to the sampling position corresponding to each sampling data;
and taking the sampling position corresponding to the Nth sampling data before the last acquired sampling data as the initial position of the running design program, wherein N is a positive integer greater than or equal to 1.
5. The method for simulation test of a chip according to claim 1, wherein said performing at least one sampling comprises:
periodically sampling at least one time according to a design time; alternatively, the first and second electrodes may be,
sampling at least once according to the design sampling position information; the design sampling position information is information used for triggering sampling in the design program.
6. The method for simulation test of a chip according to claim 1, wherein the simulating a first part of the chip running design program by using a hardware simulation system and performing at least one sampling to obtain at least one sampling data comprises: in the process that the hardware simulation system simulates the chip to run the first part of the design program, the information of the running state of the hardware simulation system running the design program is stored in each first storage module of a first storage unit in real time; the first storage unit comprises at least one first storage module; when sampling is carried out each time, acquiring real-time running state information of the design program from each first storage module as sampling data;
the software simulation system simulates the chip to continue to run part of or all of the rest programs of the design program based on the at least one sampling data, and comprises the following steps:
correspondingly storing each sampling data into a corresponding second storage module according to the corresponding relation between each first storage module of the first storage unit and each second storage module of a second storage unit of the software simulation system; the second storage unit comprises at least one second storage module;
and acquiring the sampling data from the second storage module when a design program is operated.
7. A simulation test method of a chip is characterized by comprising the following steps:
acquiring at least one sampling data; the at least one sampling data is obtained by simulating a first part of the chip running design program by a hardware simulation system and sampling at least once, and the sampling data is information representing the running state of the hardware simulation system running the design program;
and simulating the chip to continue to run part of or all of the rest programs of the design program based on the at least one sampling data so as to carry out simulation test on the chip running the design program.
8. The method for simulation test of a chip according to claim 7, wherein the simulating the chip to continue running a part of or all of the remaining programs of the design program based on the at least one sampled data comprises:
determining a sampling position corresponding to each of the sampling data based on execution information of each of the sampling data; the sampling data comprises execution information and intermediate result information, and the sampling position is the position of the corresponding sampling time in the design program;
determining a sampling position from the sampling positions corresponding to the sampling data as an initial position for running a design program;
and according to the intermediate result information of the sampling data corresponding to the determined sampling position, continuing to run part of or all of the rest programs of the design program from the initial position of the running design program.
9. The method for simulation test of a chip according to claim 8, wherein the determining a sampling position from the sampling positions corresponding to each of the sampling data as a starting position for running a design program comprises:
determining the sampling sequence of each sampling data according to the sampling position corresponding to each sampling data; taking the sampling position corresponding to the last acquired acquisition data as the initial position of the running design program;
or determining the sampling sequence of each sampling data according to the sampling position corresponding to each sampling data; and taking the sampling position corresponding to the Nth sampling data before the last acquired sampling data as the initial position of the running design program, wherein N is a positive integer greater than or equal to 1.
10. A simulation test device of a chip is characterized by comprising:
an acquisition module for acquiring at least one sample data; the at least one sampling data is obtained by simulating a first part of the chip running design program by a hardware simulation system and sampling at least once, and the sampling data is information representing the running state of the hardware simulation system running the design program;
and the simulation testing module is used for simulating the chip to continuously run part of or all of the rest programs of the design program based on the at least one sampling data so as to carry out simulation testing on the chip running the design program.
11. An apparatus for simulation test of a chip, comprising: memory, processor and computer program stored on the memory, characterized in that the processor executes the computer program to implement the steps of the simulation test method of a chip according to any of claims 7-9.
12. A simulation test system for a chip, comprising:
the hardware simulation system is used for sampling at least once in the process of simulating the chip to run the first part of the design program to obtain at least one sampling data; the sampling data is information representing the running state of the hardware simulation system running the design program;
and the software simulation system is used for acquiring the at least one sampling data, simulating the chip to continuously run a part of residual programs or all residual programs of the design program based on the at least one sampling data, and carrying out simulation test on the chip running the design program.
13. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of the simulation test method of a chip according to any one of claims 7 to 9.
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