CN114185572A - Data flashing method, device, equipment and storage medium - Google Patents
Data flashing method, device, equipment and storage medium Download PDFInfo
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Abstract
The application discloses a method, a device, equipment and a storage medium for flashing data, wherein the method comprises the following steps: the upper computer analyzes the compiled program file to obtain code segment data, data segment data and data size and address range of the code segments and the data segments, and sends the code segment data, the data segment data and the data size and address range of the code segments and the data segments to the lower computer; and the lower computer performs partition flash according to the code segment data, the data segment data, and the data size and address range of the code segment and the data segment. According to the data flashing method provided by the embodiment of the application, the sizes of the code area and the data area can be automatically adjusted, the lower computer flashing program does not need to be frequently upgraded, the later spare part does not perform flashing, and the effectiveness of flashing is greatly improved.
Description
Technical Field
The present invention relates to the field of data processing technologies, and in particular, to a method, an apparatus, a device, and a storage medium for data flashing.
Background
When a program is updated to a target device, the process of updating the program is a data flashing process, the data flashing speed is usually limited by a baud rate, a load rate and the throughput of a gateway for data interaction, and the flashing process is long.
Along with the iterative development of programs, the complexity of functions can be continuously increased, if a certain flash memory partition is not enough, the flash memory partition can be divided again, the whole partition framework needs to be adjusted, the upper computer and the lower computer upgrade the software again, the problem that the software versions are not compatible from top to bottom is caused, and meanwhile, the whole-area flash writing consumes long time.
Therefore, how to improve the efficiency of data flashing is an urgent technical problem to be solved by those skilled in the art.
Disclosure of Invention
The embodiment of the application provides a data flashing method, a data flashing device, data flashing equipment and a storage medium. The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview and is intended to neither identify key/critical elements nor delineate the scope of such embodiments. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is presented later.
In a first aspect, an embodiment of the present disclosure provides a data flashing method, including:
the upper computer analyzes the compiled program file to obtain code segment data, data segment data and data size and address range of the code segments and the data segments, and sends the code segment data, the data segment data and the data size and address range of the code segments and the data segments to the lower computer;
and the lower computer performs partition flash according to the code segment data, the data segment data, and the data size and address range of the code segment and the data segment.
In an optional embodiment, before the upper computer parses the compiled program file, the method further includes:
acquiring a program to be flashed compiled according to a preset rule;
and carrying out dynamic self-adaptive partitioning according to the program to be flashed to generate a program file.
In an optional embodiment, the dynamic adaptive partitioning according to the program to be flashed includes:
obtaining code segment data and data segment data according to the segment identification in the program to be flashed;
sequentially storing the code segment data and the data segment data into a Block partition according to the data size and the Block partition sequence;
the starting positions of the code segment partition and the data segment partition contain starting marks, and the ending positions of the code segment partition and the data segment partition contain ending marks.
In an optional embodiment, further comprising:
when the size of the code segment data does not meet one or more Block partitions, filling the rest parts of the Block partitions with preset values;
when the size of the data segment data does not satisfy one or more Block partitions, the rest of the Block partitions are filled with preset values.
In an optional embodiment, further comprising:
when the program is upgraded, if the data of the code segment is increased, the code segment Block partitions are sequentially expanded backwards, and if the data of the data segment is increased, the data segment Block partitions are sequentially expanded backwards.
In an optional embodiment, the upper computer parses the compiled program file to obtain the code segment data, the data segment data, and the data size and address range of the code segment and the data segment, and sends the code segment data, the data segment data, and the data size and address range of the code segment and the data segment to the lower computer, including:
analyzing the program file by analysis function software in the upper computer to obtain code segment data, data segment data, and data size and address range of the code segment and the data segment;
the flashing function software in the upper computer generates an executable code segment flashing file and a data segment flashing file according to the code segment data, the data segment data and the data size and address range of the code segment and the data segment, analyzes the code segment flashing file and the data segment flashing file, and obtains the executable code segment data, the data segment data and the data size and address range of the code segment and the data segment;
the upper computer and the lower computer perform safety check;
and if the data passes the safety check, sending the executable code segment data, the executable data segment data, and the data size and the address range of the code segment and the data segment to the lower computer.
In an optional embodiment, after the lower computer performs partition flashing according to the code segment data, the data segment data, and the data size and address range of the code segment and the data segment, the lower computer further includes:
the upper computer and the lower computer carry out integrity check on the data in the preset address range;
and if the integrity check is passed, the flash is completed.
In a second aspect, an embodiment of the present disclosure provides an apparatus for flashing data, including:
the upper computer is used for analyzing the compiled program file to obtain code segment data, data segment data and data size and address range of the code segments and the data segments, and sending the code segment data, the data segment data and the data size and address range of the code segments and the data segments to the lower computer;
and the lower computer is used for performing partition flash according to the code segment data, the data segment data, and the data size and address range of the code segment and the data segment.
In a third aspect, the present disclosure provides a data flashing device, including a processor and a memory storing program instructions, where the processor is configured to execute the data flashing method provided in the foregoing embodiments when executing the program instructions.
In a fourth aspect, the present disclosure provides a computer-readable medium, on which computer-readable instructions are stored, where the computer-readable instructions are executed by a processor to implement a data flashing method provided in the foregoing embodiments.
The technical scheme provided by the embodiment of the application can have the following beneficial effects:
according to the data flashing method in the embodiment of the application, the dynamic distribution of the engine control program and the data is realized through the cooperation of the upper computer and the lower computer. Can the size of automatically regulated code district and data area, be the monoblock principle according to the Block subregion, when the code district grow, look for the closest Block subregion downwards, if the code variation can not cover whole Block subregion, fill with 0xFF at the back, can realize dynamic allocation, extravagant space not. Identifications are added at the beginning and end of the code segment partition and the data segment partition. The upper computer obtains address ranges of the code segments and the data segments by analyzing the initial identification and the ending identification in the generated program file, respectively converts the program and the data into executable flash files, and transmits the address range of each partition to the lower computer in a message conversation mode. The lower computer performs the flash according to the received data, the flash program of the lower computer can keep compatible in real time, the flash program of the lower computer does not need to be frequently updated, the flash is not performed on the residual blank partition parts, and the effectiveness of the flash can be improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
FIG. 1 is a flow diagram illustrating a method of flashing data in accordance with an exemplary embodiment;
FIG. 2 is a diagram illustrating a prior art partitioning method in accordance with an exemplary embodiment;
FIG. 3 is a schematic diagram illustrating a partitioning method in the present application, according to an example embodiment;
FIG. 4 is a block diagram of an apparatus for scrubbing data according to an exemplary embodiment;
FIG. 5 is a block diagram illustrating an exemplary data scrubbing apparatus according to one illustrative embodiment;
FIG. 6 is a schematic diagram illustrating a computer storage medium in accordance with an exemplary embodiment.
Detailed Description
The following description and the drawings sufficiently illustrate specific embodiments of the invention to enable those skilled in the art to practice them.
It should be understood that the described embodiments are only some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of systems and methods consistent with certain aspects of the invention, as detailed in the appended claims.
In the current scheme, the address ranges of the code segments and the data segments of the control program are often planned in advance according to experience. As shown in fig. 2, the Flash partition of the lower computer includes 18 partitions, i.e., Block0-Block17, and in the Flash partition of the lower computer, regardless of the actual size of data, Block0-Block7 are used as the address range of code segments, Block8-Block12 are used as the address range of a CAL area for calibration, and Block13-Block17 are used as the address range of an EOL area for offline calibration.
The lower computer conducts security check with the upper computer according to the address field range planned in advance, data transmitted by the upper computer are written in corresponding intervals in a flashing mode, if the space of a certain field is not completely used up, 0xFF is filled in the following sections in a unified mode, as shown in fig. 2, the actual size of code field data only occupies partitions of Block0-Block5, and all partitions of Block6-Block7 in the following sections are filled with 0 xFF. At the time of a subsequent flush, the filled data is also to perform the flush operation. If the distributed range of the control program in continuous iterative upgrade is not enough, the interval of each segment needs to be divided again, and programs of the upper computer and the lower computer need to be upgraded together, so that the upper and lower software versions are easily incompatible.
As shown in fig. 2, in the prior art, when the version is upgraded from ver.1 to ver.2, the code segment is increased by 100K, the CAL area for calibration in the data segment is increased by 20K, and the EOL area for offline calibration in the data segment is not increased. When the flash is executed, the data in the range of the blocks 0-17 are all subjected to flash, some filling data are also subjected to flash, and the flash time is basically unchanged regardless of the complexity of a program.
Therefore, with the iterative development of the program, the complexity of the function will be increased continuously, if a certain area is subdivided when not enough, the whole partition framework needs to be adjusted, and the upper computer and the lower computer upgrade the software again, which may cause the problem of incompatibility of the software version. Meanwhile, the whole area is written by a brush, and the time consumption is long. The efficiency of the flash is low.
Aiming at the technical problems in the prior art, the embodiment of the application provides a data flashing method which can perform dynamic self-adaptive partitioning and improve the flashing efficiency.
The data flashing method provided by the embodiment of the present application will be described in detail below with reference to the accompanying drawings. Referring to fig. 1, the method specifically includes the following steps.
S101, the upper computer analyzes the compiled program file to obtain code segment data, data segment data, and data sizes and address ranges of the code segments and the data segments, and sends the code segment data, the data segment data, and the data sizes and address ranges of the code segments and the data segments to the lower computer.
In a possible implementation manner, before executing step S101, compiling the program to be flashed according to a preset rule, where the preset rule includes adding different segment identifier differences to code segments and data segments of the program. And the upper computer acquires the program to be flashed compiled according to the preset rule and generates a program file of the self-adaptive partition.
Specifically, the upper computer obtains code segment data and data segment data according to the segment identifier in the program to be written, and stores the code segment data and the data segment data into the Block partition in sequence according to the data size and the Block partition sequence. As shown in fig. 3, first, according to the data size of the code segment, the code segment data is sequentially stored in the Block partition, occupies the Block0-Block5 partition, adds a start identifier at the start position of the code segment, and adds an end identifier at the end position of the code segment. The identification may be made using ASCII.
Further, data of the data segments are sequentially stored into the Block partitions according to the data sizes of the data segments, as shown in fig. 3, the calibration segment CAL of the data segment occupies the Block6-Block7 partitions, and the down-line calibration segment EOL of the data segment occupies the Block8-Block9 partitions. Each segment has an identification of the start and END of the STR and the END of the END.
By the method, the partition can be carried out according to the actual sizes of the code segments and the data segments, and the mark is added at the starting position and the ending position of each segment. To distinguish the address range corresponding to each segment of data.
Further, if the size of the code segment data does not satisfy one or more Block partitions at the time of partitioning, the remaining portion of the Block partition is filled with a preset value, for example, with 0 xFF. When the size of the data segment data does not satisfy one or more Block partitions, the remaining portion of the Block partition is filled with a preset value, for example, 0 xFF.
Further, when the program is upgraded, if the data of the code segment is increased, the code segment Block partition is sequentially expanded backwards, and if the data of the data segment is increased, the data segment Block partition is sequentially expanded backwards. As shown in FIG. 3, when the program is upgraded to Ver.2 version, the CODE area is increased by 100K, the normal calibration area CAL is increased by 20K, the EOL area is not changed, the CODE section moves back to the Block6 partition, only 100K of the Block is occupied, the remaining 156K is filled with 0xFF, and the END of Block6 is added with the CODE _ END END identifier. The nominal CAL region of the data segment is increased by 20K from Block 7-Block 9, where Block9 fills only 20K of them, the remaining 236K with 0xFF and CAL _ END END flags. The down marking EOL area of the data segment is shifted back to Block10-Block 11.
By the method, the sizes of the code area and the data area can be automatically adjusted, according to the principle that the Block partitions are a whole Block, when the code area is enlarged, the closest Block partition is found downwards for expansion, and if the code variation cannot cover the whole Block partition, the rest part is filled with 0 xFF. Dynamic allocation can be realized, and no space is wasted. Identified by ASCII at the beginning and end of each partition.
Further, the upper computer generates a program file of the adaptive partition according to the data of the divided address range, and in a possible implementation manner, the generated program file is a hex file.
And the analysis function software in the upper computer obtains the code segment data, the data size and the address range of the code segment and the data segment according to the program file.
Specifically, analysis function software in the upper computer can automatically analyze the hex file, identify start and END marks of the STR and END in the hex file, and analyze start addresses, END addresses and data sizes of code segments, CAL areas and EOL areas of data segments.
And then the flashing function software in the upper computer respectively generates an executable code segment flashing file, an CAL segment flashing file of the data segment and an EOL segment flashing file of the data segment according to the code segment data, the data segment data, and the data sizes and address ranges of the code segment and the data segment. The executable flash file is a bin file. And analyzing the generated feasible flash file by flash function software in the upper computer to obtain executable code segment data, data segment data, and data size and address range of the code segment and the data segment.
Further, the upper computer and the lower computer perform safety check, the upper computer sends a check request to the lower computer, the lower computer generates a seed file after receiving the check request, the generated seed file is sent to the upper computer, the upper computer performs calculation according to the received seed file to obtain a check value, the lower computer also simultaneously calculates the check value of the sent seed file, and if the check values calculated by the upper computer and the lower computer are the same, the safety check is passed.
If the address range and the size of each address field pass the safety check, the upper computer transmits the address range and the size of each address field to the lower computer through messages, the lower computer receives and stores the address range and the size, and analyzed executable code field data and data field data are transmitted to the lower computer when the address fields are written.
And S102, the lower computer performs partition flash according to the code segment data, the data segment data, and the data size and address range of the code segment and the data segment.
In one possible implementation, the lower computer performs the flash according to the received data.
Specifically, after receiving the code segment data, the data segment data, and the data size and address range of the code segment and the data segment, the lower computer judges whether the data and the address range are in accordance with each other or not, if not, the lower computer performs the flash writing, and the corresponding file is flash written at the position corresponding to the lower computer. For example, the executable code segment data is flushed in the address range corresponding to the lower computer code segment, the executable data segment data is flushed in the address range corresponding to the lower computer data segment, partition flushing is carried out, and the Block partition without data does not need to be flushed. If the error exists, the flashing is stopped, a negative instruction is sent to the upper computer, and the response is stopped.
In one embodiment, after the lower computer performs the partition flash, the method further includes: and the upper computer and the lower computer carry out integrity verification on the data in the preset address range, and if the data pass the integrity verification, the flashing is completed.
Specifically, after the flash is completed, the upper computer and the lower computer adopt a real-time online verification mode to verify the integrity of the flash data. And the upper computer and the lower computer calculate the sum of a section of data in a preset address range according to the same calculation method, and if the sum calculated by the lower computer is the same as the sum calculated by the upper computer, the verification is successful and the data flashing is finished. If the calculated sums are different, the verification fails, and if the verification fails, the verification is stopped in the flashing program of the lower computer so as to continuously flash the program.
By the method, the upper computer analyzes the start address and the end address of the code segment, analyzes the start address and the end address of the data segment and calculates the sizes of the code segment and the data segment by analyzing the start and end marks of the code segment and the data segment in the hex file to respectively generate the bin file which can be executed by flash.
And the upper computer and the lower computer carry out safety check, and if the safety check is passed, the upper computer transmits the address range and the size of each address section and corresponding data to the lower computer.
And the lower computer performs partition flashing according to the code segment data, the data segment data, and the data size and address range of the code segment and the data segment, and after the flashing is completed, the upper computer and the lower computer verify the integrity of the flashing data in a real-time online verification mode.
The partitioning method of the present application is described in detail below with reference to fig. 3, as shown in fig. 3: the Ver.1 version code segment is exactly 1072K, occupies six complete Block partitions of blocks 0-5, a calibration area CAL section 512K of a data segment occupies blocks 6-7, the data segment is used for an EOL section 512K of offline calibration, and the Block 8-9 is occupied. The start of each segment is marked with the start and END of the STR and END. At the moment, the contents of the address space of the Block0-Bolck9 only need to be refreshed during the refreshing, and the following Block10-Block17 do not need to be refreshed. Compared with a full-area flashing mode in the prior art, the method has higher flashing efficiency.
And (3) upgrading to a ver.2 version, increasing the CODE area by 100K, increasing the normal calibration area by 20K, keeping the EOL area unchanged, moving the CODE section back to a Block6 partition and only occupying 100K of the Block6 partition, filling 0xFF in the rest 156K, and adding a CODE _ END identifier at the END of the Block 6. The nominal CAL region of the data segment is increased by 20K from Block 7-Block 9, where Block9 fills only 20K of them, the remaining 236K with 0xFF and CAL _ END END flags. The down marking EOL area of the data segment is shifted back to Block10-Block 11.
It can be seen from fig. 3 that, when the space is upgraded from Ver1 to Ver2, the space is only increased from Block0 to Block9 to Block0 to Block11, and the space of 512K is increased, so that the space utilization rate and the flash efficiency are greatly improved. According to the self-adaptive partitioning method, the blank partition is not written again, and the writing efficiency can be obviously improved.
According to the data flashing method in the embodiment of the application, dynamic self-adaptive partitioning can be realized. According to the principle that the Block partitions are whole blocks, when the code area is enlarged, the closest Block partitions are found downwards, if the code variation cannot cover the whole Block partitions, the later Block partitions are filled with 0xFF, dynamic allocation can be achieved, and space is not wasted. The start and end of the code segment partition and the data segment partition are identified by ASCII. The upper computer analyzes the address ranges of the code segments and the data segments by analyzing the initial identification of the ASCII code in the generated program, converts the program and the data into executable flash files respectively, and transmits the address range of each partition to the lower computer in a message conversation mode. The lower computer performs the flash according to the received data, the flash program of the lower computer can keep compatible in real time, the flash program of the lower computer does not need to be frequently updated, the flash is not performed on the spare part behind the lower computer, and the effectiveness of the flash can be improved.
An embodiment of the present application further provides a data flashing device, where the device is configured to execute the data flashing method according to the foregoing embodiment, and as shown in fig. 4, the device includes: the upper computer 401 and the lower computer 402, in a possible implementation manner, the upper computer 401 may be a PC host, and the lower computer 402 may be a single chip microcomputer.
The upper computer 401 is used for analyzing the compiled program file to obtain code segment data, data segment data, and data sizes and address ranges of the code segments and the data segments, and sending the code segment data, the data segment data, and the data sizes and address ranges of the code segments and the data segments to the lower computer;
and the lower computer 402 is used for performing partition flash according to the code segment data, the data segment data, and the data size and address range of the code segment and the data segment.
It should be noted that, when the data flashing apparatus provided in the foregoing embodiment executes the data flashing method, only the division of the functional modules is taken as an example, and in practical applications, the function distribution may be completed by different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules, so as to complete all or part of the functions described above. In addition, the data flashing device and the data flashing method provided by the above embodiments belong to the same concept, and details of implementation processes are found in the method embodiments, and are not described herein again.
The embodiment of the present application further provides an electronic device corresponding to the data flashing method provided in the foregoing embodiment, so as to execute the data flashing method.
Please refer to fig. 5, which illustrates a schematic diagram of an electronic device according to some embodiments of the present application. As shown in fig. 5, the electronic apparatus includes: the processor 500, the memory 501, the bus 502 and the communication interface 503, wherein the processor 500, the communication interface 503 and the memory 501 are connected through the bus 502; the memory 501 stores a computer program that can be executed on the processor 500, and the processor 500 executes the computer program to perform the method for flashing data provided in any of the foregoing embodiments of the present application.
The Memory 501 may include a high-speed Random Access Memory (RAM) and may also include a non-volatile Memory (non-volatile Memory), such as at least one disk Memory. The communication connection between the network element of the system and at least one other network element is realized through at least one communication interface 503 (which may be wired or wireless), and the internet, a wide area network, a local network, a metropolitan area network, and the like can be used.
The processor 500 may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware or instructions in the form of software in the processor 500. The Processor 500 may be a general-purpose Processor, and includes a Central Processing Unit (CPU), a Network Processor (NP), and the like; but may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components. The various methods, steps, and logic blocks disclosed in the embodiments of the present application may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in connection with the embodiments of the present application may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software module may be located in ram, flash memory, rom, prom, or eprom, registers, etc. storage media as is well known in the art. The storage medium is located in the memory 501, and the processor 500 reads the information in the memory 501, and completes the steps of the method in combination with the hardware thereof.
The electronic device provided by the embodiment of the application and the data flashing method provided by the embodiment of the application have the same inventive concept and have the same beneficial effects as the method adopted, operated or realized by the electronic device.
Referring to fig. 6, the computer-readable storage medium is an optical disc 600, on which a computer program (i.e., a program product) is stored, and when the computer program is executed by a processor, the computer program executes the method for flashing data provided in any of the foregoing embodiments.
It should be noted that examples of the computer-readable storage medium may also include, but are not limited to, phase change memory (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory, or other optical and magnetic storage media, which are not described in detail herein.
The computer-readable storage medium provided by the above embodiments of the present application and the data flashing method provided by the embodiments of the present application have the same beneficial effects as the method adopted, run or implemented by the application program stored in the computer-readable storage medium.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above examples only show some embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A method for flashing data, comprising:
the upper computer analyzes the compiled program file to obtain code segment data, data segment data and data size and address range of the code segments and the data segments, and sends the code segment data, the data segment data and the data size and address range of the code segments and the data segments to the lower computer;
and the lower computer performs partition flash according to the code segment data, the data segment data, and the data size and address range of the code segment and the data segment.
2. The method of claim 1, wherein before the upper computer parses the compiled program file, the method further comprises:
acquiring a program to be flashed compiled according to a preset rule;
and carrying out dynamic self-adaptive partitioning according to the program to be flashed to generate the program file.
3. The method of claim 2, wherein dynamically adaptively partitioning according to the program to be flashed comprises:
obtaining code segment data and data segment data according to the segment identification in the program to be flashed;
sequentially storing the code segment data and the data segment data into a Block partition according to the data size and the Block partition sequence;
the starting positions of the code segment partition and the data segment partition contain starting marks, and the ending positions of the code segment partition and the data segment partition contain ending marks.
4. The method of claim 3, further comprising:
when the size of the code segment data does not meet one or more Block partitions, filling the rest parts of the Block partitions with preset values;
when the size of the data segment data does not satisfy one or more Block partitions, the rest of the Block partitions are filled with preset values.
5. The method of claim 3, further comprising:
when the program is upgraded, if the data of the code segment is increased, the code segment Block partitions are sequentially expanded backwards, and if the data of the data segment is increased, the data segment Block partitions are sequentially expanded backwards.
6. The method of claim 1, wherein the upper computer parses the compiled program file to obtain the code segment data, the data segment data, and the data sizes and address ranges of the code segments and the data segments, and sends the code segment data, the data segment data, and the data sizes and address ranges of the code segments and the data segments to the lower computer, comprising:
analyzing the program file by analysis function software in the upper computer to obtain code segment data, data segment data, and data size and address range of the code segment and the data segment;
the flashing function software in the upper computer generates an executable code segment flashing file and a data segment flashing file according to the code segment data, the data segment data and the data size and address range of the code segment and the data segment, analyzes the code segment flashing file and the data segment flashing file and obtains the executable code segment data, the data segment data and the data size and address range of the code segment and the data segment;
the upper computer and the lower computer perform safety check;
and if the data passes the safety check, sending the executable code segment data, the data size and the address range of the code segment and the data segment to a lower computer.
7. The method of claim 1, wherein after the lower computer performs the partition flashing according to the code segment data, the data segment data, and the data size and address range of the code segment and the data segment, the method further comprises:
the upper computer and the lower computer carry out integrity check on the data in the preset address range;
and if the integrity check is passed, completing the flash.
8. An apparatus for flashing data, comprising:
the upper computer is used for analyzing the compiled program file to obtain code segment data, data segment data and data size and address range of the code segment and the data segment, and sending the code segment data, the data segment data and the data size and address range of the code segment and the data segment to the lower computer;
and the lower computer is used for performing partition flash according to the code segment data, the data segment data, and the data size and address range of the code segment and the data segment.
9. Apparatus for flashing data comprising a processor and a memory having stored thereon program instructions, the processor being configured, on execution of the program instructions, to perform a method of flashing data as claimed in any of claims 1 to 7.
10. A computer readable medium having computer readable instructions stored thereon which are executed by a processor to implement a method of flashing data as claimed in any one of claims 1 to 7.
Priority Applications (1)
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| CN202111300961.0A CN114185572A (en) | 2021-11-04 | 2021-11-04 | Data flashing method, device, equipment and storage medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115599739A (en) * | 2022-09-21 | 2023-01-13 | 深圳市航顺芯片技术研发有限公司（Cn） | Chip capable of adjusting storage structure and adjusting method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115599739A (en) * | 2022-09-21 | 2023-01-13 | 深圳市航顺芯片技术研发有限公司（Cn） | Chip capable of adjusting storage structure and adjusting method |
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