CN114185486A

CN114185486A - Data writing method of DRAM (dynamic random Access memory) and DRAM control system

Info

Publication number: CN114185486A
Application number: CN202111361888.8A
Authority: CN
Inventors: 周恺
Original assignee: Shenzhen Demingli Electronics Co Ltd
Current assignee: Shenzhen Demingli Electronics Co Ltd
Priority date: 2021-11-17
Filing date: 2021-11-17
Publication date: 2022-03-15
Anticipated expiration: 2041-11-17
Also published as: CN114185486B

Abstract

The invention discloses a data writing method and a system of a DRAM (dynamic random access memory), wherein the method comprises the following steps: the DRAM controller receives data to be written, the data to be written comprises a data section and an address section, and the data section corresponds to the address section; judging whether the length of the continuous logic value of the data segment is greater than or equal to a preset length, wherein the continuous logic value is continuous 0 or 1; if the length of the continuous logic value is greater than or equal to the preset length, acquiring a lookup table, wherein the lookup table comprises the continuous logic value stored in a DRAM memory and an address range where the stored continuous logic value is located; inquiring whether the address range to be written corresponding to the continuous logic value is in a lookup table or not; if so, sending an indication signal that the continuous logic value does not need to be written into the DRAM controller, and writing other logic values in the data segment according to a common writing mode, so that the access times of the DRAM memory are reduced, the writing speed of the continuous logic value is increased, and the data writing speed of the DRAM memory is increased.

Description

Data writing method of DRAM (dynamic random Access memory) and DRAM control system

Technical Field

The invention relates to the technical field of storage, in particular to a data writing method of a DRAM (dynamic random access memory) and a DRAM control system.

Background

DRAM is a commonly used data storage device, and the data storage is realized by charging and discharging a capacitor of each memory cell, so as to control a high level or a low level of stored data, corresponding to data 1 or 0. The DRAM controller, which currently controls and communicates data to the DRAM, requires time to precharge the DRAM before each write, a row activation pre-operation, and writes each memory cell sequentially in address order at each write (see fig. 1). Because the internal default storage units of the DRAM are all high level after the DRAM is electrified and initialized, if the data is transmitted to a string of continuous 1 data of the DRAM and written, the traditional method is to carry out pre-operation on the DRAM and access the storage units without modifying the data; for a read operation, a pre-operation is performed first, and then data is read for each memory cell. Access operations are added upon writing of such all-1 data. Some consecutive memory cells may have consecutive data 0's again. Likewise, re-accessing and writing 0 to consecutive data 0 addresses also increases the access operation, reducing the write speed of the DRAM.

Disclosure of Invention

The invention aims to provide a data writing method of a DRAM (dynamic random access memory) and a DRAM monitoring system.

In order to achieve the above object, a first aspect of the present invention provides a data writing method for a DRAM memory, including: the method comprises the steps that a DRAM controller receives data to be written, the data to be written comprises a data section and an address section, and the data section corresponds to the address section; judging whether the length of the continuous logic value of the data segment is greater than or equal to a preset length or not, wherein the continuous logic value is continuous 0 or 1; if the length of the continuous logic value is greater than or equal to the preset length, acquiring a lookup table, wherein the lookup table comprises the continuous logic value stored in a DRAM memory and an address range where the stored continuous logic value is located; inquiring whether the address range to be written corresponding to the continuous logic value is in the lookup table or not; and if so, sending an indication signal that the continuous logic value does not need to be written to the DRAM controller.

In one embodiment, the method further comprises the following steps: and receiving the preset length configured by the user.

In one embodiment, the method further comprises the following steps: determining a data length of the data segment; if the data length is smaller than the preset length, judging whether the data length is smaller than a burst length, wherein the burst length is smaller than the preset length and is the data length for setting the minimum write-once of the DRAM; and if the data length is smaller than the burst length, sending an indication signal that the data segment does not need to be written to the DRAM controller.

In one embodiment, the method further comprises the following steps: and if the data length is larger than the burst length, writing according to a preset writing rule of the DRAM.

In one embodiment, after determining whether the length of the continuous logical value of the data segment is greater than a preset length, the method further includes: and if the length of the continuous logic value is smaller than the preset length, writing according to a preset writing rule of the DRAM.

In one embodiment, after querying whether the address range to be written corresponding to the continuous logical value is in a lookup table according to the correspondence between the data segment and the address segment, the method further includes: if not, writing is executed according to the preset writing rule of the DRAM.

In one embodiment, the determining whether the length of the continuous logic value of the data segment is greater than a preset length includes: and judging whether the length of the continuous logic value of the data segment is greater than the preset length through a judging circuit.

In one embodiment, the method further comprises the following steps: acquiring a logic value stored in the DRAM memory and an address of the logic value; writing the logical value and the address of the logical value in the DRAM memory to the lookup table.

In one embodiment, after the obtaining the logical value and the address of the logical value stored in the DRAM memory, the method further includes: judging whether the logic values stored in the DRAM memory contain continuous logic values larger than the preset length; if yes, the writing the logical value in the DRAM memory and the address of the logical value into the lookup table includes: and writing addresses of continuous logic values larger than or equal to the preset length and continuous logic values larger than or equal to the preset length in the logic values in the DRAM memory into the lookup table.

A second aspect of the present invention provides a DRAM control system, comprising:

the device comprises a DRAM controller circuit, a lookup table, a DRAM memory and a judgment circuit;

the DRAM controller circuit comprises a DRAM controller and a judgment circuit;

the DRAM controller is used for receiving data to be written, the data to be written comprises a data segment and an address segment, and the data segment corresponds to the address segment;

the judging circuit is used for judging whether the length of the continuous logic value of the data segment is greater than a preset length, and the continuous logic value is continuous 0 or 1;

the DRAM controller is used for sending a query request to the lookup table if the length of the continuous logic value is greater than or equal to the preset length;

the lookup table is used for querying whether an address range to be written corresponding to the continuous logic value exists or not according to the query request, wherein the lookup table comprises the continuous logic value stored in the DRAM memory and the address range where the stored continuous logic value is located;

and the DRAM controller is used for sending an indication signal that the continuous logic value does not need to be written to the DRAM controller if the address range to be written corresponding to the continuous logic value exists in the lookup table.

The data writing method of the DRAM comprises the following steps: when the DRAM controller receives data to be written, the data to be written comprises a data segment and an address segment, and the data segment corresponds to the address segment; judging whether the length of the continuous logic value of the data segment is greater than a preset length, wherein the continuous logic value is continuous 0 or 1; if the length of the continuous logic value is greater than or equal to the preset length, acquiring a lookup table, wherein the lookup table comprises the continuous logic value stored in a DRAM memory and an address range where the stored continuous logic value is located; inquiring whether the address range to be written corresponding to the continuous logic value is in a lookup table or not; and if so, sending an indication signal that the continuous logic value does not need to be written to the DRAM controller. The lookup table of the method records data and data addresses stored in a DRAM memory, a DRAM controller judges the continuous logic value of the written data when receiving a task of the written data, if the length of the continuous logic value is longer, whether the DRAM memory has storage addresses with the same address range of the continuous logic value is judged through the recorded information in the lookup table, if the storage addresses exist, the data in the corresponding storage addresses in the DRAM memory are kept unchanged, the access times of the DRAM memory are reduced, and the data writing speed is accelerated.

Additional features and advantages of embodiments of the invention will be set forth in the detailed description which follows.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic diagram of a DRAM memory control system of the present invention;

FIG. 2 is a schematic diagram of a DRAM memory control system of the present invention;

FIG. 3 is a flow chart illustrating a data writing method of a DRAM memory according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be noted that the following examples are only illustrative of the present invention, and do not limit the scope of the present invention. Similarly, the following examples are only some but not all examples of the present invention, and all other examples obtained by those skilled in the art without any inventive work are within the scope of the present invention.

The invention provides a data writing method of a DRAM memory.

Referring to fig. 1, fig. 1 is a schematic diagram of a DRAM control system, the DRAM control system 100 includes: a DRAM controller 201, a lookup table 202, a DRAM memory 203, and a judgment circuit 204; the DRAM controller 201 is configured to receive data to be written, where the data to be written includes a data segment and an address segment, and the data segment corresponds to the address segment; the judging circuit 204 is configured to judge whether the length of a continuous logic value of the data segment is greater than a preset length, where the continuous logic value is a continuous 0 or 1; the DRAM controller 201 is configured to send a query request to the lookup table 202 if the length of the continuous logic value is greater than or equal to a preset length; a lookup table 202, configured to query whether an address range to be written corresponding to the continuous logical value exists according to the query request, where the lookup table 202 includes the continuous logical value stored in the DRAM 203 and an address range in which the stored continuous logical value is located; the DRAM controller 202 is configured to send an indication signal to the DRAM memory 203 to keep the address range to be written corresponding to the continuous logical value unchanged if the address range to be written corresponding to the continuous logical value exists in the lookup table 202.

As shown in fig. 2, fig. 2 is a flow chart illustrating a data writing method of a DRAM memory. It should be noted that the method of the present invention is not limited to the flow sequence shown in fig. 2 if the results are substantially the same.

The method comprises the following steps:

s301: the DRAM controller receives data to be written.

In this embodiment, the data to be written includes a data segment and an address segment, and the data segment corresponds to the address segment.

The DRAM controller is used for controlling data read-write operation of the DRAM. The data to be written refers to data that is ready to be written to the DRAM memory. The data to be written comprises a data segment and an address segment, wherein the data segment refers to the data to be stored, and the address segment refers to the storage address of the data. Data segment to address segment correspondence means that there is a unique corresponding address for each data.

And after the DRAM control receives the data to be written, writing the data to be written into the DRAM according to the address section according to the preset writing rule. The DRAM controller reads data from the DRAM memory according to a preconfigured read rule upon receiving a read request to read the data.

S302, judging whether the length of the continuous logic value of the data segment is larger than or equal to a preset length.

In this particular embodiment, consecutive logical values are consecutive 0 or 1.

The continuous logic value of a data segment refers to that the same logic value in the data segment is continuous, such as continuous 0 or 1, that is, 1 appears multiple times continuously or 0 appears multiple times continuously, such as a data segment "0000, 1111, 1110, 0000, 0000", where the data segment includes four continuous 0 s in front, 7 continuous 1 s in the middle, and 9 continuous 0 s in the back, where 4, 7, and 9 are lengths of continuous logic values, and the lengths of continuous logic values may also be expressed in other forms. The preset length is a preset length threshold value, and the length threshold value is related to the specified read-write length of the DRAM memory, for example, the maximum length that the DRAM memory can write at a time is taken as the preset length. When the DRAMA memory is shipped, a corresponding write rule is configured, and the write rule includes a maximum length that data can be written each time.

S303, if the length of the continuous logic value is larger than or equal to the preset length, a lookup table is obtained.

In this particular embodiment, the lookup table includes consecutive logical values stored in the DRAM memory and a range of addresses in which the consecutive logical values are stored.

S304, inquiring whether the address range to be written corresponding to the continuous logic value is in the lookup table.

S305, if yes, sending an indication signal that the continuous logic value does not need to be written to the DRAM controller.

The lookup table is a table for storing data and data addresses in the DRAM memory, and the lookup table may be stored in the DRAM memory or in another memory, and the other memory may communicate with the DRAM. The lookup table may store the continuous logic value stored in the DRAM memory and the address where the stored continuous logic value is located, or may store the discontinuous logic value and the address where the discontinuous logic value is located.

And when the length of the continuous logic value of the data segment of the data to be written is greater than the preset length, inquiring whether an address range corresponding to the address range of the continuous logic value exists in the lookup table. If the logical value identical to the continuous logical value is found in the lookup table, and the address range of the continuous logical value is correspondingly consistent with the address range in the lookup table, it indicates that the continuous logical value already exists in the DRAM memory, and the write operation on the data to be written is stopped without performing the write operation again. And sending an indication signal for indicating that the writing operation is not needed to be carried out to the DRAM controller, wherein the DRAM controller only needs to keep the data of the address range where the continuous logic value is located unchanged after receiving the indication signal, so that the frequency of accessing the DRAM memory is reduced, the writing speed of the continuous logic value is increased, and the writing speed of the data to be written is increased.

According to the data writing method of the DRAM, the data and the addresses in the DRAM are stored in the lookup table, when the data are written into the DRAM, the length of the continuous logic value of the data segment of the data to be written is judged firstly, if the length of the continuous logic value is larger than or equal to the preset critical length, whether consistent data and addresses exist is searched in the lookup table, and if yes, the writing operation is not required to be executed, so that the writing times of the DRAM are reduced, and the data writing speed of the DRAM is improved.

In one embodiment, the data writing method for a DRAM memory further includes: and receiving the preset length configured by the user.

Specifically, the data write length of the DRAM memory configuration refers to the write length determined by the user according to the requirement. Wherein the preset length is less than or equal to the maximum writing length of data written each time. The DRAM memory can write the maximum data length every time as a critical value, the writing times of data can be effectively reduced, if the maximum writing length is 8, and 8 is taken as a preset length, whether the writing operation needs to be executed or not is judged, if the length of the continuous logic value of the data segment is more than or equal to 8, and the address corresponding to the continuous logic value is found in the lookup table, the writing operation can be directly skipped, and only the DRAM controller needs to be informed that the writing is existed in the memory. Therefore, the access times of the DRAM memory are reduced, and the data writing speed of the DRAM memory is improved.

In one embodiment, the data writing method for a DRAM memory further includes: determining a data length of the data segment; if the data length is smaller than the preset length, judging whether the data length is smaller than a burst length, wherein the burst length is smaller than the preset length and is the data length for setting the minimum write-once of the DRAM; and if the data length is smaller than the burst length, sending an indication signal that the data segment does not need to be written to the DRAM controller.

Specifically, a preset length inside the DRAM memory is used to set a minimum write-once data length, which is termed a "burst length". And if the data length of the data segment is smaller than the burst length, not writing. The input data length is set to be larger than the burst length by default, and the preset length is set to be larger than the burst length by default.

In one embodiment, after determining whether the length of the continuous logic value of the data segment is greater than the preset length, the method further includes: and if the length of the continuous logic value in the data section is smaller than the preset length, performing writing according to a preset writing rule of the DRAM.

The writing rule configured in advance is that the writing rule of the DRAM memory is defined in advance before data is written into the DRAM memory, and the writing rule includes rules related to the written data, such as a writing sequence and a writing length, wherein the writing sequence includes rows/columns of memory cells written first. If the DRAM memory includes a plurality of BANKs, each of which includes a plurality of memory cells, the location of the memory cell is represented by the BANK (BANK), the row and the column of the BANK.

And if the length of the continuous logic value of the data segment is smaller than the preset length, if so, the data segment to be written is written into the DRAM according to the write-in rule defined before and the maximum write-in length of each time. And writing data according to a common data writing rule for the data segment without longer continuous logic values.

In one embodiment, if the data length < burst length < preset length, no write operation is performed to the DRAM memory at all; if the burst length is less than the data length and less than the preset length, directly writing into the DRAM, if the burst length is less than the preset length and less than the data length, searching the lookup table, and if the value of the address range in the lookup table is the same as the data section, not writing into the DRAM.

In one embodiment, after querying whether the address range to be written corresponding to the continuous logical value is in the lookup table according to the correspondence between the data segment and the address segment, the method further includes: if not, the writing is executed according to the preset writing rule of the DRAM.

The writing rule is defined the same as the writing rule in the above embodiment, and is not described herein again. If the address consistent with the address range of the continuous logic value cannot be found in the lookup table, it indicates that no data consistent with the data of the continuous logic value of the data segment exists in the DRAM, and the data segment is written according to a common writing method.

In one embodiment, the preconfigured write rule includes a preset length, and the preset length is a maximum length of data written in each time of the DRAM storage; performing a write data segment according to a preconfigured write rule for a DRAM memory, comprising: determining a logic value to be written in the data segment at the time according to the preset length; and writing the logic value to be written into the DRAM according to the address of the logic value to be written.

Specifically, the length of the data segment is greater than the maximum length of a single write of the DRAM memory, i.e., the length of the data segment is greater than the maximum length of each write of data of the DRAM memory. And splitting the data segment according to the maximum length of the single writing, wherein the data segment is split into multiple times of writing, and the maximum value of the writing length of each time of the data segment is the maximum length of the single writing. And writing the split data segment and the address to be written of the split data segment into the DRAM.

In one embodiment, determining whether the length of the continuous logic value of the data segment is greater than a preset length includes: and judging whether the length of the continuous logic value of the data segment is greater than the preset length through a judging circuit.

Specifically, the judgment circuit is configured to judge whether a length of a continuous logic value in a data segment of the data to be written is greater than a preset length. The judgment circuit is connected with the DRAM controller and judges the continuous logic value of the data to be written received by the DRAM controller.

In one embodiment, the writing method of the DRAM memory further includes: acquiring a logic value stored in a DRAM memory and an address of the logic value; the logical values and the addresses of the logical values in the DRAM memory are written to a look-up table.

Specifically, before the lookup table is obtained, the logical value and the address of the logical value stored in the DRAM memory are written into the lookup table, and the logical value and the address of the logical value stored in the DRAM memory are read by the DRAM controller, and the DRAM controller writes the read data into the lookup table. After the DRAM controller acquires the logical value and the address of the logical value from the DRAM memory, it may also determine the acquired logical value and determine whether to write the acquired logical value and the address of the logical value into the lookup table.

In one embodiment, when the logical value and the address of the logical value are obtained from the DRAM, data obtaining may be performed according to a preset condition, if corresponding data is returned, the returned data is written into the lookup table, and if data is not returned, the writing operation of the lookup table is not required to be performed.

In one embodiment, after obtaining the logical value and the address of the logical value stored in the DRAM memory, the method further includes: judging whether the logic values stored in the DRAM memory contain continuous logic values larger than or equal to a preset length; if so, writing the logical value in the DRAM memory and the address of the logical value into a lookup table, comprising: and writing addresses of continuous logic values larger than a preset length and continuous logic values larger than the preset length in the logic values in the DRAM into a lookup table.

After the logical values stored in the DRAM memory are obtained, it is determined whether the length of consecutive logical values in the logical values stored in the DRAM memory is greater than a preset length, if not, it indicates that data of the DRAM memory does not need to be written into the lookup table, if so, consecutive logical values whose length is greater than or equal to the preset length in the consecutive logical values stored in the DRAM memory are written into the lookup table, and addresses of the consecutive logical values are also written into the lookup table, where the writing of the addresses may be writing an address corresponding to each logical value, or writing an address where a start logical value of the consecutive logical value is located and a position where an end logical value is located, or writing an address where the start logical value is located and a length of the consecutive logical value, and the like, and specifically, the address representing the consecutive logical value is not specifically limited herein.

In one embodiment, the data writing method for a DRAM memory further includes: initializing a DRAM memory so that data stored in the DRAM memory are all 1; initializing a lookup table, wherein the lookup table represents a logical value stored in the DRAM memory and an address of the logical value, wherein each logical value of the logical values stored in the DRAM memory is 1.

After the DRAM control system is powered on, the DRAM is initialized, wherein after the DRAM is initialized, the data stored in each storage unit is 1. Initializing a lookup table, wherein the lookup table records that the data stored in the DRAM memory are all 1, and the addresses comprise all the addresses of the DRAM memory.

In one embodiment, the data writing method of the DRAM memory further includes: and if the address range to be written corresponding to the continuous logic value is in the lookup table and the data segment further comprises other logic values except the other logic values before the continuous logic value, writing the other logic values into the DRAM according to the preset writing rule of the DRAM.

In the several embodiments provided in the present invention, it should be understood that the disclosed system and method may be implemented in other ways. For example, the above-described system embodiments are merely illustrative, and for example, a division of modules or units is merely a logical division, and an actual implementation may have another division, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not implemented. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

Units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be substantially or partially implemented in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, a network device, or the like) or a processor (processor) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

The above description is only a part of the embodiments of the present invention, and not intended to limit the scope of the present invention, and all equivalent devices or equivalent processes performed by the present invention through the contents of the specification and the drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.

Claims

1. A data writing method of a DRAM (dynamic random access memory) is characterized by comprising the following steps:

the method comprises the steps that a DRAM controller receives data to be written, the data to be written comprises a data section and an address section, and the data section corresponds to the address section;

judging whether the length of the continuous logic value of the data segment is greater than or equal to a preset length or not, wherein the continuous logic value is continuous 0 or 1;

if the length of the continuous logic value is greater than or equal to the preset length, acquiring a lookup table, wherein the lookup table comprises the continuous logic value stored in a DRAM memory and an address range where the stored continuous logic value is located;

inquiring whether the address range to be written corresponding to the continuous logic value is in the lookup table or not;

and if so, sending an indication signal that the continuous logic value does not need to be written to the DRAM controller.

2. The method of claim 1, further comprising:

and receiving the preset length configured by the user.

3. The method of claim 1, further comprising:

determining a data length of the data segment;

if the data length is smaller than the preset length, judging whether the data length is smaller than a burst length, wherein the burst length is smaller than the preset length and is the data length for setting the minimum write-once of the DRAM;

and if the data length is smaller than the burst length, sending an indication signal that the data segment does not need to be written to the DRAM controller.

4. The method of claim 3, further comprising:

and if the data length is larger than the burst length, writing according to a preset writing rule of the DRAM.

5. The method of claim 1, wherein after determining whether the length of the consecutive logical values of the data segment is greater than a preset length, the method further comprises:

and if the length of the continuous logic value is smaller than the preset length, writing according to a preset writing rule of the DRAM.

6. The method according to claim 1, wherein after querying whether the address range to be written corresponding to the consecutive logical value is in a lookup table according to the correspondence between the data segment and the address segment, the method further comprises:

if not, writing is executed according to the preset writing rule of the DRAM.

7. The method of claim 1, wherein the determining whether the length of the consecutive logical values of the data segment is greater than a preset length comprises:

and judging whether the length of the continuous logic value of the data segment is greater than the preset length through a judging circuit.

8. The method according to any one of claims 1-7, further comprising:

acquiring a logic value stored in the DRAM memory and an address of the logic value;

writing the logical value and the address of the logical value in the DRAM memory to the lookup table.

9. The method of claim 8, wherein after the obtaining the logical value and the address of the logical value stored in the DRAM memory, the method further comprises:

judging whether the logic values stored in the DRAM memory contain continuous logic values larger than the preset length;

if yes, the writing the logical value in the DRAM memory and the address of the logical value into the lookup table includes: and writing addresses of continuous logic values larger than or equal to the preset length and continuous logic values larger than or equal to the preset length in the logic values in the DRAM memory into the lookup table.

10. A DRAM control system, characterized in that the control system comprises:

the DRAM controller circuit comprises a DRAM controller and a judgment circuit;