CN114178979A - Method for optimizing CMP cleaning capacity - Google Patents

Method for optimizing CMP cleaning capacity Download PDF

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Publication number
CN114178979A
CN114178979A CN202111544391.XA CN202111544391A CN114178979A CN 114178979 A CN114178979 A CN 114178979A CN 202111544391 A CN202111544391 A CN 202111544391A CN 114178979 A CN114178979 A CN 114178979A
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CN
China
Prior art keywords
grinding
wafer
cmp cleaning
cleaning capacity
optimizing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202111544391.XA
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Chinese (zh)
Inventor
李松
宋振伟
张守龙
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hua Hong Semiconductor Wuxi Co Ltd
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Hua Hong Semiconductor Wuxi Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hua Hong Semiconductor Wuxi Co Ltd filed Critical Hua Hong Semiconductor Wuxi Co Ltd
Priority to CN202111544391.XA priority Critical patent/CN114178979A/en
Publication of CN114178979A publication Critical patent/CN114178979A/en
Pending legal-status Critical Current

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    • BPERFORMING OPERATIONS; TRANSPORTING
    • B24GRINDING; POLISHING
    • B24BMACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00Lapping machines or devices; Accessories
    • B24B37/04Lapping machines or devices; Accessories designed for working plane surfaces
    • B24B37/07Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool
    • B24B37/10Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool for single side lapping
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B24GRINDING; POLISHING
    • B24BMACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00Lapping machines or devices; Accessories
    • B24B37/04Lapping machines or devices; Accessories designed for working plane surfaces
    • B24B37/042Lapping machines or devices; Accessories designed for working plane surfaces operating processes therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30625With simultaneous mechanical treatment, e.g. mechanico-chemical polishing

Abstract

The invention provides a method for optimizing CMP cleaning capacity, which comprises the steps of providing a wafer, wherein a contact hole is formed on the wafer and is filled with conductive metal; carrying out first grinding on the wafer by using an acidic grinding fluid, wherein the wafer reacts with the acidic grinding fluid to generate a by-product; cleaning the wafer to remove the acidic grinding fluid and the by-products on the wafer; and performing second grinding on the wafer by using the alkaline grinding fluid. The invention avoids the complex from gathering at the contact hole, reduces the formation of defects when carrying out chemical mechanical planarization, avoids influencing the product yield, and meets the requirements of the optimized result and the yield result.

Description

Method for optimizing CMP cleaning capacity
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for optimizing CMP cleaning capacity.
Background
Tungsten reacts during Chemical Mechanical Planarization (CMP) to produce tungsten oxide. In the prior art, the purpose of grinding is achieved by utilizing the characteristic that tungsten oxide is soluble in a strong acid environment and assisting mechanical action, and after a wafer is roughly ground by adopting an acidic grinding fluid, a complex formed by the reaction of a tungsten rough grinding byproduct and a finely ground (alkaline) grinding fluid is left.
After entering the 55nm technology node, the filling process faces more challenges: the aspect ratio of the contact hole may exceed 6: 1, high concentration plasma process (HDP) has not been able to meet the filling requirement, so High Aspect Ratio Process (HARP) begins to be used at 55nm to replace high concentration plasma (HDP) forming layer, and High Aspect Ratio Process (HARP) film quality is faster than high concentration plasma process (HDP) grinding rate, so tungsten at contact holes forms a certain shape, grinding byproducts are easy to gather, general cleaning cannot be effectively removed, subsequent stations are enhanced, defects are formed, and product yield is affected.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for optimizing CMP cleaning capability, which is used to solve the problems in the prior art that after tungsten at the contact hole is formed into a certain shape, the polishing by-products are easily accumulated, general cleaning cannot be effectively removed, and defects are formed when a subsequent station is enhanced, thereby affecting the yield of products.
To achieve the above and other related objects, the present invention provides a method for optimizing CMP cleaning capability, comprising:
providing a wafer and a grinding device, wherein a contact hole is formed on the wafer and is filled with conductive metal;
secondly, performing first grinding on the substrate by using an acidic grinding fluid by using the grinding device, wherein the wafer reacts with the acidic grinding fluid to generate a byproduct;
cleaning the wafer to remove the acidic grinding fluid and byproducts on the wafer;
and fourthly, performing second grinding on the substrate by using the grinding device by using alkaline grinding fluid.
Preferably, the aspect ratio of the contact hole in the first step is greater than 6: 1.
preferably, the conductive metal generation method in the first step is a high aspect ratio process.
Preferably, the material of the conductive metal in the first step is tungsten.
Preferably, the by-product in step two is tungsten oxide.
Preferably, the second polishing in the fourth step further includes cleaning a polishing pad in the polishing apparatus and cleaning the wafer.
Preferably, the first grinding in step two is rough grinding.
Preferably, the second grinding in step four is finish grinding.
As described above, the method for optimizing CMP cleaning capability of the present invention has the following advantageous effects:
the invention avoids the complex from gathering at the contact hole, reduces the formation of defects when carrying out chemical mechanical planarization, avoids influencing the product yield, and meets the requirements of the optimized result and the yield result.
Drawings
FIG. 1 is a schematic process flow diagram of the present invention;
fig. 2 is a schematic diagram illustrating yield detection according to an embodiment of the invention.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Referring to fig. 1, the present invention provides a method for optimizing CMP cleaning capability, comprising:
providing a wafer and a grinding device, wherein after the wafer is formed into a required structure through a front-end technology (FEOL), a contact hole needs to be formed in a back-end technology (BEOL), conductive metal is filled in the contact hole to form ohmic contact with the structure on the wafer, the grinding device is a CMP grinding device and comprises a grinding head and a grinding pad, when the wafer needs to be ground, the wafer is placed on the grinding pad, the grinding head is matched with grinding fluid to grind the wafer, and the grinding fluid can be alkaline grinding fluid and acidic grinding fluid;
in an alternative embodiment, the aspect ratio of the contact hole in the first step is greater than 6: plasma Chemical Vapor Deposition (PCVD), a technique for generating a solid film by activating a reaction gas with plasma to promote a chemical reaction on a substrate surface or in a near-surface space. The basic principle of the plasma chemical vapor deposition technology is that under the action of a high-frequency or direct-current electric field, a source gas is ionized to form plasma, low-temperature plasma is used as an energy source, a proper amount of reaction gas is introduced, and plasma discharge is utilized to activate the reaction gas and realize the chemical vapor deposition.
As integrated circuits have evolved into 55nm technology nodes, HDP technology has not been able to meet the filling requirements of small-sized trenches, and a new filling Process technology, i.e., High Aspect Ratio Process (HARP), has been developed. The HARP process does not have the aid of plasma and requires the trenches to have a specific topography, such as V-shaped trenches at a specific angle. It is desirable to use Harp instead of HDP, which has a faster polishing rate than HDP, so that tungsten at the contact holes forms a topography that tends to accumulate polishing by-products.
In an alternative embodiment, the conductive metal generation method in the first step is a high aspect ratio process.
In an alternative embodiment, the conductive metal in the first step is tungsten.
Secondly, carrying out first grinding on the wafer by using acid grinding fluid, wherein the first grinding is rough grinding and is used for removing large conductive metals, the wafer reacts with the acid grinding fluid to generate byproducts, and the byproducts are complexes generated by the reaction of oxides of the conductive metals and alkaline solution;
in an alternative embodiment, in the case that the conductive metal material is tungsten, the byproduct in the second step is tungsten oxide, and during the grinding, the tungsten is easily reacted with an oxidant to generate tungsten oxide, which reacts to generate a complex when being contacted with an alkaline solution.
Cleaning the wafer to remove the acidic grinding fluid and the by-products on the wafer so as to prevent the by-products from reacting with the subsequent alkaline solution to generate complexes;
in an optional implementation mode, the first grinding and the second grinding are controlled by Recipe, the Recipe is a menu and comprises each step of processing specification for a wafer in the production process, the Recipe in the second grinding in the prior art sequentially passes through a grinding head slow accelerated pressurization step, a main grinding step, a grinding pad cleaning step and a wafer cleaning step, and due to the formation of a complex, the wafer is cleaned in the defect step three during the main grinding step between the grinding head slow accelerated pressurization step and the main grinding step, namely before the second grinding is carried out on the wafer, a pre-cleaning step is added to remove byproducts and prevent the formation of the complex.
And fourthly, carrying out second grinding on the wafer by using the alkaline grinding fluid, wherein the second grinding is finish grinding and is used for repairing the oxide to enable the conductive metal to protrude.
In an alternative embodiment, the second polishing in the fourth step further includes cleaning the polishing pad in the polishing apparatus and cleaning the wafer.
In an alternative embodiment, the method is suitable for 55nm technology node processing.
In one possible embodiment, referring to fig. two, after the wafer is subjected to chemical mechanical planarization, the method prevents the complex from being accumulated on the tungsten, reduces defects, and significantly improves the yield of the product.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
In conclusion, the invention avoids the complex from gathering at the contact hole, reduces the formation of defects when carrying out chemical mechanical planarization, avoids influencing the product yield, and meets the requirements of the optimized result and the yield result. . Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (9)

1. A method for optimizing CMP cleaning capability, comprising:
providing a wafer and a grinding device, wherein a contact hole is formed on the wafer and is filled with conductive metal;
secondly, performing first grinding on the substrate by using an acidic grinding fluid by using the grinding device, wherein the wafer reacts with the acidic grinding fluid to generate a byproduct;
cleaning the wafer to remove the acidic grinding fluid and byproducts on the wafer;
and fourthly, performing second grinding on the substrate by using the grinding device by using alkaline grinding fluid.
2. The method of optimizing CMP cleaning capacity of claim 1, wherein: the depth-to-width ratio of the contact hole in the first step is larger than 6: 1.
3. the method of optimizing CMP cleaning capacity of claim 1, wherein: the conductive metal forming method in the first step is a high aspect ratio process.
4. The method of optimizing CMP cleaning capacity of claim 1, wherein: the conductive metal in the first step is made of tungsten.
5. The method of optimizing CMP cleaning capacity of claim 4, wherein: and the byproduct in the second step is tungsten oxide.
6. The method of optimizing CMP cleaning capacity of claim 1, wherein: the fourth step of polishing further includes cleaning the polishing pad in the polishing apparatus and cleaning the wafer after the second polishing.
7. The method of optimizing CMP cleaning capacity of claim 1, wherein: in the second step, the first grinding is rough grinding and is used for removing the large conductive metal.
8. The method of optimizing CMP cleaning capacity of claim 1, wherein: the second grinding in the fourth step is finish grinding for projecting the conductive metal.
9. The method of optimizing CMP cleaning capacity of claim 1, wherein: the method is suitable for the 55nm technology node process.
CN202111544391.XA 2021-12-16 2021-12-16 Method for optimizing CMP cleaning capacity Pending CN114178979A (en)

Priority Applications (1)

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Application Number Priority Date Filing Date Title
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CN114178979A true CN114178979A (en) 2022-03-15

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101459124A (en) * 2007-12-13 2009-06-17 中芯国际集成电路制造(上海)有限公司 Chemical mechanical grinding method and wafer cleaning method
US20190252244A1 (en) * 2018-02-13 2019-08-15 Raytheon Company Method of manufacturing wafer level low melting temperature interconnections
CN110900455A (en) * 2018-09-17 2020-03-24 长鑫存储技术有限公司 Wafer cleaning solution, chemical mechanical polishing post-cleaning method and wafer
CN112497048A (en) * 2020-11-23 2021-03-16 华虹半导体(无锡)有限公司 Chemical mechanical polishing apparatus and method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101459124A (en) * 2007-12-13 2009-06-17 中芯国际集成电路制造(上海)有限公司 Chemical mechanical grinding method and wafer cleaning method
US20190252244A1 (en) * 2018-02-13 2019-08-15 Raytheon Company Method of manufacturing wafer level low melting temperature interconnections
CN110900455A (en) * 2018-09-17 2020-03-24 长鑫存储技术有限公司 Wafer cleaning solution, chemical mechanical polishing post-cleaning method and wafer
CN112497048A (en) * 2020-11-23 2021-03-16 华虹半导体(无锡)有限公司 Chemical mechanical polishing apparatus and method

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
中国冶金百科全书总编辑委员会《有色金属冶金》卷编辑委员会等: "《中国冶金百科全书 有色金属冶金》", 天津科学技术出版社 *

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Application publication date: 20220315

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