CN114172489A - Multi-tap delay circuit and design method thereof - Google Patents

Multi-tap delay circuit and design method thereof Download PDF

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CN114172489A
CN114172489A CN202111341544.0A CN202111341544A CN114172489A CN 114172489 A CN114172489 A CN 114172489A CN 202111341544 A CN202111341544 A CN 202111341544A CN 114172489 A CN114172489 A CN 114172489A
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coupler
tap
circuit
output end
input end
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黄晓国
陈顺阳
陈加锐
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CETC 36 Research Institute
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/0054—Attenuators
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/10—Means associated with receiver for limiting or suppressing noise or interference
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/16—Circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B17/00—Monitoring; Testing
    • H04B17/10—Monitoring; Testing of transmitters
    • H04B17/11—Monitoring; Testing of transmitters for calibration
    • H04B17/12—Monitoring; Testing of transmitters for calibration of transmit antennas, e.g. of the amplitude or phase

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  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Networks Using Active Elements (AREA)

Abstract

The invention discloses a multi-tap delay circuit and a design method thereof. Wherein the multi-tap delay circuit comprises: shunt circuit, combiner circuit and N take a percentage, and N take a percentage parallel connection is between shunt circuit and combiner circuit, and every takes a percentage to include: the first coupler, the second coupler, the first numerical control attenuator and the second numerical control attenuator; the input end of the first coupler is connected with the input end of the tap, the output end of the first coupler is connected with the input end of the first numerical control attenuator, the output end of the first numerical control attenuator is connected with the input end of the second coupler, the output end of the second coupler is connected with the output end of the tap, the coupling end of the second coupler is connected with the input end of the second numerical control attenuator, and the output end of the second numerical control attenuator is connected with the coupling end of the first coupler. The technical scheme of the invention realizes higher-precision amplitude control on the total attenuation of the circuit and provides a basis for self-interference suppression.

Description

Multi-tap delay circuit and design method thereof
Technical Field
The invention relates to the technical field of microwave circuits, in particular to a multi-tap delay circuit and a design method thereof.
Background
The rapid development of the mobile internet has exacerbated the conflict between the rapidly growing wireless access service demand and the limited spectrum resources. Meanwhile, the same-frequency full duplex theoretically can improve the spectrum utilization efficiency by one time, but self-interference suppression is required to avoid the performance deterioration of the receiver. The existing self-interference suppression technology comprises spatial isolation, radio frequency self-interference suppression and digital self-interference suppression, wherein the radio frequency self-interference suppression is widely concerned as a key link of the self-interference suppression technology.
The existing radio frequency self-interference suppression generally adopts a reconstruction and suppression mechanism, and the specific process is to precisely reconstruct a self-interference signal by adopting a radio frequency self-interference reconstruction circuit and then subtract the self-interference reconstruction signal from a receiving signal at the front end of a receiver so as to realize the radio frequency self-interference suppression. The existing radio frequency self-interference suppression can be divided into two types of radio frequency multi-tap self-interference suppression and digital auxiliary radio frequency self-interference suppression according to the position realized by the self-interference reconstruction module. Compared with digital auxiliary radio frequency self-interference suppression, the radio frequency multi-tap self-interference suppressor has many advantages, such as the capability of canceling part of strong multipath interference, and the capability of canceling noise, nonlinearity and the like caused by a transmitter.
However, the conventional radio frequency multi-tap self-interference suppression has various defects in engineering implementation, for example, the phase and amplitude precision is limited, and the delay adjustment and the amplitude adjustment of the taps adopt an analog phase shifter and an analog/digital control attenuator, so that the precision is very limited (the minimum step of the general digital control attenuator is 0.2dB), and the self-interference suppression effect is influenced.
Disclosure of Invention
The embodiment of the invention provides a multi-tap delay circuit and a design method thereof, which are used for improving the amplitude control precision of the multi-tap delay circuit.
The embodiment of the invention adopts the following technical scheme:
in one aspect, an embodiment of the present invention provides a multi-tap delay circuit, including: the circuit comprises a shunt circuit, a combiner circuit and N taps, wherein the N taps are connected in parallel between the shunt circuit and the combiner circuit, and N is a natural number greater than 1; each tap comprises: the first coupler, the second coupler, the first numerical control attenuator and the second numerical control attenuator;
the input end of the first coupler is connected with the input end of the tap, the output end of the first coupler is connected with the input end of the first numerical control attenuator, the output end of the first numerical control attenuator is connected with the input end of the second coupler, the output end of the second coupler is connected with the output end of the tap, the coupling end of the second coupler is connected with the input end of the second numerical control attenuator, and the output end of the second numerical control attenuator is connected with the coupling end of the first coupler.
On the other hand, the embodiment of the invention provides a design method of a multi-tap delay circuit, wherein the multi-tap delay circuit comprises a shunt circuit with N output ends, a combiner circuit with N input ends and N taps, the N input ends of the N taps are respectively connected with the N output ends of the shunt circuit, the N output ends of the N taps are respectively connected with the N input ends of the combiner circuit, and N is a natural number greater than 1; the design method comprises the following steps:
a first coupler, a first numerical control attenuator and a second coupler are sequentially arranged between the input end and the output end of a tap, wherein the input end of the first coupler is connected with the input end of the tap, the output end of the first coupler is connected with the input end of the first numerical control attenuator, the output end of the first numerical control attenuator is connected with the output end of the second coupler, and the output end of the second coupler is connected with the output end of the tap;
and a second digital control attenuator is arranged between the first coupler and the second coupler, the input end of the second digital control attenuator is connected with the coupling end of the second coupler, and the output end of the second digital control attenuator is connected with the coupling end of the first coupler.
The embodiment of the invention adopts at least one technical scheme which can achieve the following beneficial effects: the tap of the embodiment comprises two couplers and two numerical control attenuators, wherein the first coupler, the first numerical control attenuator and the second coupler are sequentially connected to form a main path of a signal, the second numerical control attenuator is connected between the coupling ends of the two couplers to form a negative feedback branch of the signal, and a negative feedback loop is formed by the main path and the negative feedback branch, so that when the attenuation of the circuit is adjusted, the adjustment precision can be improved by adjusting the attenuation of the second numerical control attenuator of the negative feedback branch.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
FIG. 1 is a schematic diagram of a conventional two-tap delay circuit;
FIG. 2 is a schematic diagram of a multi-tap delay circuit shown in one embodiment of the present invention;
FIG. 3 is a schematic diagram of a tap circuit shown in one embodiment of the present invention;
FIG. 4 is a diagram illustrating the results of attenuation simulation for a multi-tap delay circuit in accordance with an embodiment of the present invention;
fig. 5 is a flow chart illustrating a method of designing a multi-tap delay circuit in accordance with an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the specific embodiments of the present invention and the accompanying drawings. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The technical solutions provided by the embodiments of the present invention are described in detail below with reference to the accompanying drawings.
As shown in fig. 1, in the conventional multi-tap delay circuit, the tap is composed of a delay and an attenuator connected in series, and as described above, since the minimum step of the attenuator in the prior art is 0.2dB, the step precision is high, finer attenuation adjustment cannot be realized, and the self-interference suppression effect is affected.
In view of this problem, embodiments of the present invention provide a multi-tap delay circuit. The tap in the embodiment of the invention comprises two couplers and two numerical control attenuators, and negative feedback loop control is realized through the couplers and the numerical control attenuators, so that high-precision adjustment of amplitude is improved.
Fig. 2 is a schematic diagram of a multi-tap delay circuit according to an embodiment of the present invention, and as shown in fig. 2, the multi-tap delay circuit in this embodiment includes: the circuit comprises a shunt circuit, a combiner circuit and N taps, wherein N is a natural number larger than 1.
N take a percentage parallel connection in the shunt circuit with combine between the circuit, the shunt circuit has N output, combine the circuit and have N input, N input that N took a percentage is connected with N output of shunt circuit respectively, N output that N took a percentage is connected with N input of combining the circuit respectively.
Wherein each tap comprises: the first coupler, the second coupler, the first numerical control attenuator and the second numerical control attenuator; the first coupler, the first numerical control attenuator and the second coupler are sequentially connected between the input end and the output end of the tap, and the second numerical control attenuator is connected between the first coupler and the second coupler to form a negative feedback branch.
Specifically, the input end of the first coupler is connected with the input end of the tap, the output end of the first coupler is connected with the input end of the first numerical control attenuator, the output end of the first numerical control attenuator is connected with the input end of the second coupler, the output end of the second coupler is connected with the output end of the tap, the coupling end of the second coupler is connected with the input end of the second numerical control attenuator, and the output end of the second numerical control attenuator is connected with the coupling end of the first coupler.
Based on the multi-tap delay circuit shown in fig. 2, it can be known that: the tap of the embodiment comprises two couplers and two numerical control attenuators, wherein the first coupler, the first numerical control attenuator and the second coupler are sequentially connected to form a main path of a signal, the second numerical control attenuator is connected between the coupling ends of the two couplers to form a negative feedback branch of the signal, and a negative feedback loop is formed by the main path and the negative feedback branch, so that when the attenuation of the circuit is adjusted, the adjustment precision can be improved by adjusting the attenuation of the second numerical control attenuator of the negative feedback branch.
In this embodiment, the output power of the coupling end of the first coupler is smaller than the output power of the output end of the first coupler, and the output power of the coupling end of the second coupler is smaller than the output power of the output end of the second coupler, so as to ensure that the insertion loss of the main path of the tap is as small as possible, and avoid the problems of nonlinearity, noise rise and the like caused by adding an amplifier.
In the multi-tap delay circuit in this embodiment, each tap further includes a delay, and the delay may be various types of delays, such as a digitally controlled delay line, an analog delay line, and the like.
As shown in fig. 3, the input terminal of the delay is used as the input terminal of the tap, the output terminal of the second coupler is used as the output terminal of the tap, and the output terminal of the delay is connected to the input terminal of the first coupler. Of course, in practical applications, the input terminal of the first coupler may also be used as the input terminal of the tap, the output terminal of the delay device is used as the output terminal of the tap, and the input terminal of the delay device is connected to the output terminal of the second coupler.
In the embodiment of the invention, attenuation and delay adjustment of taps are realized by setting a delay and a negative feedback loop consisting of two couplers and two numerical control attenuators, namely, each tap in the embodiment of the invention is a reconfigurable tap with independently adjustable attenuation and delay.
Taking the attenuation adjustment of the multi-tap delay circuit as an example, the attenuation of the whole circuit is adjusted by adjusting the attenuation values of the first numerical control attenuator and the second numerical control attenuator.
Referring to fig. 3, the first coupler and the second coupler divide the energy into two parts, wherein only a small part of the energy can enter the negative feedback branch, so as to ensure that the insertion loss of the main path is as small as possible, and avoid the problems of nonlinearity, bottom noise rise and the like caused by adding an amplifier. The energy entering the negative feedback branch can also be fully returned to the main path if the negative feedback branch is ideal enough, e.g. no attenuation, no loss and the path traversed coincides with the main path.
When a second numerical control attenuator is introduced into the negative feedback branch circuit or different attenuations and delays exist between the negative feedback branch circuit and the main circuit, signals between the negative feedback branch circuit and the main circuit form vector superposition, and the attenuation quantity of the whole circuit can be expressed by the following formula:
Figure BDA0003352274390000051
wherein the content of the first and second substances,
Figure BDA0003352274390000052
and
Figure BDA0003352274390000053
respectively the attenuation of the whole circuit and the attenuation of the first numerical control attenuator and the second numerical control attenuator, and the unit is dB; ILMaster and slaveAnd ILBranch standThe insertion loss of the main path and the negative feedback branch path respectively, the insertion loss in the embodiment refers to the line loss, and the unit is dB for customization; IL1And IL2The loss of the first coupler and the loss of the second coupler on the straight-through path and the coupling path are respectively, in order to reduce the loss of energy on the main path, the power distributed to the main path is far larger than the power on the negative feedback branch path, so that the loss of the main path is far smaller than the loss of the auxiliary path, and the loss is a fixed value and the unit is dB; and theta is the phase shift of the signal returning to the first coupler path after passing through the first coupler, the first numerical control attenuator, the second coupler and the second numerical control attenuator.
Based on the above formula, it can be known that: attenuation by a second digitally controlled attenuator
Figure BDA0003352274390000061
And the phase shift theta can be dynamically and finely adjusted to adjust the total attenuation
Figure BDA0003352274390000062
The phase shift device is required for adjusting the phase shift theta, but the phase shift device has large insertion loss and does not have broadband characteristics, so in the embodiment, the negative feedback loop is designed to be a fixed delay and pass loopAttenuation of the first numerical control attenuator
Figure BDA0003352274390000063
Coarse adjustment of total attenuation is realized by the attenuation of the second numerical control attenuator
Figure BDA0003352274390000064
Fine adjustment of the total attenuation is achieved.
FIG. 4 shows the simulation results of the first and second couplers with a coupling ratio of 20:1, and the first and second digitally controlled attenuators with a minimum step of 0.25dB, while keeping the attenuation value of the first digitally controlled attenuator at 0, and the second digitally controlled attenuator at different attenuation values.
Based on the simulation results shown in fig. 4, it can be known that: the multi-tap delay circuit provided by the embodiment of the invention has the advantages that the attenuation stepping of the whole circuit can reach 0.025dB, and compared with the traditional multi-tap delay circuit, the control precision of the multi-tap delay circuit on the total attenuation of the circuit is improved by about 10 times.
In some embodiments, the splitting circuit is constructed using a plurality of splitters, and when the splitter is a splitter that splits one signal into two signals, the splitter may be one or more of a power splitter, a bridge, or a balun. Of course, in practical applications, it is also possible to select a splitter for dividing one signal into four signals to design a splitting circuit, or to design a splitting circuit by combining a splitter for dividing one signal into two signals and a splitter for dividing one signal into four signals.
Similarly, the combiner circuit is constructed by using a plurality of combiners, and when the combiner is a combiner for combining two signals into one signal, the combiner is one or more of a power divider, an electric bridge or a balun. Of course, in practical application, it is also possible to select a combiner for combining four signals into one signal, or to design a combiner circuit by combining a combiner for combining four signals into one signal and a combiner for combining two signals into one signal.
In some embodiments, the operating frequency range of the multi-tap delay circuit is set according to the common operating frequency range of the N taps, the combiner circuit and the splitter circuit, so as to ensure that each device of the multi-tap delay circuit operates in a safe frequency range.
In some embodiments, the inputs and outputs of the N taps, the combining circuit, and the splitting circuit have the same impedance characteristics, for example, the N taps, the combining circuit, and the splitting circuit are designed with 50 ohm input-to-output impedance characteristics, which ensures that the multi-tap delay circuit realizes the best performance transmission and avoids energy reflection when being integrated into the radio frequency self-interference suppressor.
In summary, the multi-tap delay circuit of the embodiment of the present invention can implement higher-precision amplitude control on the total attenuation of the circuit, and provide a basis for self-interference suppression.
The embodiment of the invention also provides a design method of the multi-tap delay circuit, which realizes the multi-tap delay circuit in the embodiment.
In the embodiment of the invention, the multi-branch circuit, the combination circuit and the N taps are connected in parallel between the branch circuit and the combination circuit, and N is a natural number greater than 1.
Fig. 5 is a flowchart of a method for designing a multi-tap delay circuit according to an embodiment of the present invention, and as shown in fig. 5, the method according to the embodiment of the present invention includes:
s510, a first coupler, a first numerical control attenuator and a second coupler are sequentially arranged between the input end and the output end of the tap, wherein the input end of the first coupler is connected with the input end of the tap, the output end of the first coupler is connected with the input end of the first numerical control attenuator, the output end of the first numerical control attenuator is connected with the output end of the second coupler, and the output end of the second coupler is connected with the output end of the tap.
And S520, arranging a second digital control attenuator between the first coupler and the second coupler, wherein the input end of the second digital control attenuator is connected with the coupling end of the second coupler, and the output end of the second digital control attenuator is connected with the coupling end of the first coupler.
In this embodiment, the method further includes setting a delay between the input end and the output end of the tap, where the delay is connected between the input end of the tap and the input end of the first coupler, or the delay is connected between the output end of the second coupler and the output end of the tap.
In this embodiment, the output power of the coupling end of the first coupler is smaller than the output power of the output end thereof, and the output power of the coupling end of the second coupler is smaller than the output power of the output end thereof.
In some embodiments, the design method further comprises: and setting the working frequency range of the multi-tap time delay circuit according to the common working frequency range of the N taps, the combiner circuit and the shunt circuit.
In some embodiments, the design method further comprises: the inputs and outputs of the N taps, the combining circuit, and the splitting circuit are set to have the same impedance characteristics.
The above are merely examples of the present invention, and are not intended to limit the present invention. Various modifications and alterations to this invention will become apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.

Claims (10)

1. A multi-tap time delay circuit comprises a shunt circuit, a combiner circuit and N taps, wherein the N taps are connected between the shunt circuit and the combiner circuit in parallel, and N is a natural number greater than 1; wherein each of said taps comprises: the first coupler, the second coupler, the first numerical control attenuator and the second numerical control attenuator;
the input end of the first coupler is connected with the input end of the tap, the output end of the first coupler is connected with the input end of the first numerical control attenuator, the output end of the first numerical control attenuator is connected with the input end of the second coupler, the output end of the second coupler is connected with the output end of the tap, the coupling end of the second coupler is connected with the input end of the second numerical control attenuator, and the output end of the second numerical control attenuator is connected with the coupling end of the first coupler.
2. The multi-tap delay circuit of claim 1,
the output power of the coupling end of the first coupler is smaller than that of the output end of the first coupler;
the output power of the coupling end of the second coupler is smaller than that of the output end of the second coupler.
3. The multi-tap delay circuit of claim 1 wherein the attenuation of each of said taps is adjusted by adjusting the attenuation values of the first digitally controlled attenuator and the second digitally controlled attenuator.
4. The multi-tap delay circuit of any one of claims 1-3, wherein each of the taps further comprises: a time delay;
the input end of the time delay is used as the input end of the tap, the output end of the second coupler is used as the output end of the tap, and the output end of the time delay is connected with the input end of the first coupler;
or, the input end of the first coupler is used as the input end of the tap, the output end of the delayer is used as the output end of the tap, and the input end of the delayer is connected with the output end of the second coupler.
5. The multi-tap delay circuit of claim 4 wherein an operating frequency range of the multi-tap delay circuit is set according to a common operating frequency range of the N taps, the combining circuit, and the splitting circuit.
6. The multi-tap delay circuit of claim 4 wherein the inputs and outputs of the N taps, the combining circuit, and the splitting circuit have the same impedance characteristics.
7. The multi-tap delay circuit of claim 4, wherein the splitting circuit is constructed using a plurality of splitters, the splitters being one or more of power splitters, bridges, or baluns.
8. The multi-tap delay circuit of claim 4, wherein the combining circuit is implemented using a plurality of combiners, and the combiners are one or more of power dividers, bridges, or baluns.
9. A design method of a multi-tap time delay circuit comprises a shunt circuit with N output ends, a combiner circuit with N input ends and N taps, wherein the N input ends of the N taps are respectively connected with the N output ends of the shunt circuit, the N output ends of the N taps are respectively connected with the N input ends of the combiner circuit, and N is a natural number more than 1; characterized in that the method comprises:
a first coupler, a first numerical control attenuator and a second coupler are sequentially arranged between the input end and the output end of the tap, wherein the input end of the first coupler is connected with the input end of the tap, the output end of the first coupler is connected with the input end of the first numerical control attenuator, the output end of the first numerical control attenuator is connected with the output end of the second coupler, and the output end of the second coupler is connected with the output end of the tap;
and a second digital control attenuator is arranged between the first coupler and the second coupler, the input end of the second digital control attenuator is connected with the coupling end of the second coupler, and the output end of the second digital control attenuator is connected with the coupling end of the first coupler.
10. The method of claim 9, further comprising:
and a time delay device is arranged between the input end and the output end of the tap, wherein the time delay device is connected between the input end of the tap and the input end of the first coupler, or the time delay device is connected between the output end of the second coupler and the output end of the tap.
CN202111341544.0A 2021-11-12 2021-11-12 Multi-tap delay circuit and design method thereof Pending CN114172489A (en)

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