CN114171589B - Semiconductor device structure - Google Patents
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- CN114171589B CN114171589B CN202210126953.7A CN202210126953A CN114171589B CN 114171589 B CN114171589 B CN 114171589B CN 202210126953 A CN202210126953 A CN 202210126953A CN 114171589 B CN114171589 B CN 114171589B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 239000011295 pitch Substances 0.000 claims abstract description 20
- 238000002955 isolation Methods 0.000 claims description 6
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 3
- HIVGXUNKSAJJDN-UHFFFAOYSA-N [Si].[P] Chemical compound [Si].[P] HIVGXUNKSAJJDN-UHFFFAOYSA-N 0.000 claims description 3
- 238000000034 method Methods 0.000 description 10
- 238000013461 design Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 238000011161 development Methods 0.000 description 2
- 230000018109 developmental process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000015654 memory Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- 229910003811 SiGeC Inorganic materials 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
Abstract
The present invention provides a semiconductor device structure, comprising: a plurality of P-type elements and a plurality of N-type elements are arranged on the same substrate, and the P-type elements and the N-type elements have different grid electrode pitches. According to the invention, the P-type element and the N-type element on the same substrate are arranged at different grid electrode distances, so that the sizes of the embedded epitaxial layers on the two sides of the grids of the P-type element and the N-type element can be adjusted, the independent adjustment of the efficiencies of the P-type element and the N-type element is realized, the function of independently adjusting the characteristics of the corresponding elements in different regions of the device is further realized, and the overall performance of the device is improved.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor device structure.
Background
The semiconductor Integrated Circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have resulted in several generations of ICs, each with smaller and more complex circuitry than the previous generation. However, these advances increase the complexity of processing and manufacturing ICs, and similar developments in IC processing and manufacturing are required in order to achieve these advances. In the course of integrated circuit development, the functional density (i.e., the number of interconnected devices per chip area) has generally increased, while the geometry (i.e., the smallest component (or line width) that can be produced using a fabrication process) has decreased. However, conventional transistor layout designs have not been optimized for high speed IC applications, where parasitic capacitance and/or resistance can significantly degrade device performance. For example, in a semiconductor process, N-type devices and P-type devices are designed to have the same line width (pitch) to make different applications and circuit designs, and although simple process can be achieved, the problem still remains that the performance of the N-type devices and the P-type devices cannot be adjusted independently.
Disclosure of Invention
The invention aims to provide a semiconductor device structure, which is used for realizing the independent adjustment of the efficiencies of a P-type element and an N-type element and improving the overall performance of a device.
To achieve the above object, the present invention provides a semiconductor device structure comprising: a plurality of P-type elements and a plurality of N-type elements are arranged on the same substrate, and the P-type elements and the N-type elements have different grid electrode pitches.
Optionally, the substrate includes a plurality of active regions extending in a first direction, the gates of the P-type elements and the gates of the N-type elements extend in a second direction and intersect the active regions, and the gate of at least one P-type element intersects two adjacent active regions, and/or the gate of at least one N-type element intersects two adjacent active regions.
Optionally, the P-type element is a PMOS, and the N-type element is an NMOS.
Optionally, the P-type element and the N-type element are arranged at intervals.
Optionally, the substrate further includes an N-type deep well in the active region.
Optionally, a first embedded epitaxial layer is formed on the substrate on two sides of the gate of the P-type element, and a second embedded epitaxial layer is formed on the substrate on two sides of the gate of the N-type element.
Optionally, the first embedded epitaxial layer includes a germanium-silicon epitaxial layer, and the second embedded epitaxial layer includes a phosphorus-silicon epitaxial layer.
Optionally, the first embedded epitaxial layer and the second embedded epitaxial layer have different sizes.
Optionally, an isolation structure is disposed between the P-type element and the N-type element.
Optionally, the sidewalls of the gates of the P-type element and the N-type element are both provided with a sidewall structure.
In summary, the semiconductor device structure provided by the present invention includes: a plurality of P-type elements and a plurality of N-type elements are arranged on the same substrate, and the P-type elements and the N-type elements have different grid electrode pitches. According to the invention, the P-type element and the N-type element on the same substrate are arranged at different grid electrode distances, so that the sizes of the embedded epitaxial layers on the two sides of the grids of the P-type element and the N-type element can be adjusted, the independent adjustment of the efficiencies of the P-type element and the N-type element is realized, the function of independently adjusting the characteristics of the corresponding elements in different regions of the device is further realized, and the overall performance of the device is improved.
Drawings
FIG. 1 is a schematic diagram of a semiconductor device structure;
fig. 2 is a top view of a portion of the semiconductor device shown in fig. 1 in dashed outline;
fig. 3 is a partial schematic view of a semiconductor device structure according to an embodiment of the present invention;
fig. 4 is a schematic cross-sectional view of a portion of a semiconductor device structure according to an embodiment of the invention.
Wherein the reference numerals are:
100-a substrate; 101-N type deep well; 102-an active region; 103-an isolation structure; 110-P type element grid; a 120-N type element gate; 111-a first embedded epitaxial layer; 121-a second embedded epitaxial layer; 130-side wall structure.
Detailed Description
The structure of the semiconductor device of the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description and drawings, it being understood, however, that the concepts of the present invention may be embodied in many different forms and should not be construed as limited to the specific embodiments set forth herein. The drawings are in simplified form and are not to scale, but are provided for convenience and clarity in describing embodiments of the invention.
The terms "first," "second," and the like in the description are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other sequences than described or illustrated herein. Similarly, if the method described herein comprises a series of steps, the order in which these steps are presented herein is not necessarily the only order in which these steps may be performed, and some of the described steps may be omitted and/or some other steps not described herein may be added to the method. Although elements in one drawing may be readily identified as such in other drawings, the present disclosure does not identify each element as being identical to each other in every drawing for clarity of description.
Fig. 1 is a schematic diagram of a semiconductor device structure, and fig. 2 is a top view of a portion of a semiconductor element in a dashed-line box in fig. 1. As shown in fig. 1 and 2, in a semiconductor process, both N-type devices (NMOS) and P-type devices (PMOS) are designed to have the same line width (pitch), that is, the gate pitch D1 of the N-type devices (NMOS) and the gate pitch D2 of the P-type devices (PMOS) are equal to each other, so as to make different applications and circuit designs.
To solve the above problem, the present embodiment provides a semiconductor device structure, including: a plurality of P-type elements and a plurality of N-type elements are arranged on the same substrate, and the P-type elements and the N-type elements have different grid electrode pitches. In this embodiment, the P-type element and the N-type element on the same substrate are set to have different gate pitches, so that the sizes of the embedded epitaxial layers on the two sides of the gates of the P-type element and the N-type element are adjustable, the performance of the P-type element and the N-type element is independently adjusted, the characteristics of the corresponding elements are adjusted according to different regions of the device, and the overall performance of the device is improved.
Fig. 3 is a partial schematic view of a semiconductor device structure provided in this embodiment, and fig. 4 is a partial cross-sectional schematic view of the semiconductor device structure provided in this embodiment. As shown in fig. 3 and 4, the semiconductor device structure includes: a plurality of P-type elements and a plurality of N-type elements are arranged on the same substrate, and the P-type elements and the N-type elements have different grid electrode pitches. Specifically, the P-type element is a PMOS, the N-type element is an NMOS, and the P-type element and the N-type element are arranged at intervals. The gate pitches of the P-type element and the N-type element are different, so that the sizes of the embedded epitaxial layers arranged on the two sides of the gates of the P-type element and the N-type element can be different, that is, the sizes of the embedded epitaxial layers on the two sides of the gates of the corresponding P-type element or the N-type element can be adjusted according to actual needs, so that corresponding changes of performances such as parasitic capacitance or resistance can be realized, further, the effect of independently adjusting the P-type element or the N-type element can be realized, and the performance of the whole device can be enhanced.
Specifically, the substrate comprises a plurality of active regions extending in a first direction, the active regions of the P-type elements and the active regions of the N-type elements are arranged in parallel and at intervals, the gates of the P-type elements and the gates of the N-type elements extend in a second direction and intersect with the active regions, the gate of at least one P-type element intersects with two adjacent active regions, and/or the gate of at least one N-type element intersects with two adjacent active regions.
As shown in fig. 3, the active area (AA 1) of the P-type device (PMOS) and the active area (AA 2) of the N-type device (NMOS) extend in a first direction (e.g., X direction) and are disposed in parallel and spaced apart, the gates (ploy 1, ploy 2) of the P-type device (PMOS) extend in a second direction (e.g., Y direction) and intersect the active area (AA 1) of the P-type device (PMOS), and the gates (ploy 1, ploy 3) of the N-type device (NMOS) extend in a second direction (e.g., Y direction) and intersect the active area (AA 2) of the N-type device (NMOS), wherein the gate (ploy 1) of the P-type device (PMOS) and the adjacent active area (AA 1) of the P-type device (PMOS) and the active area (AA 6, 48325) of the N-type device (NMOS) share the gate elements (P) and the gate elements (NMOS). In other embodiments of the present invention, the gate may be disposed in other manners, such as the intersection of the P-type device gate (ploy 2) and the active region (AA 1) of the adjacent P-type device (PMOS) and the active region (AA 2) of the N-type device (NMOS).
It should be noted that, a plurality of P-type devices and a plurality of N-type devices are disposed on the substrate, fig. 3 only shows a minimum layout design unit of the P-type devices and the N-type devices, and fig. 1 can be referred to for layout design of the plurality of P-type devices and the plurality of N-type devices on the substrate, the difference between the semiconductor device structure provided by this embodiment and fig. 1 is that gate pitches of the P-type devices and the N-type devices are adjusted correspondingly as shown in fig. 3, so that the gate pitches of the P-type devices and the N-type devices are not equal, and the adjustment here is also adjusted within a range of corresponding process requirements. In addition, the P-type and N-type devices herein may be other types of P-type or N-type devices besides the above-mentioned PMOS and NMOS, such as radio frequency devices (RF devices), Ring oscillators (Ring oscillators), Static Random Access Memories (SRAMs), Complementary Metal Oxide Semiconductors (CMOS), flash memory devices (NOR, NAND), and the like.
Furthermore, a first embedded epitaxial layer is formed on the substrate on two sides of the gate of the P-type element, and a second embedded epitaxial layer is formed on the substrate on two sides of the gate of the N-type element. The P-type element and the N-type element have different gate pitches, and the sizes of the first embedded epitaxial layer and the second embedded epitaxial layer can be adjusted correspondingly according to needs, for example, the sizes of the first embedded epitaxial layer and the second embedded epitaxial layer can be set differently.
Specifically, as shown in fig. 4, a P-type element (PMOS) and an N-type element (NMOS) are formed on the substrate 100 at intervals. The substrate 100 is made of, for example, Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III/V compound semiconductors, and the substrate 100 may be a multilayer structure or the like made of these semiconductor materials, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-stacked germanium (S-SiGeOI), silicon-on-insulator-germanium (SiGeOI), germanium-on-insulator (GeO), or the like. An N-type deep well (DNW) 102 is formed in an active region 101 of the substrate 100, and a dopant of the P-type deep well 102 is an N-type dopant such as arsenic ion or phosphorous ion. An isolation structure 103 is disposed between the P-type element (PMOS) and the N-type element (NMOS), and the isolation structure 103 is, for example, a Shallow Trench Isolation (STI) structure.
With continued reference to fig. 4, a first embedded epitaxial layer 111 is formed on the substrate on both sides of the gate 110 of the P-type element (PMOS), and a second embedded epitaxial layer 121 is formed on the substrate on both sides of the gate 120 of the N-type element (NMOS). The first embedded epitaxial layer 111 includes a silicon germanium epitaxial layer (SiGe), and the second embedded epitaxial layer 121 includes a silicon phosphorus epitaxial layer (SiP). The first embedded epitaxial layer 111 and the second embedded epitaxial layer 121 are usually formed after the gate of the device is formed, and then a groove is formed on both sides of the gate in a self-aligned manner, and then an epitaxial process is adopted to form an embedded epitaxial layer in the groove in a self-aligned manner. The gate 110 of the P-type element (PMOS) and the gate 120 of the N-type element (NMOS) comprise a gate oxide layer, a polysilicon layer, a hard mask layer and a dielectric layer sequentially disposed on the substrate. The sidewalls of the gate 110 of the P-type element and the gate 120 of the N-type element are both provided with a sidewall structure 130, and the sidewall structure 130 is, for example, an ONO stacked structure.
Since the gate Pitch of the P-type device (PMOS) and the gate Pitch of the N-type device (NMOS) are not equal, as shown in fig. 4, the gate Pitch between the gate 110 of the P-type device (PMOS) and the gate 120 of the N-type device (NMOS) is different, i.e., Pitch1, Pitch2, and Pitch3 are not equal, and further, the size of the first embedded epitaxial layer 111 on both sides of the gate of the P-type device (PMOS) and the size of the second embedded epitaxial layer 121 on both sides of the gate 120 of the N-type device (NMOS) can be set differently, the size of the embedded epitaxial layer (EPI) is set differently, and the performance (e.g., resistance) of the corresponding device is also correspondingly different, i.e., the gate Pitch of the P-type device and the gate of the N-type device is changed, so that the size of the embedded epitaxial layers on both sides of the gates of the P-type device and the N-type device is adjustable, and further, by adjusting the size of the embedded epitaxial layers on both sides of the gates of the P-type device and the N-type device, the performance of the corresponding P-type and N-type devices is adjusted individually. For the whole device comprising a plurality of N-type elements and P-type elements, the performances of the corresponding P-type elements and N-type elements can be independently adjusted according to different regions, and the performance of the whole device is improved.
The semiconductor device structure provided by the embodiment can be applied to Static Random Access Memories (SRAMs), input/output devices (I/Os), Logic devices (Logic devices), Embedded devices (Embedded devices) and the like, the distances between the gates of the P-type elements and the N-type elements in the devices are set to be different, the size of the Embedded epitaxial layers on two sides of the gates is variable, the P-type elements and the N-type elements are independently adjusted, and the overall performance of the devices is improved.
In summary, the present invention provides a semiconductor device structure, including: a plurality of P-type elements and a plurality of N-type elements are arranged on the same substrate, and the P-type elements and the N-type elements have different grid electrode pitches. According to the invention, the P-type element and the N-type element on the same substrate are arranged at different grid electrode distances, so that the sizes of the embedded epitaxial layers on the two sides of the grids of the P-type element and the N-type element can be adjusted, the independent adjustment of the efficiencies of the P-type element and the N-type element is realized, the function of independently adjusting the characteristics of the corresponding elements in different regions of the device is further realized, and the overall performance of the device is improved.
It should be noted that, in the present specification, all the embodiments are described in a related manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the structural embodiment, since it is substantially similar to the method embodiment, the description is relatively simple, and for the relevant points, reference may be made to the partial description of the method embodiment.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (9)
1. A semiconductor device structure, comprising: arranging a plurality of P-type elements and a plurality of N-type elements on the same substrate, wherein the P-type elements and the N-type elements have different grid pitches; the substrate comprises a plurality of active regions extending in a first direction, the gates of the P-type elements and the gates of the N-type elements extend in a second direction and intersect the active regions, and the gate of at least one P-type element intersects two adjacent active regions, and/or the gate of at least one N-type element intersects two adjacent active regions.
2. The semiconductor device structure of claim 1, wherein the P-type element is a PMOS and the N-type element is an NMOS.
3. The semiconductor device structure of claim 2, wherein the P-type element and the N-type element are spaced apart.
4. The semiconductor device structure of claim 3, wherein the substrate further comprises an N-type deep well within the active region.
5. The semiconductor device structure of claim 4, wherein a first embedded epitaxial layer is formed on the substrate on both sides of the gate of the P-type element, and a second embedded epitaxial layer is formed on the substrate on both sides of the gate of the N-type element.
6. The semiconductor device structure of claim 5, wherein the first embedded epitaxial layer comprises a germanium-silicon epitaxial layer and the second embedded epitaxial layer comprises a phosphorus-silicon epitaxial layer.
7. The semiconductor device structure of claim 5, wherein the first embedded epitaxial layer and the second embedded epitaxial layer are not the same size.
8. The semiconductor device structure of claim 1, wherein an isolation structure is disposed between the P-type element and the N-type element.
9. The semiconductor device structure of claim 1, wherein sidewalls of the gate of the P-type element and the gate of the N-type element are both provided with a sidewall structure.
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| TWI236130B (en) * | 2004-09-30 | 2005-07-11 | Winbond Electronics Corp | I/O cell and ESD protection circuit |
| US8324940B2 (en) * | 2010-04-13 | 2012-12-04 | International Business Machines Corporation | Nanowire circuits in matched devices |
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