CN114171547A

CN114171547A - Micro LED transferring method and Micro LED panel

Info

Publication number: CN114171547A
Application number: CN202111466588.6A
Authority: CN
Inventors: 钟明达
Original assignee: Ziminsheng Photoelectric Technology Suzhou Co ltd
Current assignee: Ziminsheng Photoelectric Technology Suzhou Co ltd
Priority date: 2021-12-03
Filing date: 2021-12-03
Publication date: 2022-03-11

Abstract

The invention provides a Micro LED transfer method and a Micro LED panel. The Micro LED transfer method can comprise the following steps: an electrode array is arranged on the first substrate; forming a conductive layer over a portion of the electrode; depositing an isolation layer on the first substrate and exposing the surface of the conductive layer; depositing a buffer layer on the isolation layer, and forming a through hole at a part corresponding to the conductive layer, wherein the width of the through hole is greater than that of the conductive layer; depositing a first bonding layer on the surface of the conductive layer; a plurality of Micro LED chips and a second bonding layer are sequentially arranged on one side surface of the second substrate, and the second bonding layer is in bonding connection with the first bonding layer; the width of the through hole is larger than or equal to that of the Micro LED chip, and the height of the through hole is larger than or equal to that of a bonding layer formed by the first bonding layer and the second bonding layer.

Description

Micro LED transferring method and Micro LED panel

Technical Field

The invention relates to the technical field of Micro light-emitting diodes, in particular to a mass transfer method of a Micro light-emitting diode (Micro LED).

Background

Compared with Light Emitting Diodes (LEDs), Micro LEDs are also called mleds, muleds or Micro LEDs, which are novel self-luminous display technologies, and the size of the LEDs reaches the micron level. Micro LED display has the characteristics of self luminescence, high efficiency, low power consumption, high stability and the like, is an important choice of a new generation of mainstream display technology, and has the potential of replacing the prior art in numerous fields. Currently, one of the major and potential markets for Micro LEDs is the high resolution consumer electronics market for homes.

According to different application scenes of different types of product terminals, the Micro LED can be directly used for manufacturing a high-resolution display screen on a substrate or a substrate of Si, GaN, Sapphire and the like for products of small-size wearable display (such as smart bracelets), VR/AR near-eye display and the like, and the Micro LED chip can be assembled on a substrate with a larger size and a logic circuit in a mass transfer mode after being manufactured on the substrate, so that the requirements of application scenes of large-size display screens of mobile phones, tablet computers, televisions and the like are met. Commercial application or mass production of Micro LEDs presents many problems to be solved, and mass transfer technology is one of the most critical.

The huge transfer means that micron-sized LED crystal grains need to be transferred to a driving circuit substrate after the chip is manufactured, the transfer quantity of TV screens and mobile phone screens is quite large, and the tolerance of display products to pixel errors is extremely low. At present, the mainstream Micro LED bulk transfer technology mainly includes an electrostatic force adsorption transfer mode, a fluid assembly transfer technology, an elastomeric stamp transfer technology, a selective release transfer technology (such as laser transfer and laser assisted transfer), a roller transfer technology, and the like. The transfer efficiency, transfer precision, transfer success rate, bonding technology and the like in the mass transfer process deeply affect the manufacturing cost, production efficiency, production yield, popularization rate and popularization time of the Micro LED display screen and the like. In the Micro LED bulk transfer bonding technology, metal quantity evaluation during metal bonding is adopted, and the difference from the actual metal quantity evaluation is large or bonding alignment deviation during bonding is too large, so that a metal bonding layer overflows the hole range for bonding, and poor bonding phenomena such as abnormal bonding are caused.

Disclosure of Invention

The invention provides a Micro LED transfer method and a corresponding Micro LED panel, aiming at solving the problem of improving the transfer success rate in Micro LED bulk transfer.

To achieve at least one of the above advantages or other advantages, an embodiment of the present invention provides a Micro LED transferring method, which includes at least the following steps:

providing a first substrate, wherein an electrode array is arranged on the first substrate;

forming a conductive layer on a portion of the electrodes in the first substrate;

depositing an isolation layer on the first substrate and exposing the surface of the conductive layer;

depositing a buffer layer on the isolation layer, wherein at least part of the buffer layer corresponding to the conductive layer is provided with a through hole, and the width of the through hole is larger than that of the conductive layer;

depositing a first bonding layer on the surface of the conductive layer; and

providing a second substrate, wherein a plurality of Micro LED chips are arranged on one side surface of the second substrate, a second bonding layer is arranged on one side surface, away from the second substrate, of each Micro LED chip, and the second bonding layer is in bonding connection with the first bonding layer;

the width of the through hole is larger than or equal to that of the Micro LED chip, and the height of the through hole is larger than or equal to that of a bonding layer formed after the first bonding layer is bonded with the second bonding layer.

In some embodiments, the forming of the isolation layer, the buffer layer and the first bonding layer on the first substrate includes:

depositing a planar isolation layer on the first substrate, the isolation layer completely covering the conductive layer;

thinning the thickness of the isolation layer by adopting a Chemical Mechanical Polishing (CMP) method until the surface of the conductive layer is exposed;

depositing buffer layers on the surfaces of the isolation layer and the conducting layer, wherein at least part of the buffer layers corresponding to the conducting layer is provided with through holes, the surface of the conducting layer is exposed, and the width of each through hole is larger than that of the conducting layer;

depositing the first bonding layer on the surface of the conducting layer, wherein the width of the first bonding layer is larger than or equal to that of the conducting layer, and the width of the first bonding layer is smaller than or equal to that of the through hole.

Further, in some embodiments, the thickness of the buffer layer is greater than 1 μm, which ensures that the molten metal flowing during the metal bonding of the first bonding layer and the second bonding layer can be completely retained in the predetermined holes without overflow. The buffer layer is made of elastic organic photoresist materials, so that enough buffer space can be ensured during eutectic bonding, and the substrate or the LED device is prevented from being damaged due to pressure in the bonding process.

depositing a flat isolation layer on the first substrate, wherein the isolation layer completely covers the conductive layer;

forming an opening in at least part of the isolation layer corresponding to the conductive layer, exposing the surface of the conductive layer, wherein the width of the opening is less than or equal to the width of the conductive layer;

depositing the first bonding layer on the surface of the conductive layer, wherein the width of the first bonding layer is less than or equal to the width of the conductive layer and less than or equal to the width of the opening;

depositing buffer layers on the isolation layer and the first bonding layer, and forming through holes at positions of the buffer layers corresponding to the first bonding layer and the conducting layer, wherein the width of each through hole is larger than that of the conducting layer.

Further, in some embodiments, the isolation layer is an organic photoresist material having elasticity; the buffer layer is an organic photoresist layer.

In some embodiments, the first substrate is at least one of a driving substrate, a glass substrate, a Si substrate, a PI substrate, and a display backplane.

In some embodiments, the conductive layer is one or more of gold, tin, nickel, titanium, aluminum, silver, indium, or an alloy of metallic materials.

In some embodiments, the buffer layer is one of an insulating layer, an organic photoresist layer, and a passivation layer.

In some embodiments, the first bonding layer and the second bonding layer are respectively one or more of gold, tin, nickel, titanium, aluminum, silver, indium or an alloy composed of metal materials.

In some embodiments, the bonding method of the first bonding layer and the second bonding layer is one or more of alloy eutectic bonding, diffusion bonding, and transient liquid phase bonding.

In some embodiments, the second bonding layer and the first bonding layer are bonded by melting metals in the second bonding layer and the first bonding layer by using a laser heating method, and continuously pressing to form a metal bonding layer.

To achieve at least one of the advantages or other advantages, an embodiment of the present invention provides a Micro LED panel, which can be manufactured by the Micro LED transfer method as described above. The Micro LED panel at least comprises:

the electrode array is arranged on the first substrate;

the plurality of conducting layers are arranged on the first substrate and cover at least part of the electrode array;

the isolation layer is arranged on the first substrate and isolates the plurality of conductive layers;

the buffer layer is arranged on the isolation layer, and a through hole is formed in the buffer layer corresponding to the conductive layer; and

a bonding layer at least partially within the through hole, the Micro LED chip connected with the conductive layer via the bonding layer;

the width of the through hole is larger than or equal to that of the Micro LED chip, and the height or the thickness of the through hole is larger than or equal to that of the bonding layer.

In some embodiments, the isolation layer is an insulating layer, and the thickness of the isolation layer is equal to or greater than the thickness of the conductive layer.

In some embodiments, the width of the bonding layer is less than and/or greater than the width of the conductive layer.

Compared with the prior art, the Micro LED transfer method and the Micro LED panel manufactured by the method have the following advantages that:

1. when the Micro LED chip is bonded in the transfer process, the corresponding bonding layer can be attached accurately for bonding, and the bonded alloy metal of the bonding layer cannot overflow the hole and hole area limited in the bonding process to cause the waste of the alloy metal of the bonding layer.

2. After bonding, the Micro LED chip is at least partially positioned in the hole and hole area defined during bonding, so that the bonding of the Micro LED chip is firmer. Meanwhile, the alloy metal consumption required by the bonding layer during bonding can be effectively controlled according to actual requirements, and the manufacturing cost is saved or controlled.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without creative efforts.

FIG. 1 is a schematic flow chart of a Micro LED transfer method according to the present invention;

FIG. 2 is a schematic flow chart of a first embodiment of the Micro LED transfer method shown in FIG. 1;

fig. 3a to 3h are schematic process diagrams corresponding to the flow chart shown in fig. 2, and fig. 3h is a schematic cross-sectional diagram of a first embodiment of a Micro LED panel according to the present invention;

FIG. 4 is a schematic flow chart of a second embodiment of the Micro LED transfer method shown in FIG. 1; and

fig. 5a to 5h are schematic process diagrams corresponding to the flow shown in fig. 4, and fig. 5h is a schematic cross-sectional diagram of a second embodiment of a Micro LED panel according to the present invention.

Reference numerals:

1-Micro LED Panel 10-first substrate 11-electrode

20-conductive layer 30-isolation layer 31-openings

40-buffer layer 41-through hole 50-bonding layer

51-first bonding layer 52-second bonding layer 60-Micro LED chip

70-second substrate H1, H2-height L1, L2, L3, L4, L5-width

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In the description of the present invention, it is to be understood that the terms "center", "lateral", "up", "down", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, indicate orientations and positional relationships based on those shown in the drawings, are only for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or component in question must have a particular orientation or be constructed and operated in a particular orientation, and therefore, should not be taken as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless otherwise specified. In addition, the term "comprises" and any variations thereof mean "including at least".

In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integrally formed connection; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, and the two components can be communicated with each other. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Referring to fig. 1, fig. 1 is a schematic flow chart illustrating a Micro LED transfer method according to the present invention. To achieve at least one of the advantages or other advantages, an embodiment of the invention provides a Micro LED transferring method, which may include at least the following steps:

step (S01): a first substrate is provided, and an electrode array is arranged on the first substrate. A surface of at least some of the electrodes in the electrode arrays is flush with a surface of the first substrate. It is understood that a surface of the partial electrodes is exposed to the same side of the first substrate.

The first substrate may be a driving substrate, a glass substrate, a Si substrate, a PI substrate, a display backplane, or the like, but is not limited thereto. In some embodiments, the first substrate may also be a self-supporting substrate, an intermediate substrate, a carrier substrate, or the like.

Here, the first substrate is explained and illustrated as a Si-driven backplate. The Si driving backboard is provided with at least three electrode arrays, wherein one surface of each electrode is exposed to one side of the Si driving backboard.

Step (S02): and forming a conductive metal layer on the first substrate, and forming a conductive layer on part of the electrodes. Further, the conductive layer is formed on a surface of the electrode on a side exposed to the first substrate. The material of the conducting layer can be one or more of gold, tin, nickel, titanium, aluminum, silver and indium, or an alloy composed of metal materials. That is, the conductive layer may be a pure metal or a metal alloy.

Specifically, a photoresist is coated on a side of the Si-driven backplate where a surface of the electrode is exposed. And exposing and developing to form a conductive metal pattern on the exposed electrode surface. A conductive metal layer is deposited on the photoresist. The photoresist is removed and the conductive metal layer is removed in unnecessary areas at the same time, except that the conductive metal is formed on the exposed electrode surface. When at least three electrode arrays are arranged on the Si driving backboard, the conducting layer is correspondingly formed on one surface of two electrodes.

Step (S03): and depositing an isolating layer on the conductive metal layer to isolate and protect the formed conductive layers. At the same time, the surfaces of the respective conductive layers are exposed in the isolation layer. The isolation layer may be an insulating layer, a buffer insulating layer, or the like.

Step (S04): depositing a buffer layer on the isolation layer. The buffer layer may be one of an insulating layer, an organic photoresist layer, and a passivation layer. The buffer layer is provided with through holes at least corresponding to the conductive layers. The through hole can be used as a bonding moving space or a moving area required by Micro LED chip transfer bonding. The width of each via is greater than the width of each conductive layer. So set up, effectual electric connection can be realized with the conducting layer through the bonding layer after the bonding of Micro LED chip.

Step (S05): and depositing a first bonding layer on the surface of the conductive layer. The first bonding layer may serve as a connection layer of the first substrate in Micro LED chip transfer bonding. The material of the first bonding layer can be one or more of gold, tin, nickel, titanium, aluminum, silver and indium or an alloy composed of metal materials.

Step (S06): and providing a second substrate, wherein a plurality of Micro LED chips are arranged on one side surface of the second substrate. The Micro LED chips are arranged on the second substrate in an array mode. The width of the through hole is larger than or equal to that of the Micro LED chip. And each Micro LED chip is provided with a second bonding layer on the surface of one side, far away from the second substrate. The material of the second bonding layer can be one or more of gold, tin, nickel, titanium, aluminum, silver and indium or an alloy composed of metal materials.

When the Micro LED chips are transferred to the first substrate, the second bonding layer is in bonding connection with the first bonding layer. The height of the through hole is larger than or equal to that of a bonding layer formed after the first bonding layer is bonded with the second bonding layer. The bonding method of the first bonding layer and the second bonding layer can be one or more of alloy eutectic bonding, diffusion bonding and transient liquid phase bonding.

In one embodiment, the second substrate may be an original substrate, a growth substrate, a substrate, or the like. A plurality of Micro LED chips can be reversely arranged on the second substrate in an array mode.

Referring to fig. 1 and fig. 3a to 3h, fig. 2 is a schematic flowchart of a first embodiment of the Micro LED transfer method shown in fig. 1, and fig. 3a to 3h are schematic process diagrams corresponding to the flowchart shown in fig. 2. The specific process steps of the first embodiment of the Micro LED transfer method illustrated in these figures are described below.

Referring to fig. 3a, referring to step (S01) of fig. 1, a first substrate 10 having an array of electrodes 11 thereon is provided. The first substrate 10 is shown as a Si-driven backplane. The Si-driven backplate 10 is provided with at least three arrays of electrodes 11, wherein the upper surfaces of two electrodes 11 are exposed to the same side of the Si-driven backplate 10, in the example shown the upper surface of the first substrate 10.

Referring to fig. 3b, referring to step (S02) of fig. 1, a conductive metal layer is formed on the first substrate 10, and a conductive layer 20 is formed on a portion of the electrode 11. Further, the conductive layer 20 is formed on a surface of the electrode 11 on a side exposed to the first substrate 10.

Specifically, a photoresist layer is coated on the upper surface of the Si-driven backplate 10 shown in fig. 3a, and the photoresist layer covers the upper surface of the central portion of the electrode 11 in the Si-driven backplate 10. Exposing and developing the photoresist layer to form a conductive metal pattern on the upper surface of the partial electrode 11. Then, a conductive metal layer is deposited on the photoresist layer. It is understood that the conductive metal layer overlies the photoresist layer and the conductive metal pattern. The photoresist layer is removed and at the same time the conductive metal layer in the unnecessary area is removed, and finally the conductive layer 20 is formed only on the upper surface of the partial electrode 11. As shown in fig. 3b, at least two electrodes 11 in the three electrode 11 arrays on the Si driving backplate 10 are correspondingly formed with a conductive layer 20 on the upper surface. The conductive layer 20 is a pure metal or an alloy having conductive properties.

As shown in fig. 3c, referring to the steps of fig. 1 (S03) and fig. 2 (S11), a planar isolation layer 30 is deposited on the Si-driven backplate 10. The isolation layer 30 completely covers the respective conductive layers 20 formed in the previous steps and other areas of the upper surface of the Si driving backplate 10. The isolation layer 30 can isolate the conductive layers 20 and provide conductive protection.

Referring to fig. 3d, in step S12 of fig. 2, the isolation layer 30 is thinned by Chemical Mechanical Polishing (CMP) until the top surface of each conductive layer 20 is exposed. In the illustrated example, the height or thickness of the conductive layer 20 is equal to the height or thickness of the isolation layer 30. Thus, it is beneficial to perform subsequent processing operations on the upper surface of the conductive layer 20 and the upper surface of the isolation layer 30.

Referring to fig. 3e, referring to step S04 in fig. 1 and step S13 in fig. 2, a buffer layer 40 is deposited on the surfaces of the isolation layer 30 and the conductive layers 20. The buffer layer 40 has through holes 41 at least corresponding to the conductive layers 20 and exposes the upper surface of the conductive layer 20. The width of the via hole 41 is larger than the width of the conductive layer 20.

Specifically, a photoresist layer is coated on the buffer layer 40. Exposing the photoresist layer to light, forming a via hole 41 in the buffer layer 40 corresponding to the conductive layers 20, and removing the photoresist layer. The corresponding through hole 41 on the upper surface of the conductive layer 20 can be used as a bonding active space or an active area required when the Micro LED chip is subjected to transfer bonding.

In the illustrated example, the isolation layer 30 may be an insulating layer. The side space of the conductive layer 20 is covered and protected by the isolation layer 30, so that the range of the buffer layer 40 for forming the through hole 41 can be enlarged, and the variation space or the activity space of the Micro LED chip in the bonding process can be enlarged.

In the illustration, the buffer layer 40 is an organic photoresist material with elasticity, which can ensure a sufficient buffer space during eutectic bonding and prevent the substrate or the LED device from being damaged due to pressure during the bonding process. The thickness of the buffer layer 40 is greater than 1 μm, which ensures that the molten metal flowing during the metal bonding between the first bonding layer and the second bonding layer can be completely retained in the predetermined holes without overflow.

As shown in fig. 3f, referring to step S05 in fig. 1 and step S14 in fig. 2, a first bonding layer 51 is deposited and formed on the upper surface of the conductive layer 20. Specifically, a photoresist layer is coated on the buffer layer 40 and in the via 41. A metal pattern is formed on the Si-driven backplate 10 at the through hole 41 by exposing and developing above the photoresist layer. And depositing a metal film layer on the photoresist layer and the metal pattern. The photoresist layer is removed, and a first bonding layer 51 is formed on the metal pattern in the through hole 41. It is understood that the first bonding layer 51 is a metal film layer at this time. The first bonding layer 51 is an alloy metal layer. The first bonding layer 51 may be one of gold, tin, nickel, titanium, aluminum, silver, indium, or an alloy of metal materials. In this process, the width of the first bonding layer 51 is smaller than or equal to the width of the through hole 41, and the width of the first bonding layer 51 is larger than or equal to the width of the conductive layer 20, so as to ensure that the subsequent Micro LED chip and the conductive layer 20 have a sufficient electrical connection surface to obtain a good conductive performance.

In the illustrated embodiment, the first bonding layer 51 is located entirely within the via 41 in the buffer layer 40. The width L1 of the first bonding layer 51 is greater than the width L2 of the conductive layer 20, and the width L1 of the first bonding layer 51 is less than or equal to the width L3 of the via 41. But is not limited thereto. In practice, the width L1 of the first bonding layer 51 may be smaller than the width L2 of the conductive layer 20, depending on the kind, model, etc. of the Micro LED chip. The Micro LED chip can be electrically connected to the conductive layer 20 via the first bonding layer 51.

Referring to fig. 3g, referring to step (S06) of fig. 1, a second substrate 70 is provided, and a plurality of Micro LED chips 60 are disposed on a surface of the second substrate 70. The Micro LED chips 60 are arranged in an array on the second substrate 70. The Micro LED chip 60 is shown flip-chip mounted on the second substrate 70. A second bonding layer 52 is disposed on a surface of each Micro LED chip 60 on a side away from the second substrate 70. The material of the second bonding layer 52 may be one of gold, tin, nickel, titanium, aluminum, silver, and indium, or an alloy of metal materials. The thickness of the second bonding layer 52 is related to the space required for curing of the bonding layer 50 after bonding, and the thickness of the buffer layer 40. The width of the second bonding layer 52 is smaller than or equal to the width of the Micro LED chip 60, so as to ensure that the Micro LED chip 60 is electrically connected to the first substrate 10 through the second bonding layer 52. The width of the second bonding layer 52 in the illustrated example is less than the width of the Micro LED chip 60.

When the Micro LED chips 60 are transferred to the first substrate 10, the second bonding layer 52 on the second substrate 70 is aligned and attached to the first bonding layer 51 on the first substrate 10. The metal or alloy on the first bonding layer 51 and the second bonding layer 52 is melted by a laser heating method. Meanwhile, the other side of the second substrate 70 (the side far from the Micro LED chip 60 in the figure) is continuously pressed, so that the first bonding layer 51 and the second bonding layer 52 complete eutectic bonding to form a bonding layer 50. Then, the second substrate 70 is removed, thereby obtaining the Micro LED panel 1, as shown in fig. 3 h. In the illustrated example, the bonding layer 50 is located entirely within the via 41 in the buffer layer 40.

The width L3 of the through hole 41 in the buffer layer 40 is greater than or equal to the width L4 of the Micro LED chip 60, which is beneficial to the movement of the Micro LED chip 60 in the through hole 41 and the alignment and attachment with the conductive layer 20 in the transfer bonding process of the Micro LED chip 60.

In the illustrated example, the height H1 of the through hole 41 is greater than the height H2 of the bonding layer 50, so that the bonding layer 50 is prevented from overflowing outside the through hole 41 or onto the upper surface of the buffer layer 40 to cause abnormal bonding of the Micro LED chips 60, and further the transfer efficiency of the huge amount of Micro LED chips 60 is affected. Although not limited thereto, in one embodiment, the height H1 of the via 41 is equal to the height H2 of the bonding layer 50. At this time, the surface of the Micro LED chip 60 is attached to the upper surface of the buffer layer 40, and is electrically connected to the conductive layer 20 through the bonding layer 50. In this aspect, the width L4 of the Micro LED chip 60 is equal to or slightly greater than the width L3 of the via 41 in the buffer layer 40.

The width L3 of the through hole 41 in the buffer layer 40 is greater than or equal to the width L2 of the conductive layer 20, so that the width of the bonding layer 50 in the through hole 41 is greater than or equal to the width of the conductive layer 20, thereby ensuring excellent electrical connection performance between the bonding layer 50 and the conductive layer 20. In the illustrated example, the width L3 of the via 41 in the buffer layer 40 is greater than the width L2 of the conductive layer 20.

Referring to fig. 4 and fig. 5a to 5h in combination with fig. 1 and fig. 2, fig. 4 is a schematic flow chart of a second embodiment of the Micro LED transfer method shown in fig. 1, and fig. 5a to 5h are schematic process diagrams corresponding to the flow chart shown in fig. 4. The specific process steps of the second embodiment of the Micro LED transfer method illustrated in these figures are described below.

Referring to fig. 5a, referring to step (S01) of fig. 1, a first substrate 10 on which an array of electrodes 11 is disposed is provided. The first substrate 10 is shown as a Si-driven backplane. The Si-driven backplate 10 is provided with at least three arrays of electrodes 11, wherein the upper surfaces of two electrodes 11 are exposed to the same side of the Si-driven backplate 10, in the example shown the upper surface of the first substrate 10.

Referring to fig. 5b, referring to step (S02) of fig. 1, a conductive metal layer is formed on the first substrate 10, and a conductive layer 20 is formed on a portion of the electrode 11. Further, the conductive layer 20 is formed on a surface of the electrode 11 on a side exposed to the first substrate 10.

Specifically, a photoresist layer is coated on the upper surface of the Si-driven backplate 10 shown in fig. 5a, and the photoresist layer covers the upper surface of the central portion of the electrode 11 in the Si-driven backplate 10. Exposing and developing the photoresist layer to form a conductive metal pattern on the upper surface of the partial electrode 11. Then, a conductive metal layer is deposited on the photoresist layer. It is understood that the conductive metal layer overlies the photoresist layer and the conductive metal pattern. The photoresist layer is removed and at the same time the conductive metal layer in the unnecessary area is removed, and finally the conductive layer 20 is formed only on the upper surface of the partial electrode 11. As shown in fig. 5b, at least two electrodes 11 in the three electrode 11 arrays on the Si driving backplate 10 are correspondingly formed with a conductive layer 20 on the upper surface.

As shown in fig. 5c, referring to the steps of fig. 1 (S03) and fig. 4 (S21), a planar isolation layer 30 is deposited on the Si-driven backplate 10. The isolation layer 30 completely covers the respective conductive layers 20 formed in the previous steps and other areas of the upper surface of the Si driving backplate 10. The isolation layer 30 can isolate the conductive layers 20 and provide conductive protection. The isolation layer 30 may be a buffer insulating layer. In the illustrated example, the height or thickness of the isolation layer 30 is greater than the height or thickness of the conductive layer 20.

Further, referring to step (S22) of fig. 4, an opening 31 is formed in the isolation layer 30 at least at the position corresponding to the conductive layers 20, and the upper surface of the conductive layer 20 is exposed. Specifically, a photoresist layer is coated on the isolation layer 30. An opening 31 is formed above the conductive layer 20 by exposing and developing the photoresist layer.

In the illustrated embodiment, the isolation layer 30 is an organic photoresist material with elasticity, which can ensure a sufficient buffer space during eutectic bonding, and prevent the substrate or the LED device from being damaged due to pressure during the bonding process. The width L5 of the opening 31 is less than or equal to the width L2 of the conductive layer 20, which ensures that the bonding layer metal is confined within the hole during the eutectic process and does not overflow the opening 31, thereby causing signal short between adjacent conductive layers 20. In the illustrated example, the width L5 of opening 31 is less than the width L2 of conductive layer 20.

As shown in fig. 5d, referring to the steps of fig. 1 (S05) and fig. 4 (S23), a first bonding layer 51 is deposited and formed on the upper surface of the conductive layer 20. Specifically, a photoresist layer is coated on the isolation layer 30 and in the opening 31. A metal pattern is formed on the Si-driven backplate 10 at the opening 31 by exposing and developing above the photoresist layer. And depositing a metal layer or an alloy layer on the photoresist layer and the metal pattern. The photoresist layer is removed, and a first bonding layer 51 is formed on the metal pattern in the opening 31. The first bonding layer 51 may be one of gold, tin, nickel, titanium, aluminum, silver, indium, or an alloy of metal materials. In this process, the width of the first bonding layer 51 is smaller than or equal to the width of the opening 31, and the width of the first bonding layer 51 is smaller than or equal to the width of the conductive layer 20, so as to ensure that there is a sufficient electrical connection surface between the subsequent Micro LED chip and the conductive layer 20 to obtain a good conductive performance.

The upper surface of the first bonding layer 51 is flush with the upper surface of the isolation layer 30, or the upper surface of the first bonding layer 51 is lower than the upper surface of the isolation layer 30. In other words, the height or thickness of the first bonding layer 51 is less than or equal to the height or thickness of the opening 31 in the isolation layer 30. This arrangement facilitates subsequent processing operations over the isolation layer 30 and the first bonding layer 51.

In the illustrated embodiment, the width L1 of the first bonding layer 51 is less than the width L2 of the conductive layer 20 and less than or equal to the width L5 of the opening 31. Thus, it is ensured that the metal fluid of the first bonding layer 51 is confined in the hole area in the subsequent eutectic process and does not overflow the opening 31, thereby causing signal short circuit of the adjacent conductive layer 20.

As shown in fig. 5e and 5f, referring to the steps (S04) and (S05) of fig. 1 and the step (S24) of fig. 4, the buffer layer 40 is deposited on the isolation layer 30 and on the first bonding layer 51. The buffer layer 40 is provided with a through hole 41 corresponding to the first bonding layer 51 and the conductive layer 20. Specifically, a buffer layer 40 is deposited on the isolation layer 30 and the first bonding layer 51. A photoresist layer is coated on the buffer layer 40. A through hole 41 is opened in the buffer layer 40 corresponding to the first bonding layer 51 and the conductive layer 20 by exposing and developing processes above the photoresist layer, and then the photoresist layer is removed. The corresponding through hole 41 on the upper surface of the first bonding layer 51 can be used as a bonding active space or an active area required when the Micro LED chip is subjected to transfer bonding. The width of the via hole 41 is larger than the width of the conductive layer 20.

In the illustrated embodiment, the buffer layer 40 is an organic photoresist layer, which can ensure sufficient buffer space during eutectic bonding to prevent damage to the substrate or the LED device due to pressure during the bonding process.

Referring to fig. 5g, referring to step (S06) of fig. 1, a second substrate 70 is provided, and a plurality of Micro LED chips 60 are disposed on a surface of the second substrate 70. The Micro LED chips 60 are arranged in an array on the second substrate 70. The Micro LED chip 60 is shown flip-chip mounted on the second substrate 70. A second bonding layer 52 is disposed on a surface of each Micro LED chip 60 on a side away from the second substrate 70. The material of the second bonding layer 52 may be one of gold, tin, nickel, titanium, aluminum, silver, and indium, or an alloy of metal materials. The thickness of the second bonding layer 52 is related to the space required for curing of the bonding layer 50 after bonding, and the thickness of the buffer layer 40. The width of the second bonding layer 52 is smaller than or equal to the width of the Micro LED chip 60, so as to ensure that the Micro LED chip 60 is electrically connected to the first substrate 10 through the second bonding layer 52. The width of the second bonding layer 52 in the illustrated example is less than the width of the Micro LED chip 60.

When the Micro LED chips 60 are transferred to the first substrate 10, the second bonding layer 52 on the second substrate 70 is aligned and attached to the first bonding layer 51 on the first substrate 10. The metal or alloy on the first bonding layer 51 and the second bonding layer 52 is melted by a laser heating method. Meanwhile, the other side of the second substrate 70 (the side far from the Micro LED chip 60 in the figure) is continuously pressed, so that the first bonding layer 51 and the second bonding layer 52 complete eutectic bonding to form a bonding layer 50. Then, the second substrate 70 is removed, thereby obtaining the Micro LED panel 1, as shown in fig. 5 h. In the illustrated example, the bonding layer 50 is located in both the opening 31 in the isolation layer 30 and the via 41 in the buffer layer 40.

The width L3 of the through hole 41 in the buffer layer 40 is greater than or equal to the width L2 of the conductive layer 20, so that the width of the bonding layer 50 in the through hole 41 is greater than and/or less than the width of the conductive layer 20, thereby ensuring excellent electrical connection performance between the bonding layer 50 and the conductive layer 20. In the illustrated example, the bonding layer 50 is located in both the opening 31 of the isolation layer 30 and the via 41 of the buffer layer 40. The width of the bonding layer 50 in the opening 31 is less than or equal to the width L2 of the conductive layer 20, and the width of the bonding layer 50 in the through hole 41 is greater than or equal to the width L2 of the conductive layer 20.

Please refer to fig. 3h and fig. 5h with reference to fig. 1, fig. 2 and fig. 4. It is understood that the Micro LED panel structure shown in fig. 3h is fabricated according to the method shown in fig. 1 and 2, and the Micro LED panel structure shown in fig. 5h is fabricated according to the method shown in fig. 1 and 4.

To achieve at least one of the advantages or other advantages, an embodiment of the present invention provides a Micro LED panel 1, which can be manufactured by the Micro LED transfer method as described above. The Micro LED panel 1 at least includes a first substrate 10, a plurality of conductive layers 20, an isolation layer 30, a buffer layer 40 and a bonding layer 50.

An array of electrodes 11 is provided on the first substrate 10. A plurality of conductive layers 20 are disposed on the first substrate 10 and cover at least a portion of the array of electrodes 11.

The isolation layer 30 is disposed on the first substrate 10 and separates the conductive layers 20 to form a conductive protection for the conductive layers 20. The isolation layer 30 can be an insulating layer to ensure the electrical conductivity or signal convergence independence of two adjacent conductive layers 20, thereby preventing short circuit. The thickness of the isolation layer 30 is greater than or equal to the thickness of the conductive layer 20. In fig. 3h, the thickness of the isolation layer 30 is equal to the thickness of the conductive layer 20. In fig. 5h, the thickness of the isolation layer 30 is greater than the thickness of the conductive layer 20.

A buffer layer 40 is disposed on the isolation layer 30. The buffer layer 41 may be one of an insulating layer, an organic photoresist layer, and a passivation layer. The buffer layer 40 has through holes 41 corresponding to the conductive layers 20. The through hole 41 can be used as a bonding active space or an active area required when the Micro LED chip 60 is transfer bonded. The width L3 of the via hole 41 is greater than or equal to the width L4 of the Micro LED chip 60. Therefore, the Micro LED chip 60 can move in the through hole 41 and can be aligned and attached to the conductive layer 20 in the transfer bonding process of the Micro LED chip 60. The height H1 of the through hole 41 is greater than or equal to the height H2 of the bonding layer 50, so that the bonding layer 50 can be prevented from overflowing outside the through hole 41 or to the upper surface of the buffer layer 40 to cause abnormal bonding of the Micro LED chip 60, and further the transfer efficiency of the huge Micro LED chip 60 is affected.

The bonding layer 50 is at least partially located in the through hole 41, and the Micro LED chip 60 is electrically connected to the conductive layer 20 through the bonding layer 50, so as to ensure that the Micro LED chip 60 and the first substrate 10 have good conductive performance. The width of bonding layer 50 is less than and/or greater than the width of conductive layer 20. In fig. 3h, the width of the bonding layer 50 is greater than the width of the conductive layer 20. In fig. 5h, the width of the bonding layer 50 in the opening 31 is smaller than the width of the conductive layer 20, and the width of the bonding layer 50 in the through hole 41 is larger than the width of the conductive layer 20.

Although terms such as Micro LED chip, first substrate, second substrate, conductive metal layer, isolation layer, buffer layer, bonding layer, height, width, etc. are used more often herein, the possibility of using other terms is not excluded. These terms are used merely to more conveniently describe and explain the nature of the present invention; they are to be construed as being without limitation to any additional limitations that may be imposed by the spirit of the present invention.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A Micro LED transferring method is characterized by at least comprising the following steps:

depositing a first bonding layer on the surface of the conductive layer; and

providing a second substrate, wherein a plurality of Micro LED chips are arranged on one side surface of the second substrate, a second bonding layer is arranged on one side surface, far away from the second substrate, of each Micro LED chip, and the second bonding layer is in bonding connection with the first bonding layer;

2. The Micro LED transfer method of claim 1, wherein: the method for forming the isolation layer, the buffer layer and the first bonding layer on the first substrate comprises the following steps:

thinning the thickness of the isolation layer by adopting a chemical mechanical polishing method until the surface of the conductive layer is exposed;

3. The Micro LED transfer method of claim 2, wherein: the thickness of the buffer layer is more than 1 mu m, and the buffer layer is made of elastic organic photoresist material.

4. The Micro LED transfer method of claim 1, wherein: the method for forming the isolation layer, the buffer layer and the first bonding layer on the first substrate comprises the following steps:

forming an opening in at least part of the isolation layer corresponding to the conductive layer, and exposing the surface of the conductive layer, wherein the width of the opening is less than or equal to that of the conductive layer;

5. The Micro LED transfer method of claim 4, wherein: the isolation layer is made of elastic organic photoresist material; the buffer layer is an organic photoresist layer.

6. The Micro LED transfer method of claim 1, wherein: the first substrate is at least one of a driving substrate, a glass substrate, a Si substrate, a PI substrate and a display back plate.

7. The Micro LED transfer method of claim 1, wherein: the conducting layer is one or more of gold, tin, nickel, titanium, aluminum, silver and indium, or an alloy composed of metal materials.

8. The Micro LED transfer method of claim 1, wherein: the buffer layer is one of an insulating layer, an organic photoresist layer and a passivation layer.

9. The Micro LED transfer method of claim 1, wherein: the first bonding layer and the second bonding layer are respectively one or more of gold, tin, nickel, titanium, aluminum, silver and indium or an alloy formed by metal materials.

10. The Micro LED transfer method of claim 1, wherein: the bonding method of the first bonding layer and the second bonding layer is one or more of alloy eutectic bonding, diffusion bonding and transient liquid phase bonding.

11. The Micro LED transfer method of claim 1, wherein: the bonding mode of the second bonding layer and the first bonding layer is to melt the metals in the second bonding layer and the first bonding layer by a laser heating method and continuously press the metals to form the metal bonding layer.

12. A Micro LED panel, producible by the Micro LED transfer method according to any of claims 1 to 11, characterized in that it comprises at least:

the electrode array is arranged on the first substrate;

the width of the through hole is larger than or equal to that of the Micro LED chip, and the height of the through hole is larger than or equal to that of the bonding layer.

13. A Micro LED panel according to claim 12, wherein: the isolation layer is an insulating layer, and the thickness of the isolation layer is greater than or equal to that of the conducting layer.

14. A Micro LED panel according to claim 12, wherein: the buffer layer is one of an insulating layer, an organic photoresist layer and a passivation layer.

15. A Micro LED panel according to claim 12, wherein: the width of the bonding layer is smaller and/or larger than the width of the conductive layer.