CN114171524A - Preparation method of semiconductor structure and three-dimensional memory - Google Patents

Abstract

The application provides a preparation method of a semiconductor structure and a three-dimensional memory, which comprises the following steps: alternately stacking a sacrificial layer and a dielectric layer on a substrate to form a stacked structure, wherein the stacked structure includes a cutting region; forming a plurality of first dummy channel openings through portions of the stack structure located in a dicing region and extending into the substrate; filling a channel filling material in the first dummy channel opening to form a first dummy channel structure; forming a cutting groove penetrating through the first dummy channel structure; and filling a conductive material in the cutting groove to form a cutting path.

Description

Preparation method of semiconductor structure and three-dimensional memory

Technical Field

The present disclosure relates to the field of three-dimensional memory technologies, and more particularly, to a semiconductor structure and a method for manufacturing a three-dimensional memory.

Background

In a three-dimensional memory, a Scribe Line (Scribe Line) is used to divide different chips (Die), generally, a Wafer (Wafer) includes a plurality of chips, a Scribe Line is disposed between adjacent chips, a dicing process is performed through the Scribe Line to cut the Wafer into small dies, and then the dies are packaged to form chips (chips). However, as the number of stacked layers of the three-dimensional memory is increased, the etching aspect ratio of the scribe line is increased, which results in an increase in difficulty of manufacturing the scribe line.

Disclosure of Invention

An embodiment of the present application provides a method of fabricating a three-dimensional memory, the method including: alternately stacking a sacrificial layer and a dielectric layer on a substrate to form a stacked structure, wherein the stacked structure includes a cutting region; forming a plurality of first dummy channel openings through portions of the stack structure located in the dicing area and extending into the substrate; filling a channel filling material in the first dummy channel opening to form a first dummy channel structure; forming a cutting groove penetrating through the first dummy channel structure; and filling a conductive material in the cutting groove to form a cutting path.

In one embodiment, outlines of a cross section of the first dummy channel opening, the scribe line, and the scribe lane in a direction parallel to the substrate are arranged in a zigzag shape.

In one embodiment, the stacked structure further comprises a step region, the method further comprising: forming a second dummy channel opening penetrating through a portion of the stacked structure located in the step area and extending into the substrate, and filling a channel filling material in the second dummy channel opening to form a second dummy channel structure, wherein the second dummy channel opening and the first dummy channel opening are formed by using the same mask plate, and the second dummy channel structure is formed when the first dummy channel structure is formed.

In one embodiment, the stacked structure further comprises a core region and a step region, the method further comprising: forming gate line slits through portions of the stacked structure located in the core region and the stepped region and extending into the substrate; and replacing the sacrificial layers of the core region and the step region with gate layers through the gate line slits. In one embodiment, the method may further comprise: replacing the sacrificial layer with a gate layer.

In one embodiment, the step region includes a plurality of steps and an insulating layer covering the plurality of steps, and the method further includes: forming a plurality of conductive channel holes penetrating through the insulating layer and respectively extending to the portions of the gate layer located in the step areas, and filling a conductive material in the conductive channel holes to form a plurality of conductive pillars, wherein the plurality of conductive channel holes and the cutting grooves are formed by using the same mask plate, and the plurality of conductive pillars are formed when the cutting channels are formed.

In one embodiment, the insulating layer and the trench fill material are configured to have the same etch selectivity.

In a second aspect, embodiments of the present application provide a semiconductor structure comprising a substrate; a stack structure disposed on the substrate, the stack structure including a cutting region; a plurality of first dummy channel structures located through portions of the stacked structure in the scribe area and having scribe lines therethrough.

In one embodiment, the contour of the cross-section of the scribe line in a direction parallel to the substrate is a zigzag shape.

In one embodiment, the portion of the stacked structure located at the cutting region includes sacrificial layers and dielectric layers that are alternately stacked.

In one embodiment, the stack structure further includes a step region, wherein the semiconductor structure further includes a second dummy channel structure located in the step region through the stack structure and extending into the substrate.

In one embodiment, the first dummy channel structure and the second dummy channel structure comprise the same channel fill material.

In one embodiment, the stacked structure further includes a step region, and the portion of the stacked structure located in the step region includes gate layers and dielectric layers that are alternately stacked.

In one embodiment, the step region includes a plurality of steps and an insulating layer covering the plurality of steps, wherein the semiconductor structure further includes a plurality of conductive pillars penetrating the insulating layer and respectively extending to portions of the gate layer located in the step region.

According to the semiconductor structure and the preparation method of the three-dimensional memory, the dielectric layer and the sacrificial layer of the stacked structure are reserved in the cutting area, so that the stress of the step area of the three-dimensional memory can be effectively reduced, and the process difficulty of the step area is reduced. By forming the first dummy channel structure penetrating through the stacked structure in the scribe region and then forming the scribe line through the first dummy channel structure, the scribe line can be closer to the step region, and thus the chip size of the three-dimensional memory can be reduced.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:

fig. 1 and 2 are top views schematically showing the distribution of the cutting region, the step region, and the core region of the three-dimensional memory.

FIG. 3 is a schematic cross-sectional view of a semiconductor structure in one embodiment.

Fig. 4 is a flowchart of a method of manufacturing a three-dimensional memory in another embodiment.

Fig. 5 to 9 are process diagrams of a method of manufacturing a three-dimensional memory according to an exemplary embodiment of the present application.

Detailed Description

For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that the detailed description is merely illustrative of exemplary embodiments of the present application and does not limit the scope of the present application in any way. Like reference numerals refer to like elements throughout the specification. The expression "and/or" includes any and all combinations of one or more of the associated listed items.

It should be noted that in this specification, the expressions first, second, third, etc. are used only to distinguish one feature from another, and do not represent any limitation on the features. Thus, a first dummy channel structure discussed below may also be referred to as a second dummy channel structure, and vice versa, without departing from the teachings of the present application.

In the drawings, the thickness, size and shape of the components have been slightly adjusted for convenience of explanation. The figures are purely diagrammatic and not drawn to scale. Such as the thickness of the substrate and the stack structure, are not to scale in actual production. As used herein, the terms "approximately", "about" and the like are used as table-approximating terms and not as table-degree terms, and are intended to account for inherent deviations in measured or calculated values that would be recognized by one of ordinary skill in the art.

It will be further understood that the terms "comprises," "comprising," "has," "having," "includes" and/or "including," when used in this specification, specify the presence of stated features, elements, and/or components, but do not preclude the presence or addition of one or more other features, elements, components, and/or groups thereof. Moreover, when a statement such as "at least one of" appears after a list of listed features, the entirety of the listed features is modified rather than modifying individual elements in the list. Furthermore, when describing embodiments of the present application, the use of "may" mean "one or more embodiments of the present application. Also, the term "exemplary" is intended to refer to an example or illustration.

Unless otherwise defined, all terms (including engineering and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. The layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate and the top side is relatively far from the substrate. The layer can extend over the entire underlying or overlying structure or can have a smaller extent than the underlying or overlying structure. Furthermore, the layer can be a region of uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer can be located between any set of horizontal planes at or between the top and bottom surfaces of the continuous structure. The layers can extend horizontally, vertically, and/or along a tapered surface. The substrate can be a layer, such as a semiconductor layer. The substrate can include one or more layers therein, and/or can have one or more layers thereon, and/or thereunder. The substrate can be a layer of a thickness that has support capability, as well as a layer of a thickness that does not have support capability.

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. In addition, unless explicitly defined or contradicted by context, the specific steps included in the methods described herein are not necessarily limited to the order described, but can be performed in any order or in parallel. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.

Fig. 1 and 2 are top views of a three-dimensional memory, which may include a Core region (Core)103 and a terrace region (SS)102 surrounded by a cutting region 101, i.e., the cutting region 101 is disposed at the periphery of the Core region 103 and the terrace region 102. In one embodiment of the present application, the core region 103 and the stepped region 102 are arranged as shown in fig. 1, wherein the stepped region 102 is located between two core regions 103. In another embodiment of the present application, the core region 103 and the stepped region 102 are arranged as shown in fig. 2, the core region 103 being located between two stepped regions 102. However, those skilled in the art will appreciate that the arrangement of the core region 103 and the stepped region 102 in fig. 1 and 2 is an exemplary arrangement, and the present application is not limited thereto.

Fig. 1 and 2 schematically show that the dicing area 101 may contain two dicing streets 501, wherein the contour lines of the cross sections of the dicing streets 501 in the direction parallel to the substrate are in a zigzag shape.

FIG. 3 is a cross-sectional schematic view of a semiconductor structure 10' in one embodiment. As shown in fig. 3, the semiconductor structure 10' may include a substrate 10a and a stack structure 20a formed on the substrate 10a, wherein the stack structure 20a includes dielectric layers 201a and gate layers 203a alternately stacked on the substrate 10 a. The semiconductor structure 10' may further include an insulating layer 30a, the insulating layer 30a mainly serves as a step structure covering the step region 102a and also serves as a support material for the scribe region 101a, and illustratively, two scribe lines 501a are formed in the insulating layer 30a of the scribe region 101 a. Illustratively, the insulating layer 30a may include at least one insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or the like. The stepped region 102a may include a plurality of dummy channel structures 402a and conductive pillars 502 a. The dummy channel structure 402a mainly serves to provide support for the step region 102 a.

The semiconductor structure 10' may be mechanically separated into a plurality of chips for subsequent formation of three-dimensional reservoirs via dicing streets 501 a. The inventors have noticed in their studies that the insulating layer 30a of the semiconductor structure 10' in the embodiment shown in fig. 3, which is located in the scribe line 101a, is formed at the same time as the insulating layer 30a is formed in the step region 102a, and then the insulating layer 30a of the scribe line 102a is etched to form scribe grooves (not shown) and the conductive material is filled in the scribe grooves to form the scribe lines 501 a. However, as the number of stacked structures 20a increases, the aspect ratio of the scribe line 501a becomes larger, and the stress distribution imbalance between the insulating layer 30a and the stacked structure 20a becomes more serious, which results in the difficulty of the process for preparing the scribe line 501 a.

Some embodiments of the present application provide methods of fabricating three-dimensional memory devices other than those shown in fig. 3 above. Fig. 4 schematically shows a flow chart of a method 1000 for manufacturing a three-dimensional memory in another embodiment. As shown in fig. 4, the method includes:

s110: alternately stacking a sacrificial layer and a dielectric layer on a substrate to form a stacked structure, wherein the stacked structure includes a cutting region;

s120: forming a plurality of first dummy channel openings through portions of the stacked structure located in the dicing area and extending into the substrate;

s130: filling a channel filling material in the first dummy channel opening to form a first dummy channel structure;

s140: forming a cutting groove penetrating through the first dummy channel structure; and

s150: and filling the cutting groove with a conductive material to form a cutting path.

In the process of manufacturing the three-dimensional memory, a plurality of steps such as manufacturing a core region and a peripheral circuit of the three-dimensional memory are also included. However, in order to highlight the emphasis of the invention, the above steps are not described in the present application, and those skilled in the art can determine the preparation method of the cutting region disclosed in the present application related to other structures of the three-dimensional memory according to their knowledge, and the embodiments and process flows in the present application only show the intermediate body for forming the three-dimensional memory having the cutting region and the step region.

It should be understood that the steps shown in method 1000 are not exclusive and that other steps may be performed before, after, or between any of the steps shown. Further, some of the steps may be performed simultaneously or may be performed in an order different from that shown in fig. 4.

Fig. 5 to 9 are schematic cross-sectional views illustrating a method 1000 for fabricating a three-dimensional memory according to an embodiment of the present disclosure. The above steps S110 to S150 are further described below with reference to fig. 5 to 9.

S110, alternately stacking sacrificial layers and dielectric layers on a substrate to form a stacked structure, wherein the stacked structure comprises And (4) cutting the area.

In some embodiments of step S110, as shown in fig. 5, in this step, dielectric layers 201 and sacrificial layers 202 are alternately stacked on a substrate 10 to form a stacked structure 20. Illustratively, the method of forming the stack structure 20 may include a thin film deposition process such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof. The number of stacked dielectric layers 201 and sacrificial layers 202 in the stacked structure 20 may be, for example, 8, 32, 64, 128, or the like. The greater the number of stacks of the stack structure 20, the higher the integration level, and the greater the number of memory cells formed therefrom. The stacking number and the stacking height of the stack structure 20 may be designed according to actual storage requirements, which is not specifically limited in the present application.

Illustratively, the material of the substrate 10 may include, for example, silicon (e.g., single crystal silicon, polycrystalline silicon), silicon germanium (SiGe), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), glass, a group III-V compound semiconductor, or any combination thereof. The material of the insulating layer 201 may include, for example, an oxide (such as silicon oxide). The material of sacrificial layer 202 may, for example, comprise a nitride (such as silicon nitride).

In some examples, the substrate 10 functions to provide support for other structures fabricated thereon, but in appropriate steps, the substrate 10 may be removed from a side of the substrate 10 facing away from the stacked structure 20 using a photolithography and etching process (e.g., a dry or wet etching process), a CMP process, or any combination thereof, and in some cases, as an example, a semiconductor layer, such as comprising polysilicon, may also be formed on a side of the stacked structure 20 exposed by the removal of the substrate 10. The substrate 10 also includes the semiconductor layers described above, and the substrate 10 may not have support capability. The substrate 10 is not limited to a material and a thickness, and the substrate 10 can be a layer having a thickness capable of being supported, and the substrate 10 can also be a layer having a thickness not capable of being supported.

In an exemplary embodiment, the stack structure 20 according to the present application may have a structure in which silicon oxide and silicon nitride are sequentially deposited as a stack.

In an exemplary embodiment, as shown in fig. 5, the cutting region 101 and the step region 102 may be defined in the stacked structure 20, or it may also be considered that the stacked structure 20 may include portions located at the cutting region 101 and the step region 102, and exemplarily, the portion of the stacked structure 20 located at the step region 102 is patterned into a plurality of step structures.

In some embodiments, the step structure may be formed by performing a "trim-etch" cycle process for a plurality of dielectric layers 201 and a plurality of sacrificial layers 202 alternately stacked. Illustratively, as shown in fig. 5, each step may include one dielectric layer 201 and one sacrificial layer 202. In the direction perpendicular to the substrate 10, the pair of dielectric layers 201 and the sacrificial layer 202 far from the substrate 10 partially covers the pair of dielectric layers 201 and the sacrificial layer 202 adjacent and closer to the substrate 10, so that the sacrificial layer 202 of the pair of insulating layers 201 and the sacrificial layer 202 close to the substrate 10 has a region exposed to the pair of dielectric layers 201 and the sacrificial layer 202 adjacent and far from the substrate 10. The exposed regions of sacrificial layer 202 may serve as electrical connection regions for word line contacts formed during subsequent processing.

In some embodiments, an insulating layer 30 is formed over the step structure, and the insulating layer 30 includes at least one insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride. The insulating layer 30 is mainly used to cover the step structure and the surrounding areas, such as the cutting region 101 and the core region (not shown), and the insulating layer 30 may be subsequently planarized by Chemical Mechanical Polishing (CMP).

S120, forming a plurality of first dummy channels penetrating through the part of the stacked structure in the cutting area and extending into the substrate And (4) opening.

In some embodiments of step S120, as shown in fig. 6, in this step, a plurality of first dummy channel openings 41 are formed, wherein the first dummy channel openings 41 penetrate through the portion of the stacked structure 20 located in the cutting region 101 and extend into the substrate 10.

In some embodiments of step S120, the step S120 may further include forming a second dummy channel opening 42, the second dummy channel opening 42 penetrating the insulating layer 30 and a portion of the stack structure 20 located in the step region 102.

In some embodiments, the first and second dummy channel openings 41 and 42 may be formed by the same process and method, i.e., the first and second dummy channel openings 41 and 42 may be formed simultaneously by using the same mask, and for example, a plurality of dummy channel openings extending through the stacked structure 20 and into the substrate 10 may be formed by using a photolithography and etching process (e.g., a dry or wet etching process). Specifically, for the sake of convenience in description, the dummy channel opening in the cutting region 101 is defined as a first dummy channel opening 41, and the dummy channel opening in the step region 102 is defined as a second dummy channel opening 42.

In some embodiments, the outline of the cross-section of the first dummy channel opening 41 in a direction parallel to the substrate 10 is closed, e.g., polygonal.

In some embodiments, two first dummy channel openings 41 may be provided, and the outline of the cross section of the first dummy channel opening 41 in the direction parallel to the substrate 10 is in a zigzag shape.

S130, filling a channel filling material in the first dummy channel opening to form a first dummy channel structure.

In some embodiments of step S130, as shown in fig. 7, in this step, a channel filling material is filled in the first dummy channel opening 41 to form a first dummy channel structure 401.

In some embodiments, the outline of the cross-section of the first dummy channel structure 401 in a direction parallel to the substrate 10 is closed, e.g., polygonal.

In some embodiments, two first dummy channel structures 401 may be provided, and the outline of the cross section of the first dummy channel structure 401 in the direction parallel to the substrate 10 is in a zigzag shape.

In some embodiments of step S130, this step S130 may further include filling a channel filling material in the second dummy channel opening 42 to form a second dummy channel structure 402.

In some embodiments, the filling material and the filling process of the first dummy channel structure 401 and the second dummy channel structure 402 may be the same, i.e., the channel filling material may also be filled simultaneously in the first dummy channel opening 41 and the second dummy channel opening 42 to form the first dummy channel structure 401 and the second dummy channel structure 402 simultaneously. Illustratively, after the first and second dummy channel openings 41 and 42 are formed as described above, at least one channel filling material, which may be an insulating material such as silicon oxide, may be filled in the first and second dummy channel openings 41 and 42 using a thin film deposition process such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof. The fine structure of the first dummy channel structure 401 and the second dummy channel structure 402 in fig. 7 is simplified or the first dummy channel structure 401 and the second dummy channel structure 402 in fig. 7 are considered to include only a channel filling material.

The role of the first dummy channel structure 401 and the second dummy channel structure 402 includes, but is not limited to, providing mechanical support or load balancing. In particular, the second dummy channel structure 402 is a structure configured to alleviate the stress imbalance between the insulating layer 30 and the stepped structure. It can be understood that the distance between the plurality of second dummy channel structures 402 may be closer to each other, so as to improve the supporting effect of the dummy channel structures 402 on the insulating layer 30, and especially when the number of layers of the step structures is large and the height of the step structures is higher, the supporting effect of the densely arranged second dummy channel structures 402 on the subsequent gate replacement process is better.

Referring to fig. 7 and 8A, in an exemplary embodiment of the present application, the method 1000 of fabricating a three-dimensional memory may further include replacing the sacrificial layer 202 of the core region (not shown) and the step region 102 with the gate layer 203. While the stacked structure 20 of the cutting region 101 still maintains the structure of alternately stacking the dielectric layers 201 and the sacrificial layers 202.

In some embodiments, gate line slits (not shown) are formed through portions of the stacked structure 20 located in the core region (not shown) and the stepped region 102 and extending into the substrate 10, and the gate line slits are used to replace the sacrificial layer 202 of the stacked structure 20 located in the core region and the stepped region 102 with the gate layer 203. Illustratively, photolithography and etching processes (e.g., dry or wet etching processes) may be used to form gate line slits extending through the stacked structure 20 at portions of the core region and the stepped region 102 and into the substrate 10. Further, the sacrificial layer 202 of the stacked structure 20 in the core region and the step region 102 may be removed by a process such as wet etching to form a sacrificial gap (not shown) using the gate line slit as a passage for providing an etchant and a chemical precursor. Next, a gate layer 203 may be formed within the sacrificial gap, for example, using a thin film deposition process such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof (fig. 8A). Alternatively, the material of the gate layer 203 may, for example, comprise a conductive material such as tungsten, cobalt, copper, aluminum, or any combination thereof.

S140, forming a cutting groove penetrating the first dummy channel structure.

In some embodiments of step S140, as shown in fig. 8A, in this step, a scribe line 51 is formed through the first dummy channel structure 401. Illustratively, the first dummy channel structure 401 is etched, and a cutting groove 51 may be formed through the first dummy channel structure 401 by using a photolithography and etching process (e.g., a dry or wet etching process).

Fig. 8B is a schematic sectional view at a-a in fig. 8A, and exemplarily, the outline of a cross section of the dicing groove 51 in a direction parallel to the substrate 10 is a zigzag shape.

In some embodiments, the contour line of the cross section of the dicing groove 51 in the direction parallel to the substrate 10 is closed, for example, a polygon.

In some embodiments of step S140, as shown in fig. 8A, the step S140 may further include forming conductive via holes 52, wherein the conductive via holes 52 penetrate the insulating layer 30 and respectively extend to the gate layer 203 of the corresponding step. Illustratively, the insulating layer 30 is etched, and photolithography and etching processes (e.g., dry or wet etching processes) may be used.

In an exemplary embodiment, the channel filling material and the insulating layer 30 included in the first dummy channel structure 401 may be the same or have the same etching selectivity, and the same mask may be used to simultaneously perform an etching process to simultaneously form the scribe line 51 and the conductive via hole 52.

S150, filling the conductive material in the cutting groove to form a cutting path.

In some embodiments of step S150, as shown in fig. 9, in this step, the scribe line 51 is filled with a conductive material to form a scribe line 501. Illustratively, the dicing grooves 51 may be filled with a conductive material, for example, using a thin film deposition process such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof. The conductive material may, for example, comprise a conductive material such as tungsten, cobalt, copper, aluminum, or any combination thereof.

In some embodiments, the contour of the cross-section of the scribe line 501 in a direction parallel to the substrate 10 is closed, e.g., polygonal.

In some embodiments, two dicing streets 501 may be provided, and the contour lines of the cross sections of the dicing streets 501 in the direction parallel to the substrate 10 are in a zigzag shape.

In some embodiments of step S150, as shown in fig. 9, the step S150 may further include filling the conductive via hole 52 with a conductive material to form a conductive pillar 502, where the conductive pillar 502 is a word line contact of the three-dimensional memory. Illustratively, the conductive channel hole 52 may be filled with a conductive material, for example, using a thin film deposition process such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof. Illustratively, the plurality of conductive pillars 502 may extend to the electrical connection regions of the plurality of gate layers 203 in a direction intersecting the gate layer 203, for example, a direction perpendicular or substantially perpendicular to the gate layer 203, such that one end of the conductive pillar 502 is electrically connected with the gate layer 203. Wherein the conductive material may, for example, comprise a conductive material such as tungsten, cobalt, copper, aluminum, or any combination thereof.

In some embodiments, the materials and processes used to form the scribe line 501 by filling the conductive material in the scribe line 51 and the conductive post 502 by filling the conductive material in the conductive via hole 52 may be the same, that is, the scribe line 501 and the conductive post 502 may also be formed at the same time.

Another aspect of the present application also provides a semiconductor structure 2000, as shown in fig. 9, the semiconductor structure 2000 may include a cutting region 101 and a step region 102. Semiconductor structures according to some embodiments of the present application include: a substrate 10, a stack structure 20, a first dummy channel structure 401, and a scribe line 501.

The substrate 10 is a semiconductor substrate, and suitable materials may be selected to form the substrate 10 according to actual requirements, which will not be described herein again. In some examples, the substrate 10 functions to provide support for other structures fabricated thereon, but in some cases, as an example, the substrate 10 may also be a semiconductor layer without support capability, including, for example, polysilicon. The substrate 10 is not limited to a material and a thickness, and the substrate 10 can be a layer having a thickness capable of being supported, and the substrate 10 can also be a layer having a thickness not capable of being supported.

In an exemplary embodiment, a portion of the stack structure 20 located at the cutting region 101 may include sacrificial layers 202 and dielectric layers 201 alternately stacked in a direction perpendicular or substantially perpendicular to the substrate 10. The material of the dielectric layer 201 may, for example, comprise an oxide (such as silicon oxide). The material of sacrificial layer 202 may, for example, comprise a nitride (such as silicon nitride).

The first dummy channel structure 401 penetrates through a portion of the stack structure 20 located in the cutting region 101, and the first dummy channel structure 401 may include at least one channel filling material, which may be an insulating material, such as silicon oxide.

A scribe line 501 is located in the scribe region 101 and extends through the first dummy channel structure 401, and the scribe line 501 may include a conductive material. The conductive material may, for example, comprise a conductive material such as tungsten, cobalt, copper, aluminum, or any combination thereof.

In some embodiments, the outline of the cross-section of the first dummy channel structure 401 and the scribe line 501 in a direction parallel to the substrate 10 is closed, e.g., polygonal.

In some embodiments, the outline of the cross-section of the first dummy channel structure 401 and the scribe lane 501 in a direction parallel to the substrate 10 is a zigzag.

In an exemplary embodiment, a portion of the stack structure 20 located in the step region 102 may include a plurality of steps, wherein each step includes at least one pair of the gate layer 203 and the dielectric layer 201. In the direction perpendicular to the substrate 10, the pair of dielectric layers 201 and the gate layer 203 far from the substrate 10 partially covers the pair of dielectric layers 201 and the gate layer 203 adjacent and closer to the substrate 10, so that the gate layer 203 of the pair of dielectric layers 201 and the gate layer 203 close to the substrate 10 has an area exposed to the pair of dielectric layers 201 and the gate layer 203 adjacent and far from the substrate 10. The exposed areas of the gate layer 203 may serve as electrical connection areas for word line contacts. The material of the gate layer 203 may, for example, comprise a conductive material such as tungsten, cobalt, copper, aluminum, or any combination thereof.

In an exemplary embodiment, the semiconductor structure 2000 further includes an insulating layer 30, the insulating layer 30 is mainly used for covering the step structure and the surrounding area thereof, for example, the insulating layer 30 may cover the step region 102 and the cutting region 101. The material of the insulating layer 30 may be, for example, silicon oxide, silicon nitride, silicon oxynitride, or the like.

In an exemplary embodiment, the semiconductor structure 2000 further includes a second dummy channel structure 402 located in the stepped region 102, and the second dummy channel structure 402 may penetrate the insulating layer 30 and the portion of the stack structure 20 located in the stepped region 102. The second dummy channel structure 402 may include at least one channel fill material, which may be an insulating material, such as silicon oxide.

In some embodiments, the channel fill material and fill process of the first dummy channel structure 401 and the second dummy channel structure 402 may be the same. The fine structure of the first dummy channel structure 401 and the second dummy channel structure 402 is simplified in fig. 9, or the first dummy channel structure 401 and the second dummy channel structure 402 in fig. 9 are considered to include only a channel filling material.

The role of the first dummy channel structure 401 and the second dummy channel structure 402 includes, but is not limited to, providing mechanical support or load balancing. In particular, the second dummy channel structure 402 is a structure configured to alleviate the stress imbalance between the insulating layer 30 and the stepped structure. It can be understood that the distances between the plurality of second dummy channel structures 402 may be closer to each other, so as to improve the supporting effect of the dummy channel structures 402 on the insulating layer 30, and especially when the number of layers of the step structures is large and the height is higher, the supporting effect of the densely arranged second dummy channel structures 402 on processes such as a gate replacement process, chemical mechanical polishing, and the like is better.

In an exemplary embodiment, the first dummy channel structure 401 may include the same channel filling material as the insulating layer 30 or have the same etch selectivity.

In an exemplary embodiment, the semiconductor structure 2000 further includes conductive pillars 502 located in the step region 102, and the conductive pillars 502 penetrate the insulating layer 30 and respectively extend to the gate layer 203 corresponding to the steps. Conductive post 502 may comprise a conductive material. Illustratively, the plurality of conductive pillars 502 may extend to the electrical connection regions of the plurality of gate layers 203 in a direction intersecting the gate layer 203, for example, a direction perpendicular or substantially perpendicular to the gate layer 203, such that one end of the conductive pillar 502 is electrically connected with the gate layer 203. Conductive pillars 502 are word line contacts for a three-dimensional memory. Wherein the conductive material may, for example, comprise a conductive material such as tungsten, cobalt, copper, aluminum, or any combination thereof.

In some embodiments, the materials of the scribe line 501 and the conductive post 502 may be the same.

Since the matters and structures involved in the description of the fabrication method 1000 above may be fully or partially applicable to the semiconductor structures described herein, descriptions related or analogous thereto are omitted. The semiconductor structure 2000 may be mechanically separated into a plurality of chips for subsequent formation of a three-dimensional memory via dicing streets 501.

In the semiconductor structure 10' of one embodiment shown in fig. 3, the stacked structure 20a is not retained in the scribe line 101a, the scribe line 101a is located in the insulating layer 30a near the step region 102a, and a sufficient process width is required for forming the scribe line 501a by using a conductive Contact (CT) process, so that the scribe line 501a can be disposed only at a position far from the step region 102a, and thus the chip size is large. In addition, the step structure of the step region 102a and the insulating layer 30a covering the step structure and the cutting region 101a may cause the step region 102a to be subjected to a large stress due to different materials. However, referring to fig. 9, the cutting region 101 of the semiconductor structure 2000 provided by the embodiment of the present application retains the dielectric layer 201 and the sacrificial layer 202 of the stacked structure 20, which can effectively relieve the stress of the step region 102, and the cutting street 501 is formed by the first dummy channel structure 401, so that the cutting street 501 can be closer to the step region 102, and the chip size can be reduced.

The above description is only a preferred embodiment of the present application and is illustrative of the principles of the technology employed. It will be appreciated by a person skilled in the art that the scope of protection covered by the present application is not limited to the embodiments with a specific combination of the features described above, but also covers other embodiments with any combination of the features described above or their equivalents without departing from the technical idea described above. For example, the above features and (but not limited to) features having similar functions in this application are mutually replaced to form the technical solution.

Claims (13)

1. A method of fabricating a three-dimensional memory, the method comprising:

alternately stacking a sacrificial layer and a dielectric layer on a substrate to form a stacked structure, wherein the stacked structure includes a cutting region;

forming a plurality of first dummy channel openings through portions of the stack structure located in the dicing area and extending into the substrate;

filling a channel filling material in the first dummy channel opening to form a first dummy channel structure;

forming a cutting groove penetrating through the first dummy channel structure; and

and filling a conductive material in the cutting groove to form a cutting path.

2. The method of claim 1, wherein outlines of a cross section of the first dummy channel opening, the scribe line, and the scribe lane in a direction parallel to the substrate are arranged in a zigzag shape.

3. The method of claim 1, wherein the stacked structure further comprises a step region, the method further comprising:

forming a second dummy channel opening through a portion of the stack structure located in the stepped region and extending into the substrate, and filling a channel fill material in the second dummy channel opening to form a second dummy channel structure,

wherein the second dummy channel opening and the first dummy channel opening are formed using the same mask, and the second dummy channel structure is formed when the first dummy channel structure is formed.

4. The method of claim 1, wherein the stacked structure further comprises a core region and a step region, the method further comprising:

forming gate line slits through portions of the stacked structure located in the core region and the stepped region and extending into the substrate; and

and replacing the sacrificial layer in the core region and the step region with a gate layer through the gate line slits.

5. The method of claim 4, wherein the step region comprises a plurality of steps and an insulating layer covering the plurality of steps, the method further comprising:

forming a plurality of conductive via holes penetrating the insulating layer and respectively extending to portions of the gate layer located in the step regions, and filling a conductive material in the conductive via holes to form a plurality of conductive pillars,

and forming the conductive channel holes and the cutting grooves by using the same mask plate, and forming the conductive columns when the cutting grooves are formed.

6. The method of claim 5, wherein the insulating layer and the trench fill material are configured to have the same etch selectivity.

7. A semiconductor structure, comprising:

a substrate;

a stack structure disposed on the substrate, the stack structure including a cutting region;

a plurality of first dummy channel structures located through portions of the stacked structure in the scribe area and having scribe lines therethrough.

8. The semiconductor structure of claim 7, wherein a contour of a cross-section of the scribe line in a direction parallel to the substrate is a zigzag shape.

9. The semiconductor structure of claim 7, wherein the portion of the stack structure located at the dicing region comprises alternately stacked sacrificial layers and dielectric layers.

10. The semiconductor structure of claim 7, the stack structure further comprising a step region, wherein the semiconductor structure further comprises a second dummy channel structure located in the step region through the stack structure and extending into the substrate.

11. The semiconductor structure of claim 10, wherein the first and second dummy channel structures comprise the same channel fill material.

12. The semiconductor structure of claim 7, wherein the stack structure further comprises a stepped region, and a portion of the stack structure located in the stepped region comprises alternately stacked gate layers and dielectric layers.

13. The semiconductor structure of claim 12, the stepped region comprising a plurality of steps and an insulating layer covering the plurality of steps, wherein the semiconductor structure further comprises a plurality of conductive pillars penetrating the insulating layer and respectively extending to portions of the gate layer located in the stepped region.

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