CN1141703A

CN1141703A - Higher order digital phase loop filter

Info

Publication number: CN1141703A
Application number: CN 94194823
Authority: CN
Inventors: B·B·巴特
Original assignee: RCA Licensing Corp
Current assignee: RCA Licensing Corp
Priority date: 1994-01-12
Filing date: 1994-01-12
Publication date: 1997-01-29
Anticipated expiration: 2014-01-12
Also published as: CN1123182C

Abstract

High order phase loop filter includes and integrator consisting of an adder and a delay element arranged in a feedback loop between the output port of such adder and one of its input ports. Signal to be filtered is applied to a second input port of the adder. A detector is coupled to the output of the adder to detect limiting value, which, when detected, conditions the detector to reset the current valve in the delay element of the integrator to a fixed value such as zero. Resetting the delay element momentarily lowers the order of the filter and speeds system responds time in the presence of noise.

Description

Higher order digital phase loop filter

The present invention relates to be used to recover the circuit of pulse amplitude modulation PAM signal, especially for the loop filter of this system.

The PAM signal for example appears at such as among quadrature amplitude modulation (QAM), phase shift keying (PSK) and some kinds of forms of Quadrature Phase Shift Keying (QPSK), and the information of PAM signal is that constellation with the discrete amplitude of representing fixed number is a feature.The recovery of the information that is sent requires to recover to have the carrier wave of the signal modulation of suitable phase control, to guarantee correct constellation orientation.Typical PAM signal system was published in the Kluwer of BostonMa. Academic Pub. publishing company in 1992, be described in article " DIGITAL COMMUNICATION " the 14th chapter of author for Lee and Messerschmitt, an example of this system is illustrated among Fig. 1 of this specification.

The equipment of Fig. 1 comprises a PAM signal source (not shown) that is applied to frequency mixer 11.Frequency mixer 11 can be to have a complex multiplier that is used to receive the first input end mouth of PAM signal and is used to apply second input port of the carrier signal that is resumed.Frequency mixer 11 provides a baseband signal to a phase circuit that comprises amplitude limiter 12 and decision circuit 13.Decision circuit 13 is determined poor between the amplitude of the amplitude of received signals and most probable constellation value, and exports as error e that this is poor.Parts 11,12 and 13 be combined to form one of a plurality of phase detectors that replace 10.The output of these phase detectors is applied to loop filter 14, and this loop filter is combined and regularly intercepts and captures parameter with the measurement that noise immunity is provided and the system that sets up.The output of loop filter is to be coupled a control signal C who is used to control controlled oscillator 15.If frequency mixer 11 is realized that by analog form oscillator 15 can be one and be arranged to the oscillator that the control of the aanalogvoltage of two signals with 90 degree phase relations is provided.Under another situation, if this frequency mixer is realized (that is, handling digital PAM signal) with digital form, this oscillator can be a controlled discrete time oscillator DTO.

Fig. 2 represents to be implemented a kind of known second-order loop filter circuit of the filter 14 that is used for Fig. 1.This filter is represented as and utilizes that digital unit is realized and the data mode operation of hypothesis to take a sample.In Fig. 2, be added to first and

second Calibration Circuit

23 and 24 of utilizing weight coefficient K1 and K2 weighted error signal respectively from the error signal e of phase detectors.The error signal sample value that is weighted in parts 23 postpones a sample period and delivers to adder 20 in delay unit 22.Be added to an integrator by the error signal sample value of being demarcated in parts 24, it comprises signal summing circuit or adder 25 and is coupling in a sample period delay unit 26 between one of the output port of adder 25 and its input port.Be applied to second input port of adder 20 through limiter circuitry 27 from the output signal of integrator.

Design of Filter technical professional will be appreciated that when circuit path provided a longer-term limited signal trend response down, last circuit path provided the response of a transient signal variation.Under stable state, phase error is zero or very little, and the transfer function H (Z) of Fig. 2 circuit can be by following The Representation Equation:

H(Z)＝K1(Z ^-1)＋K2/(1－Z ^-1) (1)

Wherein K1 and K2 are the fixed weighting coefficients.Equation (1) supposes that the output of integrator is enough little, is unlikely to cause signal limiter.But in, if having obvious noise in the signal that receives, the output that this noise will have influence on error signal and integrator may be limited.Suppose that this amplitude limit value is K3.When amplitude limit occurring, the transfer function of this loop filter becomes:

H(Z)＝K1(Z ^-1)＋K3 (2)

The amplitude limit effect has reduced the undesirable influence that causes owing to signal noise, such as spurious lock.But when system when limiter mode is operated, K3 will preponderate usually, cause undesirable slow-response time.

The present invention attempts to comprise some useful aspects of the influence that comprises amplitude limiter in the loop filter, and does not cause more undesirable aspects.

The present invention is a kind of high-order phase loop filter, and this filter comprises by signal summing circuit or adder and is arranged in the output of this adder and the integrator that the delay unit in the feedback control loop between input port is formed.Treat that the signal of filtering is fed to second input port of this adder.A detector is coupled to the output of this adder, and the detectability amplitude when this value detected the time, stipulates that this detector resets at currency in the delay unit of integrator for such as a fixed value of zero.The order of this delay unit moment ground reduction filter and the response time of quickening system under the situation of noise reset.

To understand more easily with reference to each accompanying drawing the present invention, wherein:

Fig. 1 is the block diagram of the phase-locked system of prior art;

Fig. 2 is the block diagram of a kind of known loop filter that can implement to be used for the loop filter 14 of Fig. 2;

Fig. 3 and 5 is block diagrams of implementing loop filter of the present invention; With

Fig. 4 implements the block diagram that carrier wave of the present invention recovers phase correction system.

Fig. 3 with reference to explanation one exemplary embodiment of the present invention.In the figure, be applied to first and

second Calibration Circuit

23 and 24 of K1 of utilization value respectively and K2 calibrated error signal from an error signal of the phase detectors 10 of for example Fig. 1.The exemplary value of K1 and K2 is 1/4 and 1/32.The signal by coefficient 1/4 weighting from Calibration Circuit 23 is coupled to delay unit 22.This error signal is assumed that it is data-signal and 22 delay sampling periods of this signal of delay unit of a sampling.The signal that delayed parts 22 postpone is coupled to the first input end mouth of adder 20.

The signal by calibration coefficient K2 weighting from Calibration Circuit 24 is applied to an integrating circuit that comprises signal summing circuit or adder 25 and delay unit 31.Delay unit 31 will from the signal of adder 25 output and postpone a sample period and apply this delay and to an input port of adder 25.From the output of adder 25 be coupled to second input port of adder 20.From the output of adder 25 with also be applied to detector 30, whenever that provide by adder 25 and when surpassing a predetermined limits value, this detector provides a reset signal.The reset signal that (for 16 adders, this limits value can be ± 4000 hexadecimals) provided by detector 30 is coupled, and the value in the delay unit 31 is reset to such as a zero predetermined reset value.

For the error signal of little value, the transfer function of the loop filter of Fig. 3 is described by equation 1.When signal noise made one of integrator generation surpass the output valve of this limiting value, transfer function was provided by following formula:

H(Z)＝K1(Z ^-1)＋K2 (3)

But, should be noted that COEFFICIENT K 1 significantly greater than COEFFICIENT K 2, so this loop filter effectively, temporarily returns to one first rank loop.That is to say that second of the right side of equation (3) can be left in the basket.When this loop filter returns to the first rank loop, exist under the situation of noise, it will have locking time faster inherently.In addition, this integrator to one little value that resets reduces because the build-up effect that signal noise causes.

In Fig. 3, detector 30 is represented as a limiter and in fact can utilizes the suitable part of limiter circuitry to realize.But, detector 30 is a feature with a window comparator preferably, and this comparator provides an output signal that for example has zero first state for all input values that are applied between second output state that appears at limit specified and for example logic/state.

The system of Fig. 1 wants the system of the sort of type of emending frequency and phase error.Fig. 4 represents only to be used for the system of phase calibration error.In Fig. 4 with Fig. 1-3 in identical parts label represent to be similarly and carry out similar effect.Phase detectors 10A can be the form that the phase detectors that are similar to Fig. 1 maybe can be taked any other known phase detectors.Signal at the phasing of the output of frequency mixer 11 is utilizable.Loop filter is similar to loop filter shown in Figure 3, except second Calibration Circuit 244 is that cascade is connected with first Calibration Circuit 23, rather than is in parallel shown in Fig. 2 and 3.The weight coefficient K7 of second Calibration Circuit 244 is arranged to K1 and takes advantage of K7 to equal K2.

QAM signal and the hypothesis frequency mixer 11 of considering the input that is applied to frequency mixer 11 as complex multipliers.The QAM signal has same-phase I and quadrature phase Q component.Can obtain each calibrated component signal I according to relation given below _cAnd Q _c:

I _c＝ICOS(θ)＋QSIN(θ) (4)

Q _c＝QC0S(θ)－ISIN(θ) (5)

If represent each value of the complex multiplier of COS (θ) and SIN (θ) to be applied to frequency mixer from loop filter, then complex multiplier 11 will produce the component signal of phasing inherently.Value COS (θ) and SIN (θ) are the orthogonal representation of the error signal of filtering.

Promptly be coupled to an input port of subtracter 50 from the signal of adder 20 from loop filter.Its another input port is coupled in the output of subtracter through a sample period delay unit 51.Subtracter 50 and delay unit 51 be combined to form a difference engine, this difference engine is actually a band pass filter, only can be by the variation of phase error.This phase error of bandpass filtering (difference) be coupled to the look-up table 52 that can realize by read-only memory or ROM.It is right corresponding to the value of COS (θ) and SIN (θ) value that this ROM provides, and wherein θ is provided by following formula:

θ＝{1/(1＋Z ^-1)}{K1(Z ^-1)＋K2/(1－Z ^-1)}{ε} (6)

Fig. 5 is to use the example of the relative Fig. 3 and the higher-order loop filter of 4 illustrated and the identical restriction notions of describing.Dotted arrow between limiter/detector 301 and the delay unit 312 will represent that this connection is to choose wantonly.

Claims

1. in a kind of carrier recovery circuit, this circuit comprises by signal summing circuit (25) and is coupling in the output port of described signal summing circuit and signal storage parts (31) between the input port form the loop filter (14) that integrator is formed, a kind of improvement comprises: the checkout gear (30) that is coupled to described signal summing circuit, when be used to detect and surpass predetermined restriction with output from described signal summing circuit, and device (30,31) in response to surpass this restriction and detection, be used in described memory unit reset signal to a predetermined value.

2. circuit according to claim 1, wherein response and detection surpass the described device of this restriction, reset signal is to null value in described memory unit.

3. loop filter that is used for phase-locked loop comprises:

An error signal source (10);

An adder (20) has first and second inputs and an output, is used to provide the error signal through filtering;

First circuit path (22,23) is coupling between described first input end and the described source, and comprises first a signal scaling circuit and a delay unit that is connected in series;

Second circuit passage (24,25,31) is coupling between described second input and the described source, and comprises a signal integration device, and described integrator comprises:

A signal summing circuit (25) has the another one signal lag part that is coupling between its input port and the output port;

A detector (30), be used to detect when provide by described signal summing circuit and surpass predetermined value and when described and be used to reset described another one delay unit (31) to a predetermined value when surpassing this value of being scheduled to.

4. loop filter according to claim 3, wherein said detector reset described another one delay unit to null value.

5. equipment that comprises a loop filter comprises:

A signal source that comprises carrier component;

Have a multiplier of the first input end that is coupled to described source, have second input and output;

The phase calculation device is coupled to the output of described multiplier, is used for providing on its output the phase error signal of phase difference of the carrier phase of a described carrier component of indication and an expectation;

An adder with first, second input and an output is used to provide the error signal of filtering;

First circuit path is coupling between the described first input end and described output of described phase calculation device, comprises first signal scaling circuit and the delay unit that is connected in series;

The second circuit passage is coupling in described second input and the described output of described phase calculation device, and comprises secondary signal Calibration Circuit and the signal integration device that is connected in series, and described integrator comprises:

A signal summing circuit has the other signal lag part that is coupling between its output port and the input port;

When a detector is used to detect by being that the signal summing circuit provides and having surpassed predetermined value, and when described and when surpassing this predetermined value, described other delay unit to a predetermined value resets;

The device that comprises the difference engine between second input of the output that is coupling in described adder and described multiplier.