CN114168193A

CN114168193A - Instruction processing method, device and system and intelligent equipment

Info

Publication number: CN114168193A
Application number: CN202010957662.3A
Authority: CN
Inventors: 郭任
Original assignee: Pingtouge Shanghai Semiconductor Co Ltd
Current assignee: Hangzhou C Sky Microsystems Co Ltd
Priority date: 2020-09-10
Filing date: 2020-09-10
Publication date: 2022-03-11

Abstract

The embodiment of the invention discloses an instruction processing method, which comprises the following steps: executing a target instruction sequence comprising a stake point instruction, and performing exception handling when the stake point instruction is executed; writing a target instruction corresponding to the stub instruction into an instruction cache register; after exception handling is finished, reading a target instruction from an instruction cache register; and single-stepping the target instruction. The embodiment of the invention also discloses a corresponding device, computing equipment, a system on a chip and intelligent equipment.

Description

Instruction processing method, device and system and intelligent equipment

Technical Field

The present invention relates to the field of processors, and in particular, to a method, an apparatus, a system, and an intelligent device for processing an instruction.

Background

In the field of processors, to debug instructions, a stub detection method is generally used. Currently, a widely used stub detection method, such as Kprobe/Uprobe technology, replaces an instruction at a stub with a stub instruction, copies the replaced instruction to another memory address, and subsequently reads and executes the instruction from another memory address in a simulated execution or single-step execution manner. Obviously, since the instructions are executed by different addresses and different rights, single-step execution cannot effectively simulate part of the instructions in a kernel mode, and only software simulation can be adopted. But the use of software emulation increases the complexity of software design and the difficulty of CPU microarchitecture maintenance across instruction sets.

Therefore, it is desirable to provide a more advanced instruction processing scheme to solve the problem that a part of instructions cannot be effectively simulated in the conventional single-step execution mechanism.

Disclosure of Invention

To this end, embodiments of the present invention provide an instruction processing method, apparatus, system, and intelligent device, so as to solve or at least alleviate the above problems.

According to an aspect of an embodiment of the present invention, there is provided an instruction processing method including: executing a target instruction sequence comprising a stake point instruction, and performing exception handling when the stake point instruction is executed; writing a target instruction corresponding to the stub instruction into an instruction cache register; after exception handling is finished, reading a target instruction from an instruction cache register; and single-stepping the target instruction.

Optionally, in the method according to the embodiment of the present invention, the method further includes: in response to executing the to-stake instruction, a stake point enable flag in the state control register is configured to be active.

Optionally, in the method according to the embodiment of the present invention, writing a target instruction corresponding to the stub instruction into the instruction cache register includes: responding to the detected effective pile point enabling mark, and acquiring a target instruction corresponding to the pile point instruction; and writing the target instruction into the instruction cache register.

Optionally, in the method according to the embodiment of the present invention, the method further includes: before executing the target instruction sequence, replacing the target instruction at the pile inserting position in the original instruction sequence with a pile point instruction to obtain the target instruction sequence.

Optionally, in the method according to the embodiment of the present invention, the method further includes: recording the corresponding relation between the pile inserting position and the target instruction; and acquiring a target instruction corresponding to the pile point instruction, including: and determining the target instruction originally positioned at the pile inserting position of the pile point instruction based on the corresponding relation.

Optionally, in the method according to the embodiment of the present invention, the method further includes: after the target instruction is single-stepped, the stub enable flag is configured to be invalid.

Optionally, in the method according to the embodiment of the present invention, configuring the stub enable flag in the status control register to be valid includes: setting a stake point enabling mark in a state control register to be 1; and configuring the stub enable flag in the state control register to be invalid, including: the peg point enable flag in the status control register is set to 0.

Optionally, in the method according to the embodiment of the present invention, the exception handling includes: the object associated with the stub instruction is executed.

Optionally, in the method according to the embodiment of the present invention, the method further includes: before exception handling, saving the current running state; and restoring the saved running state after the exception processing is finished.

Optionally, in the method according to an embodiment of the present invention, the stub enable flag is a single-step enable flag.

Optionally, in the method according to an embodiment of the present invention, the stub instruction includes a breakpoint instruction or a jump instruction.

According to another aspect of the embodiments of the present invention, there is provided a program debugging method, including: setting a pile inserting position in an original instruction sequence of a program; replacing a target instruction at the pile inserting position in the original instruction sequence with a pile point instruction to obtain a target instruction sequence; starting a program for instructing the processing device to execute a target instruction sequence; and when the stub point instruction is executed, exception handling is carried out, the instruction processing device writes a target instruction corresponding to the stub point instruction into the instruction cache register, and after exception handling is finished, the target instruction is read from the instruction cache register, and the target instruction is executed in a single step mode.

According to another aspect of the embodiments of the present invention, there is provided an instruction processing apparatus including: an instruction cache register adapted to register instructions; the instruction execution unit is suitable for executing a target instruction sequence comprising a stake point instruction, and when the stake point instruction is executed, exception handling is carried out; the register configuration unit is suitable for writing a target instruction corresponding to the stub instruction into the instruction cache register; the instruction reading unit is suitable for reading a target instruction from the instruction cache register after exception handling is finished; and a single-step execution unit adapted to execute the target instruction in a single step.

Optionally, in the apparatus according to the embodiment of the present invention, the apparatus further includes: a state control register including a stake point enable flag; the register configuration unit is further adapted to configure the stub enable flag to be active in response to execution of the to-stub instruction.

Optionally, in the apparatus according to the embodiment of the present invention, the register configuration unit is further adapted to, in response to detecting a valid stub enable flag, obtain a target instruction corresponding to the stub instruction, and write the target instruction into the instruction cache register.

Optionally, in the apparatus according to the embodiment of the present invention, the instruction execution unit is further adapted to replace the target instruction located at the instrumentation position in the original instruction sequence with the stub instruction before executing the target instruction sequence, so as to obtain the target instruction sequence.

Optionally, in the apparatus according to the embodiment of the present invention, the instruction execution unit is further adapted to record a corresponding relationship between the instrumentation position and the target instruction; the register configuration unit is further adapted to determine a target instruction originally located at the position of the instrumentation point where the instrumentation point instruction is located, based on the corresponding relationship.

Optionally, in the apparatus according to an embodiment of the present invention, the register configuration unit is further adapted to configure the stub enable flag to be invalid after the target instruction is executed in a single step.

Optionally, in the apparatus according to the embodiment of the present invention, the register configuration unit is adapted to set the stub enable flag in the state control register to 1, and is further adapted to set the stub enable flag in the state control register to 0.

Optionally, in the apparatus according to an embodiment of the present invention, the instruction execution unit is further adapted to execute an object associated with the stub instruction.

Optionally, in the apparatus according to the embodiment of the present invention, the instruction execution unit is further adapted to save the current running state before performing the exception handling, and to restore the saved running state after completing the exception handling.

Optionally, in the apparatus according to an embodiment of the present invention, the stub point enable flag is a single step enable flag.

Optionally, in the apparatus according to an embodiment of the present invention, the stub instruction includes a breakpoint instruction or a jump instruction.

According to another aspect of the embodiments of the present invention, there is provided a program debugging apparatus including: the pile point setting unit is suitable for setting pile inserting positions in an original instruction sequence of the program and replacing target instructions positioned at the pile inserting positions in the original instruction sequence with pile point instructions to obtain a target instruction sequence; a program starting unit adapted to start a program for instructing the processing device to execute the target instruction sequence; and the exception handling unit is suitable for carrying out exception handling when the stub point instruction is executed, the instruction processing device writes a target instruction corresponding to the stub point instruction into the instruction cache register, and reads the target instruction from the instruction cache register after the exception handling is finished, and the target instruction is executed in a single step mode.

According to another aspect of an embodiment of the present invention, there is provided a computing device including: a memory; one or more processors comprising an instruction processing apparatus according to an embodiment of the present invention; and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the one or more programs including instructions for performing the program debugging method according to the embodiments of the present invention.

According to another aspect of the embodiments of the present invention, there is provided a system on a chip including an instruction processing apparatus according to an embodiment of the present invention.

According to another aspect of the embodiments of the present invention, there is provided a smart device including the system on chip according to the embodiments of the present invention.

According to the instruction processing scheme of the embodiment of the invention, the target instruction replaced by the stub instruction is written into the instruction cache register by adding the stub enable mark and the instruction cache register, so that the processor (such as instruction processing apparatus 200) can read the target instruction from the instruction cache register and execute the target instruction after the stub exception processing is completed, and normally jump to the address space of the target instruction sequence, rather than jumping to another address space (e.g., another memory address in Kprobe/Uprobe technology), stepping the target instruction with an out-of-address-space privilege, therefore, single-step execution of the target instruction under the same address space and the same authority is realized, the problem that a traditional single-step execution mechanism cannot effectively simulate part of instructions under the condition of different address spaces and different authorities is solved, and the problems that software design complexity is increased and the CPU micro-architecture maintenance difficulty of a cross-instruction set and the like possibly caused by software simulation are solved.

The foregoing description is only an overview of the technical solutions of the embodiments of the present invention, and the embodiments of the present invention can be implemented according to the content of the description in order to make the technical means of the embodiments of the present invention more clearly understood, and the detailed description of the embodiments of the present invention is provided below in order to make the foregoing and other objects, features, and advantages of the embodiments of the present invention more clearly understandable.

Drawings

To the accomplishment of the foregoing and related ends, certain illustrative aspects are described herein in connection with the following description and the annexed drawings, which are indicative of various ways in which the principles disclosed herein may be practiced, and all aspects and equivalents thereof are intended to be within the scope of the claimed subject matter. The above and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description read in conjunction with the accompanying drawings. Throughout this disclosure, like reference numerals generally refer to like parts or elements.

FIG. 1 shows a schematic diagram of a processor 100 according to one embodiment of the invention;

FIG. 2 shows a schematic diagram of an instruction processing apparatus 200 according to one embodiment of the invention;

FIG. 3 illustrates a variation of the instruction sequence according to one embodiment of the invention;

FIG. 4 illustrates a flow diagram of an instruction processing method 400 according to one embodiment of the invention;

FIG. 5 shows a schematic diagram of a computing device 500, according to one embodiment of the invention;

FIG. 6 illustrates a flow diagram of a method 600 for debugging a program according to one embodiment of the invention;

FIG. 7 is a diagram illustrating a program debugging apparatus 700 according to an embodiment of the present invention; and

FIG. 8 shows a schematic diagram of a system on a chip (SoC)800, according to one embodiment of the invention.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

FIG. 1 shows a schematic diagram of a processor 100 according to one embodiment of the invention. In some embodiments, processor 100 may be, in addition to a processor, a processor core of a multi-core processor or a processing element in an electronic system.

As shown in FIG. 1, processor 100 includes an instruction fetch unit 130. Instruction fetch unit 130 may fetch instructions to be processed from cache 110, memory 120, or other sources (e.g., instruction cache register 212 described below) and send to decode unit 140. Instructions fetched by instruction fetch unit 130 include, but are not limited to, high-level machine instructions, macro instructions, or the like. Processor 100 performs certain functions by executing these instructions.

Decode unit 140 receives incoming instructions from instruction fetch unit 130 and decodes the instructions to generate low-level micro-operations, microcode entry points, micro-instructions, or other low-level instructions or control signals that reflect or are derived from the received instructions. The low-level instructions or control signals may operate at a low level (e.g., circuit level or hardware level) to implement the operation of high-level instructions. Decoding unit 140 may be implemented using a variety of different mechanisms. Examples of suitable mechanisms include, but are not limited to, microcode, look-up tables, hardware implementations, Programmable Logic Arrays (PLAs). The present invention is not limited to various mechanisms for implementing decoding unit 140, and any mechanism that can implement decoding unit 140 is within the scope of the present invention.

These decoded instructions are then sent to execution unit 150 and executed by execution unit 150. Execution unit 150 includes circuitry operable to execute instructions. Execution unit 150, when executing these instructions, receives data input from and generates data output to register set 170, cache 110, and/or memory 120.

In one embodiment, the register set 170 includes architectural registers, also referred to as registers. Unless specified otherwise or clearly evident, the phrases architectural register, register set, and register are used herein to refer to a register that is visible (e.g., software visible) to software and/or programmers and/or that is specified by a macro-instruction to identify an operand. These registers are different from other non-architected registers in a given microarchitecture (e.g., temporary registers, reorder buffers, retirement registers, etc.).

According to one embodiment, the register set 170 may include a set of vector registers 175, where each vector register 175 may be 512 bits, 256 bits, or 128 bits wide, or may use a different vector width. Optionally, the register set 170 may also include a set of general purpose registers 176. General purpose registers 176 may be used when execution unit 150 executes instructions.

Execution unit 150 may include a number of specific instruction execution units 150a, 150b … 150c, etc., such as, for example, a vector arithmetic unit (ALU), an integer unit, a floating point unit, a memory execution unit, etc., and may execute different types of instructions, respectively.

To avoid obscuring the description, a relatively simple processor 100 has been shown and described. It should be understood that processor 100 may have different forms, for example, other embodiments of processor 100 may have multiple cores, logical processors, or execution engines.

In an embodiment according to the invention, the processor 100 is implemented as an instruction processing apparatus 200 and is configured to perform an instruction processing method 400 according to an embodiment of the invention.

FIG. 2 shows a schematic diagram of an instruction processing apparatus 200 according to one embodiment of the invention. It should be noted that in fig. 2, the various components in instruction processing apparatus 200 are logically divided according to the operations to be implemented in instruction processing apparatus 200, these logical divisions being schematic and may be re-divided according to actual physical layout and business needs without departing from the scope of the present invention. The instruction processing method 400 executed in the instruction processing apparatus 200 may be performed by the respective components shown in fig. 2. When the components shown in fig. 2 are reassembled and divided, the corresponding method steps may be performed according to the logic carried by the new component without departing from the scope of the present invention.

As shown in FIG. 2, instruction processing apparatus 200 includes a state control register 211, an instruction cache register 212, an instruction execution unit 220, a register configuration unit 230, an instruction fetch unit 240, and a single-step execution unit 250.

The state control register 211 is adapted to control and/or store the state of the instruction processing apparatus 200, and includes a stub enable flag for enabling a stub instruction execution mechanism according to an embodiment of the present invention (which will be described in detail later). In some embodiments, the status control register 211 may be a 16-bit or 32-bit register, and the stub enable flag is a bit in the status control register 211. The instruction cache register 116 may be a 16-bit, 32-bit, or 64-bit register adapted to register instructions with the stub instruction execution mechanism enabled.

The instruction execution unit 220 is adapted to execute a target instruction sequence comprising a stake point instruction at a stake insertion position. The peg position (also referred to as a peg point) may be any position in the original instruction sequence that is of interest to the user (for example, to be probed or debugged), and is set by the user in the original instruction sequence in advance. The target instruction sequence may be obtained by replacing an instruction at the instrumentation position in the original instruction sequence with a stake point instruction, that is, the stake point instruction replaces an instruction at the instrumentation position in the original instruction sequence (hereinafter referred to as a target instruction). When the instruction processing device 200 executes the stub instruction, an exception is generated, and the corresponding exception processing code is skipped to execute, thereby completing the functions of tracking or debugging the program. Specifically, the stub instruction may be a breakpoint instruction (for example, a BKPT instruction under an ARM architecture, an int3 instruction under an x86 architecture) or a jump instruction, and the specific type of the stub instruction is not limited in the embodiment of the present invention, and any instruction that can implement similar functions is within the protection scope of the present invention.

In some embodiments, when a program is to be traced or debugged, a user is allowed to specify any location in the original instruction sequence of the program (the original instruction sequence is not modified at all, and does not include stub instructions) as an instrumented location. After the instrumentation position is set, the target instruction at the instrumentation position in the original instruction sequence may be replaced by the instrumentation instruction, so as to obtain the target instruction sequence.

For example, in fig. 3, the instruction sequence shown on the left side is the original instruction sequence, which has not been modified by the instruction processing device 200 any more, and does not include a stub instruction. Next, the user designates the position of instruction "inst 3" in the original instruction sequence as an instrumented position, and in this case, instruction processing apparatus 200 replaces target instruction "inst 3" located at the instrumented position with a stake point instruction, resulting in the target instruction sequence shown on the right.

According to an embodiment of the present invention, for example, before executing the target instruction sequence, the instruction execution unit 220 may record the instrumentation position, the replaced target instruction located at the instrumentation position, and the corresponding relationship between the two for subsequent query. For example, the recording may be made in a data structure.

When the instruction execution unit 220 executes a stake point instruction, an exception (the exception is referred to as a stake point exception) is generated. It should be appreciated that an exception is a synchronization event, which is a response of the processor to certain conditions detected during execution of an instruction (e.g., certain instructions are executed). Exceptions may cause the processor to change the order of instructions executed, for example, the processor may suspend execution of the current instruction sequence, branch to exception handling, and execute the corresponding exception handling code. The exception generated by executing the stub instruction may be referred to as a stub exception.

Instruction execution unit 220 may handle the stub exception. In some embodiments, handling stub exceptions includes, but is not limited to, executing an object associated with the stub instruction (which may be an object such as a function and may be configured by a user), viewing the values of variables, halting execution of certain instructions, and the like. The invention is not limited in this regard.

Before handling the stub exception, the instruction execution unit 220 may also save the current running state, for example, an address in a Program Counter (PC) for recovery after the stub exception is handled. It should be appreciated that the processor must determine the address of the next instruction to be executed in order to ensure proper execution when executing a sequence of instructions. The program counter PC is the element used for this purpose, which registers the address of the next instruction to be executed. Typically, instructions are executed sequentially. Before starting execution, the address of the first instruction is always written into the program counter PC. When a first instruction is fetched for execution, the contents of the program counter PC are automatically incremented indicating the address of the next instruction to be executed. Therefore, at this time, the program counter PC registers the address of the next instruction in the target instruction sequence of the currently executed stub instruction.

Further, when executing the peg-point to instruction, the register configuration unit 230 connected to the instruction execution unit 220 is adapted to configure the peg-point enable flag in the state control register 211 to be active in response to executing the peg-point to instruction to enable the peg-point instruction execution mechanism. Normally, setting the stub enable flag to 1 is valid, indicating that the stub instruction execution mechanism is enabled. Setting the stub enable flag to 0 is invalid, indicating that the stub instruction execution mechanism is not enabled.

It should be noted that the state control register 211 may also include a single step enable flag that is used to enable a conventional single step execution mechanism. As mentioned in the background, it is currently possible to replace an instruction at a probe point with a breakpoint instruction and copy the replaced instruction to another memory address. When the processor executes a breakpoint instruction, an exception is generated (the exception is called a breakpoint exception), breakpoint exception handling is entered, and the single step enable flag is simultaneously configured to be active to enable the conventional single step execution mechanism.

In the conventional single-step execution mechanism, another memory address storing the replaced instruction needs to be written into the program counter PC. Thus, when the breakpoint exception is completed, the processor can jump to another memory address where the replaced instruction is stored, and step the instruction. It will be appreciated that a single-step exception may be generated after a single-step instruction (the exception generated after a single-step instruction is referred to as a single-step exception) and proceed to single-step exception handling.

Since the stub instruction execution mechanism according to the embodiment of the present invention involves single-step execution of an instruction (which will be described in detail later), in some embodiments, a single-step enable flag may be directly used as the stub enable flag, in which case the stub instruction execution mechanism according to the embodiment of the present invention replaces the conventional single-step execution mechanism. In other embodiments, a stub enable flag may be separately added, the stub instruction execution mechanism according to an embodiment of the present invention is enabled by configuring the stub enable flag, and the conventional single-step execution mechanism is enabled by configuring the single-step enable flag.

The stub instruction execution mechanism according to an embodiment of the present invention is described in detail below.

In response to detecting a valid stub enable flag (i.e., in a case that the stub instruction execution mechanism is enabled), the register configuration unit 230 obtains a target instruction corresponding to the currently executed stub instruction, and writes the target instruction into the instruction cache register 212.

Specifically, the register configuration unit 230 may determine, based on a correspondence between a stub instruction and a target instruction recorded before, a target instruction originally located at an insertion position where the stub instruction is located, and obtain the target instruction.

After the stub exception is processed, the instruction execution unit 220 may also restore the running state saved before the stub exception is processed, for example, the previously saved address may be rewritten into the program counter PC by a return instruction (e.g., a ret instruction). At this time, since the target instruction is not yet executed, according to the embodiment of the present invention, the instruction execution unit 220 temporarily does not fetch and execute the instruction pointed by the address, i.e. the instruction next in the target instruction sequence (which is also the instruction next in the original instruction sequence).

The instruction fetch unit 240 is coupled to the instruction execution unit 220 and adapted to fetch a target instruction from the instruction cache register 212 after the stub exception is processed and when a valid stub enable flag is detected, the target instruction is single-stepped by the single-step execution unit 250 coupled to the instruction fetch unit 240.

A single-step exception is generated after the target instruction is executed in a single step, and single-step exception handling is performed. Similarly, prior to processing the single step exception, the current running state may be saved, such as saving the address in the program counter PC. After the single-step exception is handled, single-step execution unit 250 may restore the running state saved prior to handling the single-step exception, such as by rewriting the previously saved address into program counter PC via a return instruction. Because the instruction pointed by the program counter PC is not fetched and executed, the address in the program counter PC does not change, and the address of the next instruction of the stub instruction in the target instruction sequence is still the address of the next instruction of the stub instruction. Thus, the instruction execution unit 220 may resume executing the target instruction sequence, i.e., continue executing the remaining instructions downward from the execution stub instruction at the next instruction in the target instruction sequence.

Furthermore, in some embodiments, after single-stepping the target instruction, the register configuration unit 230 is further adapted to configure the stub enable flag to be invalid to disable the stub instruction handling mechanism to avoid generating unnecessary stub exceptions again.

FIG. 4 shows a flow diagram of an instruction processing method 400 according to one embodiment of the invention. As shown in fig. 4, the instruction processing method 400 starts at step S410 and is suitable for execution in the instruction processing apparatus 200.

In step S410, the target instruction sequence is executed, for example, the execution is started at the instruction of the user.

The target instruction sequence includes a stake point instruction at the stake insertion position that replaces the target instruction at the stake insertion position in the original instruction sequence. As shown in fig. 3, for example, if the user specifies the position of the instruction "inst 3" in the original instruction sequence as the instrumentation position, the target instruction "inst 3" is replaced by the stub instruction in the original instruction sequence to obtain the target instruction sequence.

According to one embodiment of the invention, the instrumentation position, the replaced target instruction at the instrumentation position and the corresponding relationship between the two can be recorded for subsequent query.

When the stake point instruction is executed, an exception is generated, and in step S420, the exception is processed. Specifically, the current running state may be saved first, so that the exception is recovered after the exception is processed. The exception is then handled, such as by executing an object associated with the stub instruction, which may be configured by the user. After the exception processing is completed, the operation state before the exception processing is restored based on the saved operation state. For example, the previously saved address is rewritten into the program counter PC by a return instruction, i.e. a jump to the next instruction of the stub instruction in the target instruction sequence, but this time the instruction is not executed.

Meanwhile, in step S430, in response to executing the to-stake point instruction, the stake point enable flag in the state control register 211 is configured to be valid to enable the stake point instruction execution mechanism. Next, in step S440, in response to detecting a valid stub enable flag, a target instruction corresponding to the stub instruction may be obtained, and the target instruction is written into the instruction cache register 212.

Specifically, the target instruction originally located at the pile inserting position where the pile point instruction is located may be determined based on the correspondence between the pile point instruction and the target instruction recorded before.

After the exception processing is completed, if the stub instruction execution mechanism is enabled, the target instruction may be read from the instruction cache register 212 in step S450, and executed in a single step in step S460.

As will be appreciated, after a target instruction is executed in a single step, a single step exception is generated and processed. According to an embodiment of the present invention, before the single step exception processing, the current running state may be saved, and the execution may be resumed after the single step exception processing, so as to resume executing the target instruction sequence, that is, to continue to execute the rest of instructions downwards from the execution of the stub instruction at the next instruction in the target instruction sequence.

Finally, after single-stepping the target instruction, the stub enable flag may also be configured to be disabled to disable the stub instruction handling mechanism.

For the detailed processing logic and implementation procedure of each step in the instruction processing method 400, reference may be made to the foregoing description of the instruction processing apparatus 200 in conjunction with fig. 1-3, and details are not repeated here.

In summary, the instruction processing scheme according to the embodiment of the present invention writes the target instruction replaced by the stub instruction into the instruction cache register by adding the stub enable flag and the instruction cache register, so that the processor (such as instruction processing apparatus 200) can read the target instruction from the instruction cache register and execute the target instruction after the stub exception processing is completed, and normally jump to the address space of the target instruction sequence, rather than jumping to another address space (e.g., another memory address in Kprobe/Uprobe technology), stepping the target instruction with an out-of-address-space privilege, therefore, single-step execution of the target instruction under the same address space and the same authority is realized, the problem that a traditional single-step execution mechanism cannot effectively simulate part of instructions under the condition of different address spaces and different authorities is solved, and the problems that software design complexity is increased and the CPU micro-architecture maintenance difficulty of a cross-instruction set and the like possibly caused by software simulation are solved.

A program debugging apparatus to which the instruction processing scheme according to an embodiment of the present invention is applied will be described below, and the program debugging apparatus can be implemented as a computing device as described below.

FIG. 5 shows a schematic diagram of a computing device 500, according to one embodiment of the invention. As shown in FIG. 5, in a basic configuration 502, computing device 500 typically includes a system memory 506 and one or more processors 504. A memory bus 508 may be used for communicating between the processor 504 and the system memory 506.

Depending on the desired configuration, processor 504 may be any type of processor, including but not limited to: the processor 504 may include one or more levels of cache, such as a level one cache 510 and a level two cache 512, a processor core 514, and registers 516. the example processor core 514 may include an Arithmetic Logic Unit (ALU), a Floating Point Unit (FPU), a digital signal processing core (DSP core), or any combination thereof Flash memory, etc.) or any combination thereof. System memory 506 may include an operating system 520, one or more programs 522, and program data 524. In some embodiments, the program 522 may be arranged to execute instructions on the operating system by the one or more processors 504 using the program data 524.

Computing device 500 may also include an interface bus 540 that facilitates communication from various interface devices (e.g., output devices 542, peripheral interfaces 544, and communication devices 546) to the basic configuration 502 via the bus/interface controller 530. The example output device 542 includes a graphics processing unit 548 and an audio processing unit 550. They may be configured to facilitate communications with various external devices, such as a display or speakers, via the one or more a/V ports 552. Example peripheral interfaces 544 may include a serial interface controller 554 and a parallel interface controller 556, which may be configured to facilitate communications with external devices such as input devices (e.g., keyboard, mouse, pen, voice input device, touch input device) or other peripherals (e.g., printer, scanner, etc.) via one or more I/O ports 558. An example communication device 546 may include a network controller 560, which may be arranged to facilitate communications with one or more other computing devices 562 over a network communication link via one or more communication ports 564.

A network communication link may be one example of a communication medium. Communication media may typically be embodied by computer readable instructions, data structures, program modules, and may include any information delivery media, such as carrier waves or other transport mechanisms, in a modulated data signal. A "modulated data signal" may be a signal that has one or more of its data set or its changes made in such a manner as to encode information in the signal. By way of non-limiting example, communication media may include wired media such as a wired network or private-wired network, and various wireless media such as acoustic, Radio Frequency (RF), microwave, Infrared (IR), or other wireless media. The term computer readable media as used herein may include both storage media and communication media.

Computing device 500 may be implemented as a server, such as a database server, an application server, a WEB server, and the like, or as a personal computer including both desktop and notebook computer configurations. Of course, computing device 500 may also be implemented as part of a small-sized portable (or mobile) electronic device.

In an embodiment in accordance with the invention, computing device 500 is implemented as program debugging apparatus 700. Among other things, one or more processors 504 comprise instruction processing apparatus 200 and are configured to perform instruction processing method 400 according to an embodiment of the present invention. The program 522 of the computing device 500 includes a plurality of instructions for executing the program debugging method 600 according to the embodiment of the present invention, and the program data 524 may further store the configuration data of the program debugging apparatus 700, and the like. Programs 522 of computing device 500 may also include other programs to be monitored, traced, or debugged using program debugging apparatus 700.

FIG. 6 shows a flow diagram of a method 600 for debugging a program, according to one embodiment of the invention. As shown in fig. 6, the program debugging method 600 starts at step S610 and is suitable for being executed in the program debugging apparatus 700.

In step S610, the instrumentation position is set in the original instruction sequence of the program, for example, at the instruction of the user. The instrumented location may be any location in the original instruction sequence that is of interest to the user.

Then, in step S620, the target instruction at the pile-inserting position in the original instruction sequence is replaced with the pile point instruction, so as to obtain the target instruction sequence. In addition, the position of the inserted pile, the target instruction and the corresponding relation between the two can be recorded.

After replacing the target instruction, in step S630, the program is started (e.g., under the instruction of the user) so as to instruct the processing apparatus 200 to execute the target instruction sequence. Wherein, when the peg point instruction is executed, an exception is generated. The exception may be handled in step S640. Specifically, an exception may be handled, for example, via instruction processing device 200 after saving the current operating state. Wherein handling the exception may include executing an object associated with the stub instruction, the object configurable by a user.

It should be noted that with the instruction processing apparatus 200 according to the embodiment of the present invention, the instruction processing apparatus 200 can configure the stub enable flag in the state control register 211 to be valid in response to execution of the to-stub instruction. In addition, the instruction processing device 200 also acquires the currently executed stub instruction in response to detecting the valid stub enable flagWhat is needed isThe corresponding target instruction is written into instruction cache register 212.

Thus, after the exception is handled, instruction processing apparatus 200 may read the target instruction from instruction cache register 212, and step through the target instruction.

For the detailed processing logic and implementation procedure of each step in the program debugging method 600, reference may be made to the related description of the instruction processing apparatus 200 and the instruction processing method 400 in conjunction with fig. 1 to 4, which is not described herein again.

Fig. 7 is a schematic diagram of a program debugging apparatus 700 according to an embodiment of the present invention. It should be noted that in fig. 7, the various components in the program debugging apparatus 700 are logically divided according to the operations to be implemented in the program debugging apparatus 700, and these logical divisions are schematic and can be re-divided according to the actual physical layout and business needs without departing from the scope of the present invention. Program debugging device method 600 performed in program debugging device 700 may be performed by the various components shown in FIG. 7. When the components shown in fig. 7 are reassembled and divided, the corresponding method steps may be performed according to the logic carried by the new component without departing from the scope of the present invention.

As shown in fig. 7, the program debugging apparatus 700 includes a stub setting unit 710, a program starting unit 720, and an exception handling unit 730.

The peg point setting unit 710 is adapted to set an insertion position in an original instruction sequence of the program, and replace a target instruction located at the insertion position in the original instruction sequence with a peg point instruction, resulting in a target instruction sequence.

The program initiation unit 720 is connected to the peg point setting unit 710 and is adapted to initiate a program for instructing the processing device 200 to execute a target instruction sequence. Wherein, when the peg point instruction is executed, an exception is generated.

The exception handling unit 730 connected to the program launch unit 720 is adapted to handle the exception. Specifically, an exception may be handled, for example, via instruction processing device 200 after saving the current operating state. Wherein handling the exception may include executing an object associated with the stub instruction, the object configurable by a user.

It should be noted that with the instruction processing apparatus 200 according to the embodiment of the present invention, the instruction processing apparatus 200 can configure the stub enable flag in the state control register 211 to be valid in response to execution of the to-stub instruction. In addition, the instruction processing device 200 also acquires the currently executed stub instruction in response to detecting the valid stub enable flagWhat is needed isThe corresponding target instruction is written into the instruction cache register 212, so that after the exception handling is finished, the instruction processing apparatus 200 can read the target instruction from the instruction cache register 212 to execute the target instruction in a single stepAnd (5) instructions.

For the detailed processing logic and implementation process of each unit in the program debugging apparatus 700, reference may be made to the related description of the instruction processing apparatus 200 and the instruction processing method 400 in conjunction with fig. 1-4, which is not described herein again.

It should be understood that instruction processing apparatus 200 may have different forms, such as may be implemented as a processor core, and that instruction processing method 400 may be performed in the processor core. Processor cores may be implemented in different processors in different ways. For example, a processor core may be implemented as a general-purpose in-order core for general-purpose computing, a high-performance general-purpose out-of-order core for general-purpose computing, and a special-purpose core for graphics and/or scientific (throughput) computing. While a processor may be implemented as a CPU (central processing unit) that may include one or more general-purpose in-order cores and/or one or more general-purpose out-of-order cores, and/or as a coprocessor that may include one or more special-purpose cores. Such a combination of different processors may result in different computer system architectures. In one computer system architecture, the coprocessor is on a separate chip from the CPU. In another computer system architecture, the coprocessor is in the same package as the CPU but on a separate die. In yet another computer system architecture, coprocessors are on the same die as the CPU (in which case such coprocessors are sometimes referred to as special purpose logic such as integrated graphics and/or scientific (throughput) logic, or as special purpose cores). In yet another computer system architecture, referred to as a system on a chip, the described CPU (sometimes referred to as an application core or application processor), coprocessors and additional functionality described above may be included on the same die.

FIG. 8 shows a schematic diagram of a system on a chip (SoC)800 according to one embodiment of the invention. As shown in fig. 8, the interconnect unit 802 is coupled to an applications processor 810, a system agent unit 812, a bus controller unit 814, an integrated memory controller unit 816, one or more coprocessors 820, a Static Random Access Memory (SRAM) unit 830, a Direct Memory Access (DMA) unit 832, and a display unit 840 for coupling to one or more external displays. Application processor 810 includes a set of one or more cores 811A-N and a shared cache unit 813. Coprocessor 820 includes integrated graphics logic, an image processor, an audio processor, and a video processor. In one embodiment, coprocessor 820 includes a special-purpose processor, such as, for example, a network or communication processor, compression engine, GPGPU, a high-throughput MIC processor, embedded processor, or the like.

In addition, the system-on-chip 800 described above may be included in a smart device to implement corresponding functions in the smart device, including but not limited to executing related control programs, performing data analysis, operations and processing, network communication, controlling peripherals in the smart device, and the like.

Such intelligent devices include specialized intelligent devices, such as mobile terminals and personal digital terminals, which include one or more systems-on-chips for data processing or controlling peripherals in the devices according to embodiments of the present invention.

Such smart devices also include specialized devices that are configured to implement specific functions, such as smart speakers, smart display devices, and the like. The sound box and the display device are controlled by the system on chip according to the embodiment of the invention, so that the sound box and the display device are endowed with additional functions of communication, perception, data processing and the like.

Such smart devices also include various IoT devices and AIoT devices. The devices comprise the system on chip according to the embodiment of the invention to process data, such as AI operation, data communication and transmission, so that denser and more intelligent device distribution is realized.

Such smart devices may also be used in vehicles, for example, may be implemented as on-board devices, or may be embedded in vehicles, providing data processing capabilities for intelligent driving of the vehicles.

Such smart devices may also be used in the home and entertainment fields, for example, as smart speakers, smart air conditioners, smart refrigerators, smart display devices, and the like. These devices include a system on chip according to the present invention for data processing and peripheral control, thereby enabling the intellectualization of home and entertainment devices.

In addition, such smart devices may also be used in industrial fields, for example, may be implemented as industrial control devices, sensing devices, IoT devices, AIoT devices, braking devices, and the like. The devices comprise the system on chip to process data and control peripheral devices, thereby realizing the intellectualization of industrial devices.

The above description of the smart device is only illustrative, and the smart device according to the present invention is not limited thereto, and all smart devices that can perform data processing using the system on chip according to the embodiment of the present invention are within the scope of the present invention.

Embodiments of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of these implementations. Embodiments of the invention may be implemented as computer programs or program code executing on programmable systems comprising at least one processor, a storage system (including volatile and non-volatile memory and/or storage elements), at least one input device, and at least one output device.

In the description provided herein, numerous specific details are set forth. It is understood, however, that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the invention, various features of the embodiments of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. However, the disclosed method should not be interpreted as reflecting an intention that: that is, the claimed embodiments of the invention require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of an embodiment of this invention.

Those skilled in the art will appreciate that the modules or units or components of the devices in the examples disclosed herein may be arranged in a device as described in this embodiment or alternatively may be located in one or more devices different from the devices in this example. The modules in the foregoing examples may be combined into one module or may be further divided into multiple sub-modules.

Those skilled in the art will appreciate that the modules in the device in an embodiment may be adaptively changed and disposed in one or more devices different from the embodiment. The modules or units or components of the embodiments may be combined into one module or unit or component, and furthermore they may be divided into a plurality of sub-modules or sub-units or sub-components. All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or elements of any method or apparatus so disclosed, may be combined in any combination, except combinations where at least some of such features and/or processes or elements are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.

Furthermore, those skilled in the art will appreciate that while some embodiments described herein include some features included in other embodiments, rather than other features, combinations of features of different embodiments are meant to be within the scope of and form different embodiments of the invention. For example, in the following claims, any of the claimed embodiments may be used in any combination.

Furthermore, some of the above embodiments are described herein as a method or combination of elements of a method that can be performed by a processor of a computer system or by other means for performing the functions described above. A processor having the necessary instructions for carrying out the method or method elements described above thus forms a means for carrying out the method or method elements. Furthermore, the elements of the apparatus embodiments described herein are examples of the following apparatus: the apparatus is used to implement the functions performed by the elements for the purpose of carrying out the invention.

As used herein, unless otherwise specified the use of the ordinal adjectives "first", "second", "third", etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner.

While embodiments of the invention have been described with respect to a limited number of embodiments, those skilled in the art, having benefit of this description, will appreciate that other embodiments can be devised which do not depart from the scope of the embodiments of the invention as described herein. Furthermore, it should be noted that the language used in the specification has been principally selected for readability and instructional purposes, and may not have been selected to delineate or circumscribe the inventive embodiments. Accordingly, many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the appended claims. The present embodiments are disclosed by way of illustration and not limitation, the scope of embodiments of the invention being defined by the appended claims.

Claims

1. An instruction processing method, comprising:

executing a target instruction sequence comprising a stake point instruction, and performing exception handling when the stake point instruction is executed;

writing a target instruction corresponding to the stub point instruction into an instruction cache register;

after the exception processing is finished, reading the target instruction from an instruction cache register; and

the target instruction is single-stepped.

2. The method of claim 1, further comprising:

in response to executing the peg point instruction, configuring a peg point enable flag in a state control register to be active.

3. The method of claim 2, wherein writing the target instruction corresponding to the stub instruction to an instruction cache register comprises:

responding to the detected effective pile point enabling mark, and acquiring a target instruction corresponding to the pile point instruction;

and writing the target instruction into an instruction cache register.

4. The method of claim 3, further comprising:

before the target instruction sequence is executed, replacing the target instruction at the pile inserting position in the original instruction sequence with a pile point instruction to obtain the target instruction sequence.

5. The method of claim 4, further comprising:

recording the corresponding relation between the pile inserting position and the target instruction; and

obtaining a target instruction corresponding to the pile point instruction, including:

and determining the target instruction which is originally positioned at the pile inserting position of the pile point instruction based on the corresponding relation.

6. The method of claim 2, further comprising:

after single-stepping the target instruction, configuring the stub enable flag to be invalid.

7. The method of claim 6, wherein configuring the stub enable flag in the state control register to be valid comprises:

setting a stake point enabling mark in a state control register to be 1; and

configuring the stub enable flag in the state control register to be invalid, comprising:

the peg point enable flag in the status control register is set to 0.

8. The method of claim 1, wherein performing exception handling comprises:

executing the object associated with the stub point instruction.

9. The method of claim 1, further comprising:

before exception handling, saving the current running state; and

and after the exception processing is finished, restoring the saved running state.

10. The method of any one of claims 1-9, wherein the peg point enabled flag is a single step enabled flag.

11. The method of any of claims 1-10, wherein the peg point instruction comprises a breakpoint instruction or a jump instruction.

12. A method of program debugging, comprising:

setting a pile inserting position in an original instruction sequence of a program;

replacing the target instruction at the pile inserting position in the original instruction sequence with a pile point instruction to obtain a target instruction sequence;

starting the program so as to instruct the instruction processing device to execute the target instruction sequence; and

and when the stub point instruction is executed, exception handling is carried out, the instruction processing device writes a target instruction corresponding to the stub point instruction into an instruction cache register, reads the target instruction from the instruction cache register after the exception handling is finished, and executes the target instruction in a single step mode.

13. An instruction processing apparatus comprising:

an instruction cache register adapted to register instructions;

the instruction execution unit is suitable for executing a target instruction sequence comprising a stake point instruction, and when the stake point instruction is executed, exception handling is carried out;

the register configuration unit is suitable for writing a target instruction corresponding to the stub instruction into an instruction cache register;

the instruction reading unit is suitable for reading the target instruction from an instruction cache register after the exception processing is finished; and

a single-step execution unit adapted to execute the target instruction in a single step.

14. The apparatus of claim 13, further comprising:

a state control register including a stake point enable flag;

the register configuration unit is further adapted to configure the stub enable flag to be active in response to execution of the stub instruction.

15. The apparatus of claim 14, wherein the register configuration unit is further adapted to, in response to detecting a valid stub enable flag, fetch a target instruction corresponding to the stub instruction, and write the target instruction to an instruction cache register.

16. The apparatus of claim 14, wherein the instruction execution unit is further adapted to replace a target instruction located at an instrumented position in an original instruction sequence with a stub instruction, resulting in the target instruction sequence, prior to executing the target instruction sequence.

17. The apparatus of claim 16, wherein the instruction execution unit is further adapted to record a correspondence of the instrumented position to the target instruction; the register configuration unit is further adapted to determine, based on the correspondence, a target instruction originally located at the position of the instrumentation point where the stub point instruction is located.

18. The apparatus of claim 14, wherein the register configuration unit is further adapted to configure the stub enable flag to be disabled after single stepping the target instruction.

19. The apparatus of claim 18, wherein the register configuration unit is adapted to set the stub enable flag in the state control register to 1 and is further adapted to set the stub enable flag in the state control register to 0.

20. The apparatus of claim 13, wherein the instruction execution unit is further adapted to execute an object associated with the stub instruction.

21. The apparatus of claim 13, wherein the instruction execution unit is further adapted to save a current running state before exception handling and to restore the saved running state after completion of the exception handling.

22. The apparatus of any one of claims 13-21, wherein the peg point enabling flag is a single step enabling flag.

23. The apparatus of any one of claims 13-22, wherein the peg point instruction comprises a breakpoint instruction or a jump instruction.

24. A program debugging apparatus comprising:

the pile point setting unit is suitable for setting pile inserting positions in an original instruction sequence of a program and replacing target instructions positioned at the pile inserting positions in the original instruction sequence with pile point instructions to obtain a target instruction sequence;

a program starting unit adapted to start the program for instructing a processing device to execute the target instruction sequence; and

and the exception handling unit is suitable for carrying out exception handling when the stub instruction is executed, the instruction processing device writes a target instruction corresponding to the stub instruction into an instruction cache register, reads the target instruction from the instruction cache register after the exception handling is finished, and executes the target instruction in a single step.

25. A computing device, comprising:

a memory;

one or more processors comprising the instruction processing apparatus of any one of claims 13-23; and

one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the one or more programs comprising instructions for performing the program debugging method of claim 12.

26. A system on a chip comprising an instruction processing apparatus according to any one of claims 13-23.

27. A smart device comprising the system on a chip of claim 26.