CN114167265B

CN114167265B - Circuit breaker topology network identification method, circuit breaker, device and system

Info

Publication number: CN114167265B
Application number: CN202010854805.8A
Authority: CN
Inventors: 王岚欣; 魏曦; 于波; 聂惠娟; 丰带君
Original assignee: Shanghai Liangxin Electrical Co Ltd
Current assignee: Shanghai Liangxin Electrical Co Ltd
Priority date: 2020-08-21
Filing date: 2020-08-21
Publication date: 2024-04-16
Anticipated expiration: 2040-08-21
Also published as: CN114167265A

Abstract

The application provides a circuit breaker topology network identification method, a circuit breaker, a device and a system, and relates to the technical field of piezoelectric devices. The method comprises the following steps: sequentially sending control instructions to a plurality of circuit breakers according to preset time intervals, wherein the control instructions are used for indicating the circuit breakers to send topology signals; recording the time for sending the control instruction, wherein the time is used for indicating the sending time of the circuit breaker for sending the topology signal; sending a reading instruction to a plurality of circuit breakers; receiving record data fed back by the plurality of circuit breakers according to the reading instruction, wherein the record data comprises: identifying the identification time of the topology signal of the lower-level circuit breaker; and identifying and acquiring the topology network according to the recorded data and the locally recorded sending time. By recording the topology signal identification time of each lower-level breaker in the breaker and locally recording the topology signal transmission time of the breaker in the upper computer, the frequency of the upper computer for collecting data from the breaker can be effectively reduced, and therefore the identification efficiency of the breaker topology network is effectively improved.

Description

Circuit breaker topology network identification method, circuit breaker, device and system

Technical Field

The invention relates to the technical field of piezoelectrics, in particular to a circuit breaker topology network identification method, a circuit breaker, a device and a system.

Background

Distribution is an extremely important element in the generation, transportation, and use of electricity in power grid systems, which typically include transformers and various high and low voltage circuit breaker devices. A complete and reliable network topology model is a basis for operation and maintenance of a power distribution network, and how to realize topology identification is a key technology for obtaining a reliable network topology model.

In the prior art, when network topology identification is performed, an upper computer generally needs to correspondingly acquire topology data of each breaker when a topology signal occurs to the breaker each time, and identify a topology network according to the topology data.

However, the above method may result in low topology recognition efficiency due to the complicated recognition process.

Disclosure of Invention

The invention aims to provide a circuit breaker topology network identification method, a circuit breaker, a device and a system aiming at the defects in the prior art so as to solve the problem of low circuit breaker topology network identification efficiency in the prior art.

In order to achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:

in a first aspect, an embodiment of the present application provides a method for identifying a topology network of a circuit breaker, which is applied to a circuit breaker in the topology network of the circuit breaker, and the method includes:

Responding to a control instruction of an upper computer, and sending a topology signal;

if the lower circuit breaker exists, identifying and acquiring the topology signal sent by the lower circuit breaker in the topology network, and recording identification time;

and responding to the reading instruction of the upper computer, and feeding back the identification time to the upper computer so that the upper computer identifies the topology network according to the locally recorded transmission time and the identification time, wherein the transmission time is used for indicating the transmission time of the topology signal.

Optionally, the responding to the reading instruction of the upper computer feeds back the identification time to the upper computer includes:

and responding to the reading instruction sent by the upper computer according to a preset interval, and feeding back the identification time to the upper computer.

Optionally, the identifying obtains the topology signal sent by a lower circuit breaker in the topology network, including:

and detecting current through a transformer, and identifying and acquiring the topology signal sent by a lower circuit breaker in the topology network.

In a second aspect, embodiments of the present application further provide a circuit breaker, including: the device comprises a processor, a topology generation unit, a topology identification unit and a communication module;

The topology identification unit, the topology sending unit and the communication module are electrically connected with the processor;

the processor is used for receiving a control instruction sent by the upper computer through the communication module; controlling the topology generation unit to send a topology signal in response to the control instruction;

if the lower-stage circuit breaker exists, the topology identification unit is used for identifying and acquiring the topology signal sent by the lower-stage circuit breaker in the topology network and recording identification time;

the processor is also used for responding to the reading instruction of the upper computer, and feeding back the identification time to the upper computer through the communication module so that the upper computer identifies the topology network according to the locally recorded sending time and the identification time.

Optionally, the method comprises: a control circuit board; the processor is arranged on the control circuit board, and the communication module is arranged on the control circuit board in a pluggable manner.

Optionally, the processor is specifically configured to receive, through the communication module, the read instruction sent by the upper computer at a preset interval.

Optionally, the communication module includes: a power line carrier communication module and/or an RS485 communication module.

Optionally, the method further comprises: a transformer;

the mutual inductor is connected with the topology identification unit;

the topology identification unit is specifically configured to detect current through the transformer, and identify and acquire the topology signal sent by the lower circuit breaker in the topology network.

In a third aspect, an embodiment of the present application further provides a method for identifying a topology network of a circuit breaker, where the method is applied to an upper computer in the topology network of the circuit breaker, and the method includes:

sequentially sending control instructions to a plurality of circuit breakers according to preset time intervals, wherein the control instructions are used for indicating the circuit breakers to send topology signals;

recording the time for transmitting the control instruction, wherein the time is used for indicating the transmission time of the circuit breaker for transmitting the topology signal;

transmitting a reading instruction to the plurality of circuit breakers;

receiving record data fed back by the plurality of circuit breakers according to the reading instruction, wherein the record data comprises: identifying the identification time of the topology signal of the lower-level circuit breaker;

and identifying and acquiring the topology network according to the recorded data and the locally recorded sending time.

Optionally, the identifying the obtaining topology network according to the recorded data and the locally recorded sending time includes:

Generating a topology hierarchy form according to the sending time and the identifying time corresponding to each circuit breaker, wherein the topology hierarchy form is used for representing the hierarchy relation among the circuit breakers;

and identifying and acquiring a topological network according to the topological hierarchy form.

Optionally, the generating a topology level table according to the sending time and the identifying time corresponding to each circuit breaker includes:

acquiring target identification time between two adjacent sending times according to the sending time and the identification time corresponding to each circuit breaker;

determining that the circuit breaker corresponding to the target identification time and the circuit breaker corresponding to the previous sending time in the two adjacent sending times are the same group of circuit breakers;

and generating the topology level form according to the determined at least one group of the same-group circuit breakers.

In a fourth aspect, an embodiment of the present application further provides a circuit breaker topology network identification device, which is applied to an upper computer in a circuit breaker topology network, where the device includes: the device comprises a sending module, a recording module, a receiving module and an identification module;

the sending module is used for sequentially sending control instructions to the plurality of circuit breakers according to preset time intervals, and the control instructions are used for indicating the circuit breakers to send topology signals;

The recording module is used for recording the time for transmitting the control instruction, and the time is used for indicating the transmission time of the circuit breaker for transmitting the topology signal;

the sending module is further used for sending reading instructions to the plurality of circuit breakers;

the receiving module is configured to receive record data fed back by the plurality of circuit breakers according to the reading instruction, where the record data includes: identifying the identification time of the topology signal of the lower-level circuit breaker;

the identification module is used for identifying and acquiring the topology network according to the recorded data and the local recorded sending time.

Optionally, the identification module is specifically configured to generate a topology level table according to the sending time and the identification time corresponding to each circuit breaker, where the topology level table is used to represent a level relationship between each circuit breaker; and identifying and acquiring a topological network according to the topological hierarchy form.

Optionally, the identification module is specifically configured to obtain, according to the sending time and the identification time corresponding to each circuit breaker, a target identification time between two adjacent sending times; determining that the circuit breaker corresponding to the target identification time and the circuit breaker corresponding to the previous sending time in the two adjacent sending times are the same group of circuit breakers; and generating the topology level form according to the determined at least one group of the same-group circuit breakers.

In a fifth aspect, embodiments of the present application further provide a circuit breaker topology network system, the system including: a host computer and a plurality of circuit breakers according to the second aspect; each breaker is connected with the upper computer; the circuit breakers form a multi-stage branch circuit, and each circuit breaker in each stage of branch circuit forms an upper-stage and lower-stage connection relationship;

the upper computer is used for sequentially sending control instructions to the plurality of circuit breakers according to preset time intervals, and the control instructions are used for indicating the circuit breakers to send topology signals;

the circuit breaker is used for responding to the control instruction and sending a topology signal;

the upper computer is used for recording the time for sending the control instruction, and the time is used for indicating the sending time of the circuit breaker for sending the topology signal;

the circuit breaker is used for identifying and acquiring the topology signal sent by the lower circuit breaker in the topology network if the lower circuit breaker exists, and recording the identification time;

the upper computer is also used for sending a reading instruction to the plurality of circuit breakers;

the circuit breaker is also used for responding to the reading instruction of the upper computer and feeding back the identification time to the upper computer;

The upper computer is used for receiving the identification time fed back by the plurality of circuit breakers according to the reading instruction, and identifying and acquiring the topology network according to the locally recorded sending time and the identification time.

Optionally, the circuit breaker is configured to respond to the read instruction sent by the upper computer at a preset interval, and feed back the identification time to the upper computer.

Optionally, the circuit breaker is specifically configured to detect a current through a transformer, and identify and acquire the topology signal sent by a lower circuit breaker in the topology network.

Optionally, the upper computer is specifically configured to generate a topology level table according to the sending time and the identifying time corresponding to each circuit breaker, where the topology level table is used to represent a level relationship between each circuit breaker; and identifying and acquiring a topological network according to the topological hierarchy form.

Optionally, the upper computer is specifically configured to obtain, according to the sending time and the identifying time corresponding to each circuit breaker, a target identifying time between two adjacent sending times; determining that the circuit breaker corresponding to the target identification time and the circuit breaker corresponding to the previous sending time in the two adjacent sending times are the same group of circuit breakers; and generating the topology level form according to the determined at least one group of the same-group circuit breakers.

The beneficial effects of this application are:

the application provides a circuit breaker topology network identification method, a circuit breaker, a device and a system, and in one aspect, the method is applied to a circuit breaker in the circuit breaker topology network identification system, and the method can comprise the following steps: responding to a control instruction of an upper computer, and sending a topology signal; if the lower circuit breaker exists, identifying and acquiring a topology signal sent by the lower circuit breaker in the topology network, and recording identification time; and responding to the reading instruction of the upper computer, and feeding back the identification time to the upper computer so that the upper computer identifies the topology network according to the locally recorded transmission time and the identification time, wherein the transmission time is used for indicating the transmission time of the topology signal. According to the method, the topology signal identification time of each lower-level circuit breaker is recorded in the circuit breaker, the topology signal sending time of the circuit breaker is recorded locally by the upper computer, the frequency of the upper computer for collecting data from the circuit breaker can be effectively reduced, and therefore the identification efficiency of the circuit breaker topology network is effectively improved.

On the other hand, the method is applied to an upper computer in the breaker topology network identification system, and the method can further comprise the following steps: sequentially sending control instructions to a plurality of circuit breakers according to preset time intervals, wherein the control instructions are used for indicating the circuit breakers to send topology signals; recording the time for sending the control instruction, wherein the time is used for indicating the sending time of the circuit breaker for sending the topology signal; sending a reading instruction to a plurality of circuit breakers; receiving record data fed back by the plurality of circuit breakers according to the reading instruction, wherein the record data comprises: identifying the identification time of the topology signal of the lower-level circuit breaker; and identifying and acquiring the topology network according to the recorded data and the locally recorded sending time. According to the method, the sending time of the topology signals of the circuit breakers is recorded locally by the upper computer, so that the topology network where the circuit breakers are located can be identified, and further, the number of times that the upper computer obtains data from the circuit breakers can be effectively reduced due to the fact that the sending time of the topology signals sent by the circuit breakers is recorded in the upper computer, the data collection amount is reduced, and the identification efficiency of the topology network is effectively improved.

And secondly, the upper computer only needs to read the identification time recorded by each breaker once after finishing traversing the process of sending the control instruction to all the breakers, and compared with the prior art that the identification time is correspondingly received once when the control instruction is sent once, the scheme can effectively reduce the data acquisition times, thereby improving the topology network identification efficiency.

In addition, the topology network can be accurately identified and acquired through the comparison analysis of the sending time and the identification time of the circuit breaker.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic flow chart of a circuit breaker topology network identification method provided in an embodiment of the present application;

fig. 2 is a schematic structural diagram of a circuit breaker according to an embodiment of the present application;

fig. 3 is a schematic diagram of another circuit breaker according to an embodiment of the present disclosure;

Fig. 4 is a schematic structural diagram of another circuit breaker according to an embodiment of the present disclosure;

fig. 5 is a schematic flow chart of a circuit breaker topology network identification method according to an embodiment of the present application;

fig. 6 is a flowchart of another method for identifying a topology network of a circuit breaker according to an embodiment of the present application;

fig. 7 is a flowchart of another method for identifying a topology network of a circuit breaker according to an embodiment of the present application;

fig. 8 is a schematic diagram of a circuit breaker topology network according to an embodiment of the present application;

fig. 9 is a schematic diagram of a circuit breaker topology network identification device according to an embodiment of the present application;

fig. 10 is a schematic structural diagram of a circuit breaker topology network system according to an embodiment of the present application.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it should be understood that the accompanying drawings in the present application are only for the purpose of illustration and description, and are not intended to limit the protection scope of the present application. In addition, it should be understood that the schematic drawings are not drawn to scale. A flowchart, as used in this application, illustrates operations implemented according to some embodiments of the present application. It should be understood that the operations of the flow diagrams may be implemented out of order and that steps without logical context may be performed in reverse order or concurrently. Moreover, one or more other operations may be added to the flow diagrams and one or more operations may be removed from the flow diagrams as directed by those skilled in the art.

In addition, the described embodiments are only some, but not all, of the embodiments of the present application. The components of the embodiments of the present application, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, as provided in the accompanying drawings, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, are intended to be within the scope of the present application.

It should be noted that the term "comprising" will be used in the embodiments of the present application to indicate the presence of the features stated hereinafter, but not to exclude the addition of other features.

First, a circuit breaker topology network system to which the circuit breaker topology network identification method of the present application is applied will be briefly described, and the circuit breaker topology network system may include: the system comprises an upper computer and a plurality of circuit breakers under a transformer area power grid, wherein each circuit breaker is connected with the upper computer, a multi-stage branch circuit is formed among the circuit breakers, the circuit breakers in each stage of branch circuit are connected with each other to form an upper-lower stage relationship, and the multi-stage branch circuits jointly form the topology network.

The upper computer can send control instructions to each breaker in turn according to the identifiers of the breakers so as to control the breakers to send topology signals to the topology network where the breakers are located, and meanwhile, the upper computer can locally record the time for sending the control instructions, and the time is used as the sending time of the breakers to send the topology signals.

Each breaker can also identify the topology signal sent by the next level breaker and record the identification time.

The upper computer sends a reading instruction to each breaker, and can read the identification time recorded in each breaker, so that the topology network formed by the plurality of breakers is identified and acquired according to the locally recorded sending time and the acquired identification time, and the upper-level relationship between each breaker is determined.

Fig. 1 is a flow chart of a method for identifying a topology network of a circuit breaker according to an embodiment of the present application, where the method is applied to a circuit breaker in a topology network of a circuit breaker, optionally, as shown in fig. 1, the method may include:

s101, responding to a control instruction of an upper computer, and sending a topology signal.

Alternatively, a plurality of circuit breakers may be included in the circuit breaker topology network, each of the plurality of circuit breakers being a circuit breaker under one of the bays. A plurality of branches may be formed between the plurality of circuit breakers, each branch may include at least two circuit breakers, and a superior-inferior relationship may be formed between each circuit breaker to form a circuit breaker topology network under the bay.

Each breaker can receive a control instruction sent by the upper computer, and respond to the control instruction of the upper computer to send a topology signal which is applied to a topology network (a power grid of a station area where the breaker is located) where the breaker is located.

S102, if the lower-level circuit breaker exists, identifying and acquiring a topology signal sent by the lower-level circuit breaker in the topology network, and recording identification time.

For any one breaker, its corresponding upper level breaker can identify the topology signal that it sends and applies in the topology network. When the circuit breaker is a first-stage circuit breaker, i.e. it is not present in a higher-stage circuit breaker, the topology signal sent by the first-stage circuit breaker will not be recognized by the other circuit breakers.

Alternatively, for any breaker in which a lower-stage breaker exists, when a topology signal transmitted from the lower-stage breaker is recognized, the recognition time may be recorded in the present breaker. When there are a plurality of lower circuit breakers in the upper circuit breaker, the transmission time of the topology signal transmitted to each lower circuit breaker can be separately recorded.

The identification time recorded in any one breaker is the identification time when the breaker identifies the topology signal sent by the next breaker, but is not the identification time when the topology signal sent by the breaker is identified by other breakers.

And S103, responding to a reading instruction of the upper computer, and feeding back identification time to the upper computer so that the upper computer can identify the topology network according to the locally recorded transmission time and the identification time, wherein the transmission time is used for indicating the transmission time of the topology signal.

In some embodiments, each circuit breaker may receive a read instruction sent by the upper computer, and feed back the recorded identification time for identifying the topology signal sent by the lower circuit breaker to the upper computer, so that the upper computer may perform circuit breaker topology network identification according to the received identification time and the sending time for sending the topology signal by each circuit breaker recorded locally on the upper computer, so as to determine the upper-lower relationship between each circuit breaker in the topology network. When the identification time is fed back, the corresponding breaker identification can be carried at the same time, so that the upper computer can identify and record conveniently.

In this embodiment, the identification time for identifying the topology signal is recorded in each breaker, and the transmission time for each breaker to transmit the topology signal is recorded in the upper computer, so that the upper computer has smaller data volume, fewer reading times and faster reading speed when reading the data recorded by each breaker, thereby accelerating the identification efficiency of the upper computer for identifying the topology network. The upper computer may record the time of sending the control command as the sending time.

In summary, the circuit breaker topology network identification method provided in this embodiment includes: responding to a control instruction of an upper computer, and sending a topology signal; if the lower circuit breaker exists, identifying and acquiring a topology signal sent by the lower circuit breaker in the topology network, and recording identification time; and responding to the reading instruction of the upper computer, and feeding back the identification time to the upper computer so that the upper computer identifies the topology network according to the locally recorded transmission time and the identification time, wherein the transmission time is used for indicating the transmission time of the topology signal. According to the method, the topology signal identification time of each lower-level circuit breaker is recorded in the circuit breaker, the topology signal sending time of the circuit breaker is recorded locally by the upper computer, the frequency of the upper computer for collecting data from the circuit breaker can be effectively reduced, and therefore the identification efficiency of the circuit breaker topology network is effectively improved.

Optionally, in the step S103, in response to the reading instruction of the upper computer, feeding back the identification time to the upper computer may include: and responding to a reading instruction sent by the upper computer at preset intervals, and feeding back the identification time to the upper computer.

In one implementation manner, after any breaker currently recognizes and records the recognition time, the recognition time recorded by the breaker can be fed back to the upper computer according to the reading instruction sent by the upper computer.

In another implementation manner, after all the circuit breakers identify and record the identification time, each circuit breaker respectively feeds back the recorded identification time to the upper computer according to the reading instruction sent by the upper computer.

Optionally, the circuit breaker responds to the reading instructions sequentially sent by the upper computer at preset intervals to feed back the identification time, so that the accuracy of data acquired by the upper computer can be ensured, confusion of the data is effectively avoided, and the identification efficiency of the topology network is improved.

Optionally, in the step S102, identifying and acquiring the topology signal sent by the lower circuit breaker in the topology network may include: detecting current through a transformer, and identifying and acquiring a topology signal sent by a lower circuit breaker in a topology network.

In general, a transformer in an upper circuit breaker may be connected to a power inlet terminal and a power outlet terminal of a lower circuit breaker, and a topology signal transmitted by the lower circuit breaker may be transmitted to the transformer through the power outlet terminal, so that the upper circuit breaker may detect the topology signal through the transformer to identify and acquire the topology signal transmitted by the lower circuit breaker.

Alternatively, the topology signal sent by the circuit breaker may be a current signal, and the transformer may be a current transformer correspondingly, so that the current signal may be detected by the current transformer, and the topology signal sent by the circuit breaker may be identified.

In this embodiment, the topology signal sent by the lower-level circuit breaker is identified and acquired through the transformer, and the accuracy of identifying the topology signal is higher due to higher detection accuracy of the transformer, so that the accuracy of recorded identification time is also higher.

The structure of the circuit breaker to which the circuit breaker topology network identification method described above is applied will be described by various embodiments as follows.

Fig. 2 is a schematic structural diagram of a circuit breaker according to an embodiment of the present application, and optionally, as shown in fig. 2, the circuit breaker 300 may include: a processor 110, a topology generation unit 120, a topology identification unit 130, a communication module 140. The topology generation unit 120, the topology identification unit 130, and the communication module 140 are electrically connected to the processor 110.

The processor 110 is configured to receive, through the communication module 140, a control instruction sent by the upper computer; in response to the control instruction, the topology generation unit 120 is controlled to transmit a topology signal.

Alternatively, each circuit breaker 300 may be electrically connected to the upper computer through the communication module 140. The processor 110 may receive a control instruction sent by the upper computer through the communication module 140, and at the same time, the processor 110 controls the topology generating unit 120 to send a topology signal to the topology network according to the received control instruction.

Wherein the communication module 140 may be: a power line carrier communication module and/or an RS485 communication module. The wiring of the power line carrier communication module is relatively simple, and the data transmission efficiency is high.

Alternatively, for any one of the circuit breakers 300, if a lower circuit breaker exists, the topology signal transmitted by the lower circuit breaker in the topology network may be identified and acquired by the topology identification unit 130, and the identification time may be recorded.

In addition, the processor 110 is further configured to, in response to a read instruction of the upper computer, feed back, through the communication module 140, the identification time to the upper computer, so that the upper computer identifies the topology network according to the locally recorded transmission time and the identification time.

Alternatively, the processor 110 may acquire the identification time recorded by the circuit breaker 300, and after receiving the reading instruction sent by the upper computer, feedback the identification time to the upper computer through the communication module 140.

The processor 110 may be a central processing unit (Central Processing Unit, CPU), a digital signal processor (Digital Signal Processor, DSP), a field programmable gate array (Field Programmable Gate Array, FPGA), a microprocessor, or the like.

Optionally, the processor 110 is specifically configured to receive, through the communication module 140, a read instruction sent by the upper computer at a preset interval.

In some embodiments, the upper computer may sequentially read the identification time from the plurality of circuit breakers according to the preset interval, and correspondingly, the processor 110 receives the reading instruction sent by the upper computer according to the preset interval through the communication module 140. The read instruction is used to instruct reading the recorded identification time from the circuit breaker.

By sequentially reading the identification time recorded by the circuit breakers, the upper computer can accurately record the identification time read from each circuit breaker, and errors in data reading are avoided, so that the identification accuracy is higher when topology network identification is performed based on the read identification time and the local recorded transmission time.

Fig. 3 is a schematic structural diagram of another circuit breaker according to an embodiment of the present application, optionally, as shown in fig. 3, the circuit breaker of the present application may further include: a control circuit board 100; the processor 110 may be mounted on the control circuit board 100, and the communication module 140 may be mounted on the control circuit board 100 in a pluggable manner.

As shown in fig. 3, the processor 110, the topology generating unit 120, and the topology identifying unit 130 may be mounted on the control circuit board 100. Of course, the installation shown in fig. 3 is only one possible way, and is not limited thereto.

In another implementation, the topology generation unit 120 may also be integrated on the communication module 140, which is not illustrated in the specific figures herein.

The topology identification unit 130 may be a topology identification circuit integrated on the control circuit board 100, or may be implemented in the form of software by the processor 110. The present application is not particularly limited.

Fig. 4 is a schematic structural diagram of another circuit breaker according to an embodiment of the present application, and optionally, as shown in fig. 4, the circuit breaker of the present application further includes: a transformer 150; the transformer 150 is connected to the topology identification unit 130.

The transformer 150 may be a current transformer, and is configured to identify a topology signal transmitted by a lower circuit breaker by detecting a current.

Optionally, the topology identification unit 130 is specifically configured to detect a current through the transformer 150, and identify and acquire a topology signal sent by a lower circuit breaker in the topology network.

Alternatively, the transformer 150 of each circuit breaker may be connected to the power inlet terminal and the power outlet terminal of the lower circuit breaker, the topology signal transmitted from the lower circuit breaker may be transmitted to the transformer 150 through the power outlet terminal, and the topology identification unit 130 may detect a current in the topology signal through the transformer 150, thereby identifying the topology signal transmitted from the lower circuit breaker.

It should be noted that, each breaker under the power grid of the present district may have the above structure setting, that is, in the topology network, the plurality of breakers may be the breakers of the same structure, and the working principle of each breaker is similar, which may be understood by referring to the above description, and will not be repeated here.

The above-mentioned implementation procedure of the circuit breaker topology network identification method executed by the circuit breaker when applied to the circuit breaker in the topology network is described in detail, and the specific principle of the circuit breaker topology network identification method executed by the upper computer when applied to the upper computer in the topology network will be described below through a plurality of embodiments.

Fig. 5 is a flow chart of a method for identifying a topology network of a circuit breaker according to an embodiment of the present application, where the method is applied to an upper computer in the topology network of the circuit breaker, as shown in fig. 5, and the method may include:

s501, sequentially sending control instructions to a plurality of circuit breakers according to preset time intervals, wherein the control instructions are used for indicating the circuit breakers to send topology signals.

The upper computer generally refers to a computer that can directly issue a control instruction. In this embodiment, the upper computer may send control instructions to the plurality of circuit breakers in sequence according to a preset time interval according to the identifier of each circuit breaker.

The circuit breaker is assumed to include: the circuit breaker 1, the circuit breaker 2, the circuit breaker 3, the circuit breaker 4 and the like, the preset time interval is 1 minute, and the upper computer can sequentially send control instructions to the circuit breaker 1, the circuit breaker 2, the circuit breaker 3 and the circuit breaker 4 according to the 1 minute interval time. The processor of each circuit breaker controls the topology generation unit to send topology signals to be applied to the topology network according to the received control instruction.

S502, recording time for sending the control instruction, wherein the time is used for indicating the sending time of the circuit breaker for sending the topology signal.

In some embodiments, the circuit breaker does not need to record the sending time of the topology signal sent by the circuit breaker, but is autonomously recorded locally through the upper computer, so that the data volume recorded in the circuit breaker can be reduced, and meanwhile, the upper computer does not need to read the sending time of the topology signal from the circuit breaker, so that the acquisition time of the data can be effectively saved.

In general, the time when the upper computer sends the control command to the circuit breaker is basically the same as the time when the circuit breaker receives the control command and sends the topology signal, and only a millisecond error exists, so the upper computer can record the time when the upper computer sends the control command to each circuit breaker as the sending time of the circuit breaker for sending the topology signal.

Because the control instruction is sent by the upper computer, the sending time of the control instruction is recorded locally when the upper computer sends the control instruction once, and the sending time of the control instruction is used as the sending time of the topology signal sent by the circuit breaker.

Of course, in some cases, after the upper computer sends a control instruction to the circuit breaker, the circuit breaker does not send a topology signal due to a fault or the like of the circuit breaker, and then the circuit breaker sends a feedback error report signal to the upper computer, and the upper computer will not record the sending time of the current control instruction.

S503, sending a reading instruction to a plurality of circuit breakers.

Optionally, the upper computer circularly executes the steps, sequentially sends control instructions to each circuit breaker, and after traversing all the circuit breakers, the upper computer can sequentially send reading instructions to the plurality of circuit breakers to respectively acquire the data recorded by each circuit breaker.

In this embodiment, the upper computer only needs to read the identification time recorded by each breaker once after traversing all the breakers, and compared with the prior art, which has once control instruction sent and correspondingly receives the identification time once, the scheme can effectively reduce the data acquisition times, thereby improving the topology network identification efficiency.

S504, receiving record data fed back by the plurality of circuit breakers according to the reading instruction, wherein the record data comprises: the identification time to the lower circuit breaker topology signal is identified.

After receiving the reading instruction, the circuit breaker feeds back the recorded record data to the upper computer through the communication module. The upper computer receives the record data fed back by each breaker, wherein the data recorded in the breaker is the identification time for identifying the topology signal of the lower breaker according to the description of the embodiments, that is, the upper computer can obtain the identification time recorded by each breaker from the breakers.

S505, identifying and acquiring the topology network according to the recorded data and the locally recorded sending time.

Optionally, the upper computer can identify and acquire the topology network according to the received record data fed back by the plurality of circuit breakers and the locally recorded sending time of the topology signal sent by the circuit breaker.

The time for transmitting the topology signal by the circuit breaker is locally recorded, so that the frequency of collecting data from the circuit breaker and the size of the collected data can be effectively reduced, and the identification efficiency of the topology network can be effectively improved.

In summary, the circuit breaker topology network identification method provided in the embodiment includes: sequentially sending control instructions to a plurality of circuit breakers according to preset time intervals, wherein the control instructions are used for indicating the circuit breakers to send topology signals; recording the time for sending the control instruction, wherein the time is used for indicating the sending time of the circuit breaker for sending the topology signal; sending a reading instruction to a plurality of circuit breakers; receiving record data fed back by the plurality of circuit breakers according to the reading instruction, wherein the record data comprises: identifying the identification time of the topology signal of the lower-level circuit breaker; and identifying and acquiring the topology network according to the recorded data and the locally recorded sending time. According to the method, the sending time of the topology signals of the circuit breakers is recorded locally by the upper computer, so that the topology network where the circuit breakers are located can be identified, and further, the number of times that the upper computer obtains data from the circuit breakers can be effectively reduced due to the fact that the sending time of the topology signals sent by the circuit breakers is recorded in the upper computer, the data collection amount is reduced, and the identification efficiency of the topology network is effectively improved.

Fig. 6 is a flowchart of another method for identifying a topology network of a circuit breaker according to an embodiment of the present application, optionally, as shown in fig. 6, in step S505, identifying and acquiring the topology network according to the recorded data and the locally recorded sending time may include:

s601, generating a topology level table according to the transmission time and the identification time corresponding to each circuit breaker, wherein the topology level table is used for representing the level relation among the circuit breakers.

The upper computer can obtain the identification time of the topology signals of the lower-level circuit breakers from the circuit breakers according to the locally recorded transmission time of the topology signals transmitted by each circuit breaker, compare the transmission time with the identification time, and generate a topology level form according to the combination of the transmission time and the identification time which meet the preset conditions.

The topology level form is a form for recording the upper and lower level relation of the breaker. Of course, in practical application, the relationship between the upper and lower stages of the circuit breaker may be recorded in a form not limited to this.

S602, identifying and acquiring a topological network according to the topological hierarchy form.

Alternatively, the topology network may be formed by analysis based on the upper and lower relationships of the circuit breakers recorded in the topology level table.

In general, the upper level circuit breaker or the lower level circuit breaker corresponding to one circuit breaker is not limited to one, and only all the upper level circuit breakers or the lower level circuit breakers corresponding to each circuit breaker are recorded in the topology level table, and to form a topology network, it is also necessary to determine the adjacent upper level circuit breaker of each circuit breaker, thereby determining the circuit breaker to which each circuit breaker is connected.

For example: the upper circuit breaker of the circuit breaker 1 is the circuit breaker 2, and the upper circuit breaker of the circuit breaker 2 is 3, then the upper circuit breaker of the circuit breaker 1 includes: the circuit breaker 2 and the circuit breaker 3, then, further analysis is required to determine the adjacent upper circuit breaker of the circuit breaker 1, that is, the upper circuit breaker to which the circuit breaker 1 is connected, so that a topology network is formed according to the determined connection relationship of each circuit breaker.

In this embodiment, by means of time comparison, the topology network is identified and acquired, the identification process is relatively simple, and the identification efficiency is high.

Fig. 7 is a flowchart of another method for identifying a topology network of a circuit breaker according to the embodiment of the present application, optionally, as shown in fig. 7, in step S601, generating a topology level form according to a sending time and an identifying time corresponding to each circuit breaker may include:

S701, acquiring target identification time between two adjacent transmission times according to the transmission time and the identification time corresponding to each breaker.

In general, the topology signal transmitted by the lower circuit breaker can be recognized by the upper circuit breaker faster, and the transmission time and the recognition time are often different by tens of seconds. In this embodiment, when the upper computer sends the control instruction, the upper computer sends the control instruction at intervals of 1 minute, and the sending time of the topology signal sent by the corresponding circuit breaker is also about 1 minute adjacent to the corresponding sending time, and then the target identification time between two adjacent sending times can be obtained according to the sending time and the identification time corresponding to all the circuit breakers.

S702, determining that the circuit breaker corresponding to the target identification time and the circuit breaker corresponding to the previous sending time in the two adjacent sending times are the same group of circuit breakers.

Assuming that the transmission time corresponding to the circuit breaker 1 is 8:01:00 points on 1 month and 1 day in 2020, the transmission time corresponding to the circuit breaker 2 is 8:02:00 points on 1 month and 1 day in 2020, the identification time corresponding to the circuit breaker 5 is 8:01:20 points on 1 month and 1 day in 2020, and the identification time corresponding to the circuit breaker 7 is 8:02:20 points on 1 month and 1 day in 2020, the identification time corresponding to the circuit breaker 5 is between the transmission times of the circuit breaker 1 and the circuit breaker 2, and the identification time corresponding to the circuit breaker 5 can be determined to be the target identification time.

Wherein the breaker 1 and the breaker 2 are located at the previous transmission time, then the breaker 1 and the breaker 5 can be determined to be the same group of breakers.

Similarly, a plurality of circuit breakers of the same group may be determined in accordance with the above examples.

S703, generating a topology level form according to the determined at least one group of same-group circuit breakers.

Alternatively, the same group of circuit breakers may be recorded together in a preset manner, for example: recorded on the same line, or marked, etc., to generate a topology level table.

Table 1 below is a topology level table provided in an embodiment of the present application. Alternatively, table 1 illustrates only one possible topology level form presentation, which is not limited in practical application.

TABLE 1

The topology signal sending time is the sending time of a control instruction recorded locally by the upper computer; the transmitting breaker sequence number may refer to a breaker transmitting a topology signal; the topology signal identification time can refer to the identification time from the identification of the circuit breaker obtained from each circuit breaker to the identification of the topology signal sent by the lower circuit breaker by the upper computer; identifying a breaker number may refer to identifying a breaker that is capable of identifying a topology signal transmitted by a next stage; the number may refer to the number of circuit breakers that can identify the topology signal sent by the same circuit breaker; and layer n may refer to the number of layers in which the transmitting circuit breaker is located in the topology network.

Fig. 8 is a schematic diagram of a circuit breaker topology network according to an embodiment of the present application. Alternatively, the "send breaker number" and "identify breaker number" from the topology level table generated in table 1 may be analyzed: the topology signal which is not sent by the circuit breaker 5 is not identified by other circuit breakers, namely the circuit breaker 5 does not have a superior circuit breaker and is the first layer of the topology network; the topology signals sent by the circuit breakers 1, 3 and 7 are identified by the circuit breaker 5, namely, the upper circuit breakers of the circuit breakers 1, 3 and 7 are all the circuit breakers 5 and are the second layer of the topology network; by analogy, the upper-level circuit breaker of the circuit breaker 2 is provided with the circuit breakers 5 and 7, and the circuit breaker 2 is a third layer of the topological network at the lower level of the circuit breaker 7; the upper level circuit breakers of the circuit breakers 4 and 9 are provided with the circuit breakers 3 and 5, and the circuit breakers 4 and 9 are the third layer of the topological network of the lower level of the circuit breaker 3; the upper-level circuit breakers of the circuit breakers 6 and 8 are provided with the circuit breakers 1 and 5, and the circuit breakers 6 and 8 are the third layer of the topological network of the lower-level circuit breaker 1, so that a circuit breaker topological network diagram shown in fig. 8 is generated.

Through the analysis of the topology level form, the topology network is identified and obtained.

Fig. 9 is a schematic diagram of a circuit breaker topology network identification device provided in an embodiment of the present application, where the device may be applied to an upper computer in a circuit breaker topology network, and functions implemented by the device correspond to method steps executed by the upper computer. The upper computer may be a computer that can directly send control instructions. As shown in fig. 8, the apparatus may include: a transmitting module 510, a recording module 520, a receiving module 530, and an identifying module 540;

the sending module 510 is configured to send control instructions to a plurality of circuit breakers sequentially according to a preset time interval, where the control instructions are used to instruct the circuit breakers to send topology signals;

a recording module 520, configured to record a time for sending the control instruction, where the time is used to instruct the circuit breaker to send the sending time of the topology signal;

The sending module 510 is further configured to send a reading instruction to the plurality of circuit breakers;

the receiving module 530 is configured to receive record data fed back by the plurality of circuit breakers according to the reading instruction, where the record data includes: identifying the identification time of the topology signal of the lower-level circuit breaker;

the identifying module 540 is configured to identify and acquire the topology network according to the recorded data and the locally recorded transmission time.

Optionally, the identification module 540 is specifically configured to generate a topology level table according to the sending time and the identifying time corresponding to each circuit breaker, where the topology level table is used to represent a level relationship between each circuit breaker; and identifying and acquiring the topology network according to the topology level form.

Optionally, the identifying module 540 is specifically configured to obtain a target identifying time between two adjacent sending times according to the sending time and the identifying time corresponding to each breaker; determining that the circuit breaker corresponding to the target identification time and the circuit breaker corresponding to the previous transmission time in the two adjacent transmission times are the same group of circuit breakers; and generating a topology level table according to the determined at least one group of circuit breakers.

The foregoing apparatus is used for executing the method provided in the foregoing embodiment, and its implementation principle and technical effects are similar, and are not described herein again.

The above modules may be one or more integrated circuits configured to implement the above methods, for example: one or more application specific integrated circuits (Application Specific Integrated Circuit, abbreviated as ASIC), or one or more microprocessors (digital singnal processor, abbreviated as DSP), or one or more field programmable gate arrays (Field Programmable Gate Array, abbreviated as FPGA), or the like. For another example, when a module above is implemented in the form of a processing element scheduler code, the processing element may be a general-purpose processor, such as a central processing unit (Central Processing Unit, CPU) or other processor that may invoke the program code. For another example, the modules may be integrated together and implemented in the form of a system-on-a-chip (SOC).

The modules may be connected or communicate with each other via wired or wireless connections. The wired connection may include a metal cable, optical cable, hybrid cable, or the like, or any combination thereof. The wireless connection may include a connection through a LAN, WAN, bluetooth, zigBee, or NFC, or any combination thereof. Two or more modules may be combined into a single module, and any one module may be divided into two or more units. It will be clearly understood by those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described system and apparatus may refer to corresponding procedures in the method embodiments, which are not described in detail in this application.

It should be noted that these above modules may be one or more integrated circuits configured to implement the above methods, for example: one or more application specific integrated circuits (Application Specific Integrated Circuit, abbreviated as ASIC), or one or more microprocessors (Digital Singnal Processor, abbreviated as DSP), or one or more field programmable gate arrays (Field Programmable Gate Array, abbreviated as FPGA), or the like. For another example, when a module above is implemented in the form of a processing element scheduler code, the processing element may be a general-purpose processor, such as a central processing unit (Central Processing Unit, CPU) or other processor that may invoke the program code. For another example, the modules may be integrated together and implemented in the form of a System-on-a-chip (SOC).

Fig. 10 is a schematic structural diagram of a circuit breaker topology network system according to an embodiment of the present application, as shown in fig. 10, where the system may include: a host computer 200, and a plurality of circuit breakers 300 shown in fig. 4; each circuit breaker 300 is connected with the upper computer 200; the circuit breakers form a multi-stage branch circuit, and each circuit breaker in each stage of branch circuit forms an upper-stage and lower-stage connection relationship;

The upper computer 200 is used for sequentially sending control instructions to the plurality of circuit breakers according to preset time intervals, wherein the control instructions are used for indicating the circuit breakers to send topology signals;

a circuit breaker 300 for transmitting a topology signal in response to a control instruction;

the upper computer 200 is used for recording the time for sending the control instruction, and the time is used for indicating the sending time of the topology signal sent by the circuit breaker;

the circuit breaker 300 is used for identifying and acquiring a topology signal sent by a lower-level circuit breaker in a topology network if the lower-level circuit breaker exists, and recording identification time;

the upper computer 200 is further configured to send a reading instruction to the plurality of circuit breakers;

the circuit breaker 300 is further used for responding to a reading instruction of the upper computer and feeding back the identification time to the upper computer;

the upper computer 200 is configured to receive the identification time fed back by the plurality of circuit breakers according to the reading instruction, and identify and acquire the topology network according to the locally recorded sending time and the identification time.

Optionally, the circuit breaker 300 is configured to respond to a reading instruction sent by the upper computer at preset intervals, and feed back the identification time to the upper computer.

Optionally, the circuit breaker 300 is specifically configured to detect a current through a transformer, and identify and acquire a topology signal sent by a lower circuit breaker in the topology network.

Optionally, the upper computer 200 is specifically configured to generate a topology level table according to the sending time and the identifying time corresponding to each circuit breaker, where the topology level table is used to represent a level relationship between each circuit breaker; and identifying and acquiring the topology network according to the topology level form.

Optionally, the upper computer 200 is specifically configured to obtain, according to the transmission time and the identification time corresponding to each circuit breaker, a target identification time between two adjacent transmission times; determining that the circuit breaker corresponding to the target identification time and the circuit breaker corresponding to the previous transmission time in the two adjacent transmission times are the same group of circuit breakers; and generating a topology level table according to the determined at least one group of circuit breakers.

The specific principle and the corresponding beneficial effects of the method executed by the upper computer and the circuit breaker in the system are clearly described in the foregoing embodiments, and are not described in detail herein.

In the several embodiments provided by the present invention, it should be understood that the disclosed apparatus and method may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in the embodiments of the present invention may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in hardware plus software functional units.

The integrated units implemented in the form of software functional units described above may be stored in a computer readable storage medium. The software functional unit is stored in a storage medium, and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor (english: processor) to perform some of the steps of the methods according to the embodiments of the invention. And the aforementioned storage medium includes: u disk, mobile hard disk, read-Only Memory (ROM), random access Memory (Random Access Memory, RAM), magnetic disk or optical disk, etc.

Claims

1. A method for identifying a topology network of a circuit breaker, the method comprising:

responding to a reading instruction of the upper computer, and feeding back the identification time to the upper computer so that the upper computer identifies a topology network according to the locally recorded sending time and the identification time, wherein the identification time is used for representing the identification time of the circuit breaker for identifying the topology signal sent by the lower-level circuit breaker; the locally recorded transmission time is used for representing the transmission time of the topology signal transmitted by the circuit breaker.

2. The method of claim 1, wherein the feeding back the identification time to the host computer in response to the read instruction of the host computer comprises:

3. The method of claim 1, wherein the identifying the topology signal sent by a lower circuit breaker in the topology network comprises:

4. A circuit breaker, comprising: the device comprises a processor, a topology generation unit, a topology identification unit, a communication module and a control circuit board; the processor is arranged on the control circuit board, and the communication module is arranged on the control circuit board in a pluggable manner;

the processor is also used for responding to the reading instruction of the upper computer and feeding back the identification time to the upper computer through the communication module so that the upper computer identifies the topology network according to the locally recorded sending time and the identification time; the locally recorded transmission time is used for representing the transmission time of the topology signal transmitted by the circuit breaker.

5. The circuit breaker of claim 4, wherein the processor is specifically configured to receive, via the communication module, the read command sent by the host computer at a preset interval.

6. The circuit breaker of claim 4, wherein the communication module comprises: a power line carrier communication module and/or an RS485 communication module.

7. The circuit breaker of claim 4, further comprising: a transformer;

the mutual inductor is connected with the topology identification unit;

8. The circuit breaker topology network identification method is characterized by being applied to an upper computer in a circuit breaker topology network, and comprises the following steps:

transmitting a reading instruction to the plurality of circuit breakers;

Receiving record data fed back by the plurality of circuit breakers according to the reading instruction, wherein the record data comprises: identifying the identification time of the topology signal sent by the lower circuit breaker;

identifying and acquiring a topology network according to the recorded data and the locally recorded sending time; the locally recorded transmission time is used for representing the transmission time of the topology signal transmitted by the circuit breaker.

9. The method of claim 8, wherein the identifying the acquisition topology network based on the recorded data and the locally recorded transmission time comprises:

10. The method of claim 9, wherein generating the topology level table based on the transmission time and the identification time for each of the circuit breakers comprises:

11. A circuit breaker topology network identification device, characterized by being applied to an upper computer in a circuit breaker topology network, the device comprising: the device comprises a sending module, a recording module, a receiving module and an identification module;

the receiving module is configured to receive record data fed back by the plurality of circuit breakers according to the reading instruction, where the record data includes: identifying the identification time of the topology signal sent by the lower circuit breaker;

the identification module is used for identifying and acquiring a topology network according to the recorded data and the locally recorded sending time; the locally recorded transmission time is used for representing the transmission time of the topology signal transmitted by the circuit breaker.

12. A circuit breaker topology network system, the system comprising: a host computer, a plurality of circuit breakers as claimed in any of claims 4 to 7; each breaker is connected with the upper computer; the circuit breakers form a multi-stage branch circuit, and each circuit breaker in each stage of branch circuit forms an upper-stage and lower-stage connection relationship;

the upper computer is used for receiving the identification time fed back by the plurality of circuit breakers according to the reading instruction, and identifying and acquiring the topology network according to the locally recorded sending time and the identification time; the locally recorded transmission time is used for representing the transmission time of the topology signal transmitted by the circuit breaker.