CN114156946A - Parallel inverter power balance control method based on common-mode voltage injection - Google Patents

Parallel inverter power balance control method based on common-mode voltage injection Download PDF

Info

Publication number
CN114156946A
CN114156946A CN202111493895.3A CN202111493895A CN114156946A CN 114156946 A CN114156946 A CN 114156946A CN 202111493895 A CN202111493895 A CN 202111493895A CN 114156946 A CN114156946 A CN 114156946A
Authority
CN
China
Prior art keywords
inverter
mode voltage
component
common mode
son
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202111493895.3A
Other languages
Chinese (zh)
Other versions
CN114156946B (en
Inventor
雷家兴
黄鑫林
陶以彬
席嫣娜
胡秦然
冯鑫振
张宏宇
赵文祎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Southeast University
China Electric Power Research Institute Co Ltd CEPRI
State Grid Beijing Electric Power Co Ltd
Original Assignee
Southeast University
China Electric Power Research Institute Co Ltd CEPRI
State Grid Beijing Electric Power Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Southeast University, China Electric Power Research Institute Co Ltd CEPRI, State Grid Beijing Electric Power Co Ltd filed Critical Southeast University
Priority to CN202111493895.3A priority Critical patent/CN114156946B/en
Publication of CN114156946A publication Critical patent/CN114156946A/en
Application granted granted Critical
Publication of CN114156946B publication Critical patent/CN114156946B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J3/00—Circuit arrangements for ac mains or ac distribution networks
    • H02J3/38—Arrangements for parallely feeding a single network by two or more generators, converters or transformers
    • H02J3/381—Dispersed generators
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/12—Arrangements for reducing harmonics from ac input or output
    • H02M1/126—Arrangements for reducing harmonics from ac input or output using passive filters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H02M7/53871—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J2300/00—Systems for supplying or distributing electric power characterised by decentralized, dispersed, or local generation
    • H02J2300/20—The dispersed energy generation being of renewable origin
    • H02J2300/22—The renewable source being solar energy
    • H02J2300/24—The renewable source being solar energy of photovoltaic origin
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/56—Power conversion systems, e.g. maximum power point trackers

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Control Of Electrical Variables (AREA)
  • Inverter Devices (AREA)

Abstract

The invention discloses a parallel inverter power balance control method based on common-mode voltage injection. The method injects an intrinsic and an additional common-mode voltage component into the main inverter reference output voltage, wherein the additional common-mode voltage component comprises the main inverter reference output current signal. N inverters on the slave inverter side are connected in parallel, and the nth slave inverter is controlled as follows: and carrying out proportional-integral-multimode resonance control on the zero sequence component of the output current to obtain an additional common-mode voltage component of the slave inverter, and extracting a reference output current signal of the master inverter from the zero sequence current controller to be used as the reference output current of the slave inverter. The invention can eliminate the communication line required by the traditional master-slave control, reduce the structural complexity of the parallel inverter system, ensure that the system automatically realizes power balance, has good dynamic and steady performance and is beneficial to improving the running performance of the parallel inverter.

Description

Parallel inverter power balance control method based on common-mode voltage injection
Technical Field
The invention belongs to the technical field of power electronics, and particularly relates to a parallel inverter control method based on common-mode voltage injection.
Background
With the rapid development of various new energy power generation technologies such as photovoltaic power generation, wind power generation and the like, renewable energy is becoming the main power in the power generation field, and most of the current renewable energy generates direct current electric energy which needs to be merged into a power grid through an inversion link, so that an inverter plays an irreplaceable role.
At present, the power required by electric equipment is increasingly large, a single inverter cannot meet the requirement, the problems of manufacturing cost increase, volume increase and the like are caused by simply increasing the power of the single inverter, and the influence of the fault of the single inverter on the continuous work of the whole system is very large, so that a parallel inverter system as shown in fig. 1 is generated. The parallel inverter can effectively improve the power to meet the requirement of high-power electric equipment, can also enhance the flexibility of the whole system, and is safer and more reliable when the system operates. With the continuous development and improvement of the control theory, a master-slave control mode based on communication and a droop control mode free of communication are derived in the aspect of parallel inverter system control. The principle of the traditional master-slave control is shown in fig. 2, the control signal generated by the master inverter is used as the given signal of the slave inverter to realize load balance, the control mode can enable the parallel inverter system to obtain better dynamic and steady-state performance, but the existence of the communication line makes the structure of the whole system more complex, and in addition, the equipment coupling phenomenon exists, which is not beneficial to the development of the parallel inverter. Although the traditional droop control mode has no communication line, the power automatic balance effect is poor, and the dynamic and steady-state performance is poor.
Disclosure of Invention
The invention aims to provide a parallel inverter power balance control method based on common-mode voltage injection, which does not need a communication line and only realizes information transmission by injecting common-mode voltage.
The purpose of the invention can be realized by the following technical scheme:
s1: according to the actual value i of the output current of the main invertermoTo i, pairmoActive component i ofmodAnd a reactive component imoqRespectively carrying out closed-loop control to obtain the output voltage reference value u of the main invertermo *；
S2: by umo *Calculating an intrinsic common-mode voltage component u of a main invertermoc1Constructing an additional common-mode voltage component u of the main inverter from the main inverter reference active and reactive current signalsmoc2；
S3: at umo *U obtained in step S2 is superimposedmoc1And umoc2Generating a control signal of the main inverter through sine pulse width modulation to control the main inverter;
s4: carrying out closed-loop control on the zero-sequence current generated by the nth slave inverter by using a zero-sequence current controller to obtain an additional common-mode voltage component u of the nth slave invertersonc2；
S5: obtaining reference active and reactive current signals of a main inverter from a zero sequence current controller as active and reactive components of reference output current of an nth slave inverter;
s6: according to the actual output current i of the nth slave invertersonTo i, pairsonActive component i ofsondAnd a reactive component isonqRespectively performing closed-loop control to obtain the reference value u of the output voltage of the slave inverterson *；
S7: by uson *Calculating intrinsic common mode voltage component u of nth slave invertersonc1In uson *U obtained by superpositionsonc1And usonc2And generating a control signal through sinusoidal pulse width modulation to control the nth slave inverter.
Further, the method for calculating the intrinsic and additional common mode voltage components injected by the main inverter in S2 specifically includes:
s2.1: calculating the intrinsic common mode voltage component u of the main inverter bymoc1：
Figure BDA0003400203640000021
Wherein max and min are respectively used for calculating the reference output voltage reference value u of the main invertermo *An operator of the maximum and minimum values;
s2.2: calculating an additional common mode voltage component u of the main inverter from the following equationmoc2：
umoc2＝imod *sin(ω1t)+imoq *sin(ω2t) (2)
Wherein imod *And imoq *Reference output active and reactive currents, omega, of the main inverter, respectively1And ω2Are two different frequencies at which information is communicated, t being time.
Further, the specific method for controlling the master inverter in S3 is as follows:
obtaining the intrinsic common mode voltage component u of the main invertermoc1Additional common mode voltage component umoc2And a reference output voltage umo *The three are added to obtain a resultant voltage vector umo **Using sinusoidal pulse width modulation to synthesize the voltage vector umo **And modulating to obtain a main inverter control signal, and realizing the control of the main inverter.
Further, in S4, the nth slave inverter-added common mode voltage component u is obtainedsonc2The method specifically comprises the following steps:
s4.1: calculating the zero sequence current actual value i of the nth slave inverter by the following formulason-0：
Figure BDA0003400203640000031
Wherein isona、isonbAnd isoncThe nth slave inverter outputs three-phase currents respectively;
s4.2: calculating the actual value i of the zero sequence current of the nth slave inverterson-0Difference from its reference value, the calculation result is set as eison-0；
S4.3: by zero sequence current controller G0n(s) to obtain eison-0Adjusting to obtain additional common-mode voltage component u of nth slave invertersonc2Zero sequence current controller G0n(s) comprises 5 sub-controllers, the expression for which is as follows:
G0n(s)＝G0n1(s)+G0n2(s)+G0n3(s)+G0n4(s)+G0n5(s) (4)
wherein:
Figure BDA0003400203640000032
in the formula (5), G0n1(s) and G0n2(s) proportional and integral controllers, respectively, kPAnd kIRespectively corresponding controller coefficients; g0n3(s) resonance controller for suppressing third harmonic, kRAs its coefficient, ωgFor mains voltageFrequency; g0n4(s) and G0n5(s) resonant controllers, k, each for suppressing zero-sequence currents generated by the addition of common-mode voltages to the main inverter1And k2Respectively corresponding controller coefficients, s being the differential element.
Further, in S5, a reference active component i of the nth inverter output current is obtainedsond *And a reference reactive component isonq *The method specifically comprises the following steps:
s5.1: according to zero sequence current controller G0n(s) as a result of the regulation, respectively, from G0n4(s) and G0n5(s) obtaining a signal containing information on the reference output current of the main inverter from the result of(s);
s5.2: squaring each component in the signal obtained in the S5.1, and filtering out a frequency-doubled component generated by the squaring by using a corresponding frequency-doubled wave trap;
s5.3: the filtering result of the wave trap obtained in the S5.2 is expanded to 2 times, then the square opening is carried out, and the reference output active current i of the nth slave inverter is obtainedsond *And a reactive current isonq *Wherein isond *And isonq *Are respectively equal to imod *And imoq *。
Further, in S7, the method for controlling the nth slave inverter specifically includes:
s7.1: according to the obtained uson *Calculating the intrinsic voltage component u of the nth slave inverter by the following formulasonc1：
Figure BDA0003400203640000041
Wherein max and min are the respective calculations uson *An operator of the maximum and minimum values;
s7.2: intrinsic common mode voltage component u of slave inverter of nth stationsonc1Additional common mode voltage component usonc2And a reference output voltage uson *The three are superposed to obtainResultant voltage vector uson **；
S7.3: using sinusoidal pulse width modulation to synthesize a voltage vector uson **And modulating to obtain a control signal of the nth slave inverter, realizing the control of the nth slave inverter and further finally realizing the control of the whole parallel inverter system.
After the scheme is adopted, the invention has the following beneficial effects:
1. the power of the parallel inverter system is effectively ensured to realize automatic balance in the master inverter and the slave inverter;
2. the complex communication line required by master-slave control can be eliminated by only improving and increasing the controllers, the structure and hardware cost of the whole system are reduced, and meanwhile, the equipment coupling phenomenon does not exist.
Drawings
FIG. 1 is a topology block diagram of a parallel inverter of the present invention;
FIG. 2 is a basic schematic diagram of a conventional master-slave control of the present invention;
FIG. 3 is a block diagram of a system control method according to the present invention;
FIG. 4 is a control block diagram of a master inverter in accordance with an embodiment of the present invention;
FIG. 5 is a diagram illustrating the calculation of the additional common mode voltage component u of the master inverter (slave inverter) according to the present inventionmo(uson) Schematic diagram of (1);
FIG. 6 is a control block diagram of slave inverter #1 in an embodiment of the present invention; (ii) a
FIG. 7 shows a zero sequence current controller G in slave inverter #1 according to an embodiment of the present invention0n(s)；
FIG. 8 shows an embodiment of the present invention for obtaining a reference active output current i from inverter #1so1d *And a reference reactive output current iso1q *Schematic diagram of (1);
fig. 9 is the output current simulation result using the proposed control method on a parallel inverter.
Detailed Description
For the steps of the parallel inverter control method based on common mode voltage injection proposed by the present invention, the control method will be specifically described below by taking the example of parallel connection of two inverters (master inverter + slave inverter #1) in conjunction with fig. 3-8 in the embodiment of the present invention, fig. 9 is the simulation result of the output current of the two inverters,
according to the control block diagram of the main inverter as shown in fig. 4, the actual voltage u of the power grid is obtained by the voltage measuring devicegObtaining the actual output current i of the main inverter by a current measuring devicemoAnd actual output current i from inverter #1so1。
According to the obtained ugAnd imoCalculating the phase angle difference theta between the two, and calculating i from equation (1)moActive component i ofmodAnd a reactive component imoq：
Figure BDA0003400203640000051
According to the given main inverter output current reference active component imod *And a reactive component imoq *Respectively calculate imodAnd imoqError e between actual value and reference valueimodAnd eimoqUsing a current PI controller Gm(s) are each for eimodAnd eimoqRegulated in conjunction with the mains voltage ugObtaining a reference output voltage u of the main inverter by inverse PARK conversionmo *。
From the schematic diagram shown in fig. 5, the intrinsic common-mode voltage component u of the main inverter is calculated in combination with equation (2)moc1：
Figure BDA0003400203640000052
U is within one cyclemoc1In the presence of umoa */2、umob *A combination of u and 2moc *-2 three different values;
let omega1And ω2Respectively 100Hz and 200Hz, calculating the main inverse according to equation (3)Additional common mode voltage components u of different frequencies injected by the convertermoc2：
umoc2＝imod *sin(200πt)+imoq *sin(400πt)(3)
The obtained umoc1And umoc2Is superimposed on umo *In (c), a resultant voltage component u is obtainedmo **By sinusoidal pulse width modulation of umo **And modulating to obtain a control signal of the main inverter, and realizing the control of the main inverter.
Control block diagram of slave inverter #1 as shown in fig. 6, actual output current i from inverter #1 is measuredso1The zero-sequence current actual value i from inverter #1 is calculated by equation (4)so1-0：
Figure BDA0003400203640000053
I is calculated according to the zero sequence current reference value 0 of the slave inverter #1so1-0And iso1-0 *Error e ofiso1-0Zero sequence current controller G shown in FIG. 701(s) to error eio1-0Regulation is performed to obtain an additional common mode voltage component u from inverter #1so1c2。
From the zero sequence current controller shown in fig. 7, G is based on the principle that the circulating current of the parallel inverter is zero014(s) and G015(s) obtaining a signal containing information on the reference output current of the main inverter from the result of(s); according to the schematic diagram shown in FIG. 8, for i contained in the signalmod *sin (200 π t) and imoq *sin (400 pi t) is respectively squared to obtain a result shown in a formula (5), two traps with frequencies of 400 pi and 800 pi are adopted to filter components with frequencies of 400 pi and 800 pi in the formula (5), the filtering result is expanded to 2 times and then is squared, and output reference active current i from the inverter #1 is obtainedso1d *And a reference reactive current iso1q *Wherein iso1d *And iso1q *Are respectively equal to imod *And imoq *。
Figure BDA0003400203640000061
Actual output current i from inverter #1 based on the measurementso1And the actual voltage u of the networkgCalculating the power factor angle theta between the two1Calculating i from equation (6)so1Active component i ofso1dAnd a reactive component iso1q：
Figure BDA0003400203640000062
Calculate iso1d *And iso1d、iso1q *And iso1qDifference e betweeniso1dAnd eiso1qUsing a current PI controller Gs1(s) are each for eiso1dAnd eiso1qControl is carried out in combination with the network voltage ugObtaining a reference output voltage u from inverter #1 by inverse PARK conversionso1 *。
From the schematic diagram shown in fig. 5, the intrinsic common-mode voltage component u of the slave inverter #1 is calculated by the combination formula (7)so1c1：
Figure BDA0003400203640000063
U is within one cycleso1c2Also in the presence of uso1a */2、uso1b *A combination of u and 2so1c *-2 three different values;
subjecting the obtained u toso1c1And uso1c2Is superimposed on uso1 *In (c), a resultant voltage component u is obtainedso1 **By sinusoidal pulse width modulation of uso1 **Modulating to obtain control signals of the slave inverter #1, realizing the control of the slave inverter #1, and finally realizing the parallel inversion of the master inverter and the slave inverter #1And (4) controlling the machine system.
As can be seen from fig. 9, both the master inverter and the slave inverter #1 can achieve output current equalization, and thus, automatic power equalization.
The above embodiments are only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited thereby, and any modifications made on the basis of the technical scheme according to the technical idea of the present invention fall within the protection scope of the present invention.

Claims (6)

1. A parallel inverter power balance control method based on common mode voltage injection is characterized in that a parallel system is formed by a master inverter and N slave inverters, the structure and the control method of the N slave inverters are the same, and the control method of the master inverter and the slave inverters comprises the following steps:
s1: according to the actual value i of the output current of the main invertermoTo i, pairmoActive component i ofmodAnd a reactive component imoqRespectively carrying out closed-loop control to obtain the output voltage reference value u of the main invertermo *；
S2: by umo *Calculating an intrinsic common-mode voltage component u of a main invertermoc1Constructing an additional common-mode voltage component u of the main inverter from the main inverter reference active and reactive current signalsmoc2；
S3: at umo *U obtained in step S2 is superimposedmoc1And umoc2Generating a control signal of the main inverter through sine pulse width modulation to control the main inverter;
s4: carrying out closed-loop control on the zero-sequence current generated by the nth slave inverter by using a zero-sequence current controller to obtain an additional common-mode voltage component u of the nth slave invertersonc2；
S5: obtaining reference active and reactive current signals of a main inverter from a zero sequence current controller as active and reactive components of reference output current of an nth slave inverter;
s6: according to the actual output current i of the nth slave invertersonTo i, pairsonIs provided withWork component isondAnd a reactive component isonqRespectively performing closed-loop control to obtain the reference value u of the output voltage of the slave inverterson *；
S7: by uson *Calculating intrinsic common mode voltage component u of nth slave invertersonc1In uson *U obtained by superpositionsonc1And usonc2And generating a control signal through sinusoidal pulse width modulation to control the nth slave inverter.
2. The parallel inverter power balance control method based on common mode voltage injection as claimed in claim 1, wherein: in S2, the method for calculating the intrinsic and additional common mode voltage components injected by the main inverter is as follows:
s2.1: calculating the intrinsic common mode voltage component u of the main inverter bymoc1：
Figure FDA0003400203630000011
Wherein max and min are respectively used for calculating the reference output voltage reference value u of the main invertermo *An operator of the maximum and minimum values;
s2.2: calculating an additional common mode voltage component u of the main inverter from the following equationmoc2：
umoc2＝imod *sin(ω1t)+imoq *sin(ω2t) (2)
Wherein imod *And imoq *Reference output active and reactive currents, omega, of the main inverter, respectively1And ω2Are two different frequencies at which information is communicated, t being time.
3. The parallel inverter power balance control method based on common mode voltage injection as claimed in claim 1, wherein: the specific method in S3 is as follows:
obtaining the intrinsic common mode voltage component u of the main invertermoc1Additional common mode voltage component umoc2And a reference output voltage umo *The three are added to obtain a resultant voltage vector umo **Using sinusoidal pulse width modulation to synthesize the voltage vector umo **And modulating to obtain a main inverter control signal, and realizing the control of the main inverter.
4. The parallel inverter power balance control method based on common mode voltage injection as claimed in claim 1, wherein: in S4, the nth slave inverter-added common mode voltage component u is obtainedsonc2The method comprises the following steps:
s4.1: calculating the zero sequence current actual value i of the nth slave inverter by the following formulason-0：
Figure FDA0003400203630000021
Wherein isona、isonbAnd isoncThe nth slave inverter outputs three-phase currents respectively;
s4.2: calculating the actual value i of the zero sequence current of the nth slave inverterson-0Difference from its reference value, the calculation result is eison-0；
S4.3: by zero sequence current controller G0n(s) to obtain eison-0Adjusting to obtain additional common-mode voltage component u of nth slave invertersonc2Zero sequence current controller G0n(s) comprises 5 sub-controllers, the expression for which is as follows:
G0n(s)＝G0n1(s)+G0n2(s)+G0n3(s)+G0n4(s)+G0n5(s) (4)
wherein:
Figure FDA0003400203630000022
in the formula (5), G0n1(s) and G0n2(s) proportional and integral controllers, respectively, kPAnd kIRespectively corresponding controller coefficients; g0n3(s) resonance controller for suppressing third harmonic, kRAs its coefficient, ωgIs the grid voltage frequency; g0n4(s) and G0n5(s) resonant controllers, k, each for suppressing zero-sequence currents generated by the addition of common-mode voltages to the main inverter1And k2Respectively corresponding controller coefficients, s being the differential element.
5. The parallel inverter power balance control method based on common mode voltage injection as claimed in claim 4, wherein: in the step 5, a reference active component i of the output current of the nth slave inverter is obtainedsond *And a reference reactive component isonq *The method comprises the following steps:
s5.1: according to zero sequence current controller G0n(s) as a result of the regulation, respectively, from G0n4(s) and G0n5(s) obtaining a signal containing information on the reference output current of the main inverter from the result of(s);
s5.2: squaring each component in the signal obtained in the S5.1, and filtering out a frequency-doubled component generated by the squaring by using a corresponding frequency-doubled wave trap;
s5.3: the filtering result of the wave trap obtained in the S5.2 is expanded to 2 times, then the square opening is carried out, and the reference output active current i of the nth slave inverter is obtainedsond *And a reactive current isonq *Wherein isond *And isonq *Are respectively equal to imod *And imoq *。
6. The parallel inverter power balance control method based on common mode voltage injection as claimed in claim 1, wherein: in step 7, the method for controlling the nth slave inverter includes:
s7.1: according to the obtained uson *The characteristics of the nth slave inverter are calculated by the following formulaVoltage component usonc1：
Figure FDA0003400203630000031
Wherein max and min are the respective calculations uson *An operator of the maximum and minimum values;
s7.2: intrinsic common mode voltage component u of slave inverter of nth stationsonc1Additional common mode voltage component usonc2And a reference output voltage uson *The three are superposed to obtain a resultant voltage vector uson **；
S7.3: using sinusoidal pulse width modulation to synthesize a voltage vector uson **And modulating to obtain a control signal of the nth slave inverter, realizing the control of the nth slave inverter and further finally realizing the control of the whole parallel inverter system.
CN202111493895.3A 2021-12-08 2021-12-08 Parallel inverter power balance control method based on common-mode voltage injection Active CN114156946B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111493895.3A CN114156946B (en) 2021-12-08 2021-12-08 Parallel inverter power balance control method based on common-mode voltage injection

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111493895.3A CN114156946B (en) 2021-12-08 2021-12-08 Parallel inverter power balance control method based on common-mode voltage injection

Publications (2)

Publication Number Publication Date
CN114156946A true CN114156946A (en) 2022-03-08
CN114156946B CN114156946B (en) 2023-08-22

Family

ID=80453959

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111493895.3A Active CN114156946B (en) 2021-12-08 2021-12-08 Parallel inverter power balance control method based on common-mode voltage injection

Country Status (1)

Country Link
CN (1) CN114156946B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117013611A (en) * 2023-07-12 2023-11-07 浙江艾罗网络能源技术股份有限公司 Inverter parallel system, control method and energy control method
EP4318849A1 (en) * 2022-08-03 2024-02-07 Shenzhen Poweroak Newener Co., Ltd Adaptive control method for multiple inverters in parallel and system with multiple inverters in parallel

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105048845A (en) * 2015-06-29 2015-11-11 电子科技大学 System inhibiting parallel zero-sequence circulating current of three-level inverter
CN109066820A (en) * 2018-10-23 2018-12-21 四川大学 Shunt chopper power-sharing device and control method based on electric current droop characteristic
CN111600336A (en) * 2020-05-27 2020-08-28 国网山西省电力公司电力科学研究院 Photovoltaic inverter control method considering voltage support during unbalanced voltage sag

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105048845A (en) * 2015-06-29 2015-11-11 电子科技大学 System inhibiting parallel zero-sequence circulating current of three-level inverter
CN109066820A (en) * 2018-10-23 2018-12-21 四川大学 Shunt chopper power-sharing device and control method based on electric current droop characteristic
CN111600336A (en) * 2020-05-27 2020-08-28 国网山西省电力公司电力科学研究院 Photovoltaic inverter control method considering voltage support during unbalanced voltage sag

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4318849A1 (en) * 2022-08-03 2024-02-07 Shenzhen Poweroak Newener Co., Ltd Adaptive control method for multiple inverters in parallel and system with multiple inverters in parallel
CN117013611A (en) * 2023-07-12 2023-11-07 浙江艾罗网络能源技术股份有限公司 Inverter parallel system, control method and energy control method

Also Published As

Publication number Publication date
CN114156946B (en) 2023-08-22

Similar Documents

Publication Publication Date Title
Wu et al. Analysis and design of vector control for VSC-HVDC connected to weak grids
CN108616141B (en) Control method for LCL grid-connected inverter power nonlinearity in microgrid
Xue et al. A complete impedance model of a PMSG-based wind energy conversion system and its effect on the stability analysis of MMC-HVDC connected offshore wind farms
Prodanovic et al. Control and filter design of three-phase inverters for high power quality grid connection
Hu et al. Impedance characteristic analysis and stability improvement method for DFIG system within PLL bandwidth based on different reference frames
CN102223100A (en) Control method of three-phase grid-connected inverter based on modified proportional resonant regulator
CN114156946A (en) Parallel inverter power balance control method based on common-mode voltage injection
CN110676874B (en) Direct-drive fan subsynchronous oscillation electrical quantity analysis method considering frequency coupling effect
CN106712115B (en) A kind of virtual synchronous engine controller without current feedback
CN112701720B (en) Hybrid control method for constant power load of alternating-current micro-mesh belt
CN113890096B (en) Converter sequence impedance modeling method in rectification inversion mode
CN112886647B (en) Load virtual synchronous machine coordination optimization control method based on impedance remodeling
CN110752762A (en) Control method for parallel virtual capacitor of grid-connected converter
CN113098033B (en) Self-adaptive virtual inertia control system and method based on flexible direct current power transmission system
CN113378347B (en) Wind turbine generator frequency domain impedance modeling method based on modularized multiport
CN106099969A (en) A kind of megawatt-grade high-power wired in parallel control method based on series inductance
Ma et al. Second-order linear active disturbance rejection control and stability analysis of energy storage grid-connected inverter
CN103366053B (en) A kind of improvement of Voltage-oriented control strategy and Mathematical Modeling Methods
CN109088428B (en) High voltage ride through device, method and current transformation system comprising device
CN104362675A (en) Inverter system and photovoltaic grid inverter control method and device
Tian et al. Virtual impedance refined inductor current observation and current sensorless control for grid-connected inverter
Wang Optimization strategy of DSOGI-PLL precision under harmonic interference conditions
CN115498708B (en) Grid-connected VSC and power grid interaction analysis method based on frequency response method
Gong et al. Grid-Connection Control of Doubly Fed Variable Speed Pumped Storage Unit
Bai et al. Design of Single-phase PWM Rectifier Based on PI Double-loop Control

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant