CN114153416B - Display control method and related device - Google Patents

Display control method and related device Download PDF

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Publication number
CN114153416B
CN114153416B CN202111436456.9A CN202111436456A CN114153416B CN 114153416 B CN114153416 B CN 114153416B CN 202111436456 A CN202111436456 A CN 202111436456A CN 114153416 B CN114153416 B CN 114153416B
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buffer
image
image frame
frame
display
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CN114153416A (en
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白颂荣
张海越
陈锋
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Shenzhen Xihua Technology Co Ltd
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Shenzhen Xihua Technology Co Ltd
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G06F3/147Digital output to display device ; Cooperation and interconnection of the display device with other functional units using display panels
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39Control of the bit-mapped memory
    • G09G5/393Arrangements for updating the contents of the bit-mapped memory
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39Control of the bit-mapped memory
    • G09G5/395Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00Control of display operating conditions
    • G09G2320/02Improving the quality of display appearance
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00Aspects of the architecture of display systems
    • G09G2360/12Frame memory handling

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Human Computer Interaction (AREA)
  • General Engineering & Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)

Abstract

The embodiment of the application provides a display control method and a related device, which can be applied to the field of image display. The method comprises the following steps: the display controller writes a first image frame into a first buffer, wherein the first buffer is any buffer in the plurality of buffers; the display controller continuously reads the first image frames from the first buffer N times to display a first image; the display controller outputs a first signal for requesting a new image frame, N being an integer greater than 0 and being related to a writing speed and a reading speed of the first image frame. The embodiment of the application can improve the smoothness of image display on the basis of ensuring the image display quality.

Description

Display control method and related device
Technical Field
The present disclosure relates to image processing technologies, and in particular, to a method and a related device for controlling display.
Background
With the development of science and technology, the requirements for image processing in life are higher and higher, and the common image Frame Buffer (Frame Buffer) control flow is similar to the control of a first-in first-out Buffer (First Input First Output, FIFO), and the read-write speed of the image Frame Buffer is controlled so that the read overflow or the write overflow cannot occur.
When the image frame buffer writing speed is higher than the reading speed and the writing pointer catches up with the reading pointer, or the image frame buffer reading speed is higher than the writing speed and the reading pointer catches up with the writing pointer, the phenomenon that the display pictures display a part of new and old pictures respectively, namely tearing. Because the moment of each frame input by the application host (Application Processor, AP) is substantially predictable, read and write operations can be guaranteed to be out of catch with each other by controlling the moment of the start of the image frame buffer read and write and the appropriate frame dropping mechanism.
When the read-write operation is in the same image frame, if the read pixels are not written into the buffer area at a certain moment, a tearing phenomenon can occur, so that the image cannot be normally displayed, the quality of the image is lost, and the watching experience of a user is affected.
Disclosure of Invention
The embodiment of the application provides a display control method and a related device, which improve the fluency of image display on the basis of ensuring the image display quality.
In a first aspect, an embodiment of the present application provides a display control method, which is applied to a display control device including a plurality of buffers, where the plurality of buffers are used to alternately write a plurality of image frames, and includes:
Writing a first image frame to a first buffer, the first buffer being any one of the plurality of buffers;
continuously reading the first image frames from the first buffer N times to display a first image;
a first signal is output for requesting a new image frame, N is an integer greater than 0 and is related to a writing speed and a reading speed of the first image frame.
In the above method, the possibility of the occurrence of the tearing phenomenon can be reduced by alternately writing a plurality of image frames through a plurality of buffers.
For example, if there are two buffers (which are called a first buffer and a second buffer for convenience of distinction), if a write (read) operation is performed in the first buffer last time, a write (read) operation is performed in the second buffer at this time, so when a read operation is performed in one buffer, a write operation can be performed in the other buffer, so that the read operation can be performed after the write operation is completed, thereby avoiding a tearing phenomenon and improving the smoothness of image display.
In addition, the method can also adjust the number of times of reading operation on one buffer zone according to the writing speed and the reading speed. For example, when the writing speed is faster than the reading speed, N may be 1, and after 1 reading operation is performed on one buffer, a first signal is generated to request a new image frame, so that the image can be written as soon as possible, the display quality is ensured, and no tearing phenomenon occurs.
For example, when the reading speed is faster than the writing speed, N may be 2 (or greater), and at this time, after 2 times of reading operations are performed on one buffer, a first signal is generated to request a new image frame, so that the image reading speed can adapt to the image writing speed, and thus the possibility of tearing phenomenon can be reduced, and since the image frame of the reading operation is complete, it is ensured that the image quality of the displayed image is not greatly lost.
In a second aspect, an embodiment of the present application provides a display control device, where the display control device includes a plurality of buffers, an input unit, a processing unit, and an output unit, and the display control device is configured to implement the method described in the first aspect or any possible implementation manner of the first aspect.
In a third aspect, embodiments of the present application provide a display control apparatus, where the display control apparatus includes a processor and a memory, where the memory is configured to store computer instructions, and where the processor is configured to invoke the computer instructions, where the display control apparatus is configured to implement the method described in the first aspect or any possible implementation manner of the first aspect.
In a fourth aspect, embodiments of the present application provide a computer-readable storage medium having instructions stored therein that, when executed on at least one processor, implement the method described in the first aspect.
The advantages of the technical methods provided in the second to fourth aspects of the present application may refer to the advantages of the technical solutions of the first aspect, and are not described herein again.
Drawings
The drawings that are used in the description of the embodiments will be briefly described below.
Fig. 1 is a block diagram of one possible image display device 10 provided in an embodiment of the present application;
FIG. 2 is a schematic view of a possible image display scenario provided by an embodiment of the present application;
FIG. 3 is a schematic diagram of an operational sequence during one possible image rotation provided by an embodiment of the present application;
FIG. 4 is a block diagram of a display control system according to an embodiment of the present disclosure;
fig. 5 is a schematic flow chart of a display control method according to an embodiment of the present application;
FIG. 6 is a schematic diagram of a read-write process for a buffer according to an embodiment of the present application;
FIG. 7 is a schematic diagram of another read-write process for a buffer according to an embodiment of the present disclosure;
fig. 8 is a schematic structural diagram of a display control device 80 according to an embodiment of the present application;
fig. 9 is a schematic structural diagram of a display control apparatus 90 provided in an embodiment of the present application.
Detailed Description
Embodiments of the present application will be described in detail below with reference to the accompanying drawings.
For ease of understanding, technical terms related to the embodiments of the present application will be briefly described.
1. Command mode
In the command mode, a control device (e.g., a host processor) may control peripheral devices (e.g., display modules) of a display controller by sending commands. Wherein the display controller may contain local registers and buffers, the control device may write and read the registers using commands.
For example, the control device may indirectly control the functions of the peripheral device (display module) by sending commands and parameters to the display controller. The control device may also read status information of the display module.
Command mode may enable control of other devices through a bi-directional interface.
2. Tear Effect (TE) signal
The TE signal is adapted to indicate when the display controller is ready to refresh the next frame of image. For example, taking the display controller as an example of a display chip, the TE signal is generated when the chip is ready to refresh the next frame of image.
For example, the TE signal may be sent to an application host (Application Processor, AP). Correspondingly, after the AP monitors the rising edge of the TE signal or detects that the TE signal is in a high level state, the AP sends the next image frame to the chip.
3. LCD Controller (LCD Controller, LCDC)
LCDC is a part of a display subsystem at the host side, is responsible for processing data and controlling signals, and is mainly responsible for acquiring image or video data from a memory or a first-in first-out buffer (First Input First Output, FIFO) as a video card plays a role in a computer, superposing and mixing the image or video data in a certain way, and sending the final image to an external liquid crystal display for display, and generating necessary LCD control signals.
4. Low temperature polycrystalline oxide (Low Temperature Polycrystalline Oxide, LTPO)
LTPO is a back-plate technology that automatically increases the refresh rate when a mobile phone displays a moving picture, and automatically decreases the refresh rate when a mobile phone displays a still picture, thereby effectively reducing power consumption.
5. Image display process
When displaying an image, the display reads data from the display buffer and displays the data. However, since many images require a large amount of computation to be rendered, it takes a long time to write into the display buffer, making it difficult for the display to access the display buffer once and write the complete image data to be displayed.
In general, for complex images, it is necessary to access the display buffer a plurality of times, with the latest calculated image data being written each time of access. The consequences of this are: the display effect seen by the user may be partially displayed, causing significant flicker discontinuities.
With double buffering, the intermediate result of calculation can be stored in another buffer area, and after the complete image is stored in the buffer area, the image data of the buffer area is copied to the display buffer area at one time.
Fig. 1 is a schematic diagram of a possible image display device 10 according to an embodiment of the present application, where the image display device includes a display 101, a display buffer 102, and a custom buffer 103. The custom buffer 103 is used for storing the intermediate result of the calculation, and the display buffer 102 is used for reading the image data by the display 101 for displaying. Typically, the display buffer 102 is integral with the display 101, from which the display can read data for later display. The operation of drawing a straight line on the display is usually done by writing data into the display buffer. The display may cause the data in the display buffer to be displayed by the display to reflect its changes by continually refreshing (i.e., reading the data from the display buffer).
The above-mentioned related term explanations may be applied to the following embodiments.
The following describes the scenario and architecture of the embodiments of the present application.
In scenes such as image processing, image display and the like, flickering phenomenon often occurs in images, and transition of the images appears to be unsmooth.
In some scenarios, what is displayed in the screen will typically be stored in a display buffer. In the case of image display, the display controller processes the image using the display buffer, and any operation procedure in the display buffer is displayed on the screen. The method of processing the image by using a display buffer can easily cause tearing of the display of the image. For example, a Frame Buffer (FIFO) control flow may employ control like a FIFO (first in first out) Buffer (First Input First Output), by controlling the speed of Frame image Buffer reading and writing so that no read overflow or write overflow occurs. At this time, when the writing speed of the frame image buffer memory is faster than the reading speed and the writing pointer catches up with the reading pointer, a phenomenon that a part of the new and old pictures are displayed on the display picture, namely a tearing phenomenon, may occur; for another example, when the read-out speed of the frame image buffer is faster than the write-in speed, and the read pointer catches up with the write pointer, a tearing phenomenon may also occur.
As shown in fig. 2, a schematic view of a possible image display provided in the embodiment of the present application is shown, where a portion (a) of fig. 2 is a normally displayed image, and a portion (b) of fig. 2 is a possibly torn image, it can be seen that, in the displayed image, a portion of new and old images are displayed, that is, a portion of the displayed image is a pixel of the present frame, and a portion of the displayed image is a pixel of the previous frame, so that the image display is incomplete and unsmooth, resulting in poor viewing experience of a user.
For example, when an image is rotated 90 ° (for example only), tearing may occur if the image is read from or written to a display buffer.
FIG. 3 is a schematic diagram of an operational sequence during one possible image rotation provided by an embodiment of the present application, wherein solid arrows are the sequence of image writing operations, and FIG. 3 is a left to right, top to bottom scan of an image; the dashed arrows are the sequence of image reading operations, scanning from top to bottom and left to right as shown in fig. 3. Because the read-write operation is performed in the same display buffer, if the pixel read at a certain moment is not written into the buffer, a tearing phenomenon is caused.
In view of this, the technical scheme of the application is provided.
The architecture of the embodiments of the present application is described below. Referring to fig. 4, fig. 4 is an architecture diagram of a display control system according to an embodiment of the present application, where the system includes an image frame generating module 401 and a display controller 402.
The image frame generation module 401 is an electronic device having an image output capability, and may be, for example, a terminal device, a network device, or the like. Specifically, the image frame generation module 401 may be an application host (Application Processor, AP), a handheld terminal, a host, a personal computer, a wearable device, a vehicle, a robot, or the like. It should be appreciated that the image frame generation module 401 may be a stand-alone device, such as an AP, or may be a module within a stand-alone device, such as a chip, integrated circuit, or software module within an AP, or the like.
The display controller 402 is a device having the capability of controlling the display of images. The display controller 402 may comprise hardware, software, or a combination of hardware and software, for example, the display controller 402 may be implemented by one or more of a chip, a circuit (or integrated circuit), a processor, a computer program, computer instructions, or the like.
Alternatively, the display controller 402 may be (or be included in) an application host (Application Processor, AP), a handheld terminal, a host, a personal computer, a wearable device, a vehicle, a robot, or the like. It should be appreciated that the display controller 402 may be a stand-alone device, such as an AP, or may be a module within a stand-alone device, such as a chip, integrated circuit, or software module within an AP, or the like.
The display controller 402 includes a plurality of buffers 403. Optionally, the display controller 402 may also include a processing module 405, an output module 406, and the like. Further optionally, the display controller 402 also includes an input module 406. Wherein the input module 404 is used for inputting image frames, the processing module 405 is used for performing read operations and/or write operations, and the output module 406 is used for outputting signals.
It should be noted that, the image frame generation module 401 and the display controller 402 may be integrated or independent. For example, both may be integrated in the same AP. Alternatively, in the case where the image frame generation module 401 and the display controller 402 are integrated devices, the display controller 402 may not include an input module.
In this embodiment, the plurality of buffers 403 may be used to alternately write a plurality of image frames and/or alternately read a plurality of image frames. When one buffer area performs a read operation, the rest (part or all) of the buffer areas can perform a write operation, so that the read operation can be performed after the write operation is completed, a tearing phenomenon can not occur, and the smoothness of image display is improved.
For example, taking the display controller including the buffer 1 and the buffer 2 as an example, if the write operation is performed in the buffer 1 last time, the write operation is performed in the buffer 2 this time. Similarly, if the last time a read operation was performed in buffer 1, then the current time a read operation was performed in buffer 2. Therefore, the possibility of tearing phenomenon can be reduced and the fluency of image display can be improved by performing alternate writing operation and reading operation through the two buffer areas.
Optionally, buffers 1, 2, … in the present application are custom buffers as described above. Or alternatively buffers 1, 2 … in the present application are display buffers belonging to the foregoing.
In some possible implementations, the display controller 402 may also adjust the number of read operations to one buffer based on the write speed and the read speed.
For example, when the writing speed is faster than the reading speed, N may be 1, and after 1 reading operation is performed on one buffer, a first signal is generated to request a new image frame, so that the image can be written as soon as possible, the display quality is ensured, and no tearing phenomenon occurs.
For example, when the reading speed is faster than the writing speed, N may be 2 (or greater), and at this time, after 2 times of reading operations are performed on one buffer, a new image frame is requested to be output by the first signal, so that the image reading speed can adapt to the image writing speed, and thus the possibility of tearing phenomenon can be reduced, and since the image frame of the reading operation is complete, the image quality of the displayed image is ensured not to be greatly lost.
In one design, the display control device may include three buffers (e.g., buffer 1, buffer 2, and buffer 3, respectively), where buffer 1 is a front buffer and buffers 2 and 3 are rear buffers. Immediately after the writing (reading) operation of the buffer 2 is completed, the processing of the buffer 3 is started. The display card can vacate the buffer 2 without waiting for the buffer 1 to empty, and can put the result into the buffer 3 at any time. The three buffers have no waiting time for the frame sync signal (VSYNC) of the image mode, which makes the display smoother.
It should be understood that the division of the plurality of modules shown in fig. 4 is only a logical division according to functions, and is not a limitation of a specific structure of the probe apparatus. In a specific implementation, part of the modules may be subdivided into more tiny functional modules, and part of the functional modules may be combined into one functional module.
For example, the processing module may be subdivided into a write module and a read module.
The method of the embodiment of the present application is described in detail below.
Referring to fig. 5, fig. 5 is a flowchart of a display control method according to an embodiment of the present application.
Alternatively, the method may be applied to the display control system shown in fig. 4. The display control method as shown in fig. 4 includes steps S501 to S503. It should be understood that the description of the present application by the order of S501 to S503 is for convenience of description, and is not intended to limit the execution by the above order. The execution sequence, execution time, execution number, and the like of the one or more steps are not limited.
Step S501 to step S503 are specifically as follows:
step S501: the display controller writes a first image frame to the first buffer.
Wherein the display controller may comprise a plurality of buffers, e.g. 2, 3 buffers. The first buffer is any buffer in a plurality of buffers.
Image frames, which may also be referred to as image data, are used to present an image frame in a display. For example, an image frame may contain a plurality of pixels, each of which contains a color, shade, etc. of the pixel. The display can correspondingly present images with colors and textures according to the image frames in the buffer area.
Optionally, after the display controller writes the first image frame to the first buffer, the display controller writes the second image frame to a second buffer, where the second buffer belongs to the plurality of buffers.
For example, as shown in fig. 4, after the display controller writes the first image frame to the buffer 1, the second image frame is written to the buffer 2.
Step S502: the display controller continuously reads the first image frames from the first buffer N times to display a first image.
Wherein N is an integer greater than 0, e.g., N can be 1,2,3, … …
Optionally, N is related to a writing speed and a reading speed of the first image frame. For example, when the writing speed and the reading speed satisfy a certain predefined condition, N may be a certain value.
For example, if the writing speed of the first image frame is greater than the reading speed or the reading speed is greater than the writing speed, the number of times N of continuously reading the first image frame from the first buffer is affected.
For ease of understanding, the effect of the size relationship of the write speed and the read speed on the number N is described below by taking two buffers as examples:
in the first aspect, when the writing speed of the first image frame is greater than the reading speed, n=1. That is, after the display controller reads the first image frame 1 time from the first buffer, another buffer may be read.
At this time, after 1 reading operation is performed on the first buffer area, a new image frame can be written in the first buffer area, so that the image can be written in as soon as possible, the display quality is ensured, and the tearing phenomenon can not occur.
Optionally, the display controller may generate the first signal after performing 1 read operation on the first buffer. Accordingly, the apparatus inputting the image frames may input new image frames according to the first signal, so that the new image frames may be written in the first buffer.
In the second scheme, when the writing speed of the first image frame is smaller than the reading speed, N > 1, for example, n=2. That is, after 2 consecutive first image frames are read from the first buffer by the display controller, another buffer may be read so that the speed of image reading can be adapted to the speed of image writing. Therefore, the possibility of tearing phenomenon can be reduced, and the image quality of the displayed picture is ensured not to be greatly lost because the image frame of the reading operation is complete.
Of course, after the display controller completes 2 read operations of the first buffer, a new image frame may be written in the first buffer in order to be ready for the next read.
Alternatively, the display controller may generate the first signal after performing 2 read operations on the first buffer. Accordingly, the apparatus for inputting image frames may input new image frames to the display controller according to the first signal, so that the new image frames may be written in the first buffer.
In an alternative, N may be 3, 4, or 5, and the display controller is to read the first image frame from the first buffer 3 times in succession, or read 4 times in succession, or read 5 times in succession, but the writing speed of the first image frame is smaller than the reading speed.
For ease of description, the embodiments of the present application only discuss the problem of how fast a write speed is compared to a read speed, and do not discuss the specific speeds.
Optionally, after the N times of continuous reading of the first image frames, M times of continuous reading of the second image frames from the second buffer area are performed to display a second image. Similarly, M is a positive integer greater than 0, and M is typically the same as N. Of course, if the read-out speed and the write-in speed of the second image frame are not exactly the same as the read-in speed and the write-in speed of the first image frame, N and M may be different.
Step S503: the display controller outputs a first signal.
Wherein the first signal is for requesting a new image frame for writing into the first buffer.
The first signal may be a signal that the buffer is ready for indicating that a new buffer may be written. For example, the first signal may be a TE signal (specifically referred to the term description section). For another example, the first signal may be a Status Flag (Status Flag), and when the Flag is 1, it indicates that the buffer image frame is read, and a new buffer may be written.
It will be appreciated that the buffer needs to be initialized before it can be used for reading or writing. For example, one or more initial read operations to the buffer may be performed, and the TE signal may be generated after the read operation is completed (or the buffer ready message, etc.).
In one possible design, the TE signals may include full frame update (Full Frame Update, FU) signals and local frame update (Partial Frame Update, PU) signals. When the TE signal is the FU signal, the new image frame requested by the display controller is a complete one. When the TE signal is a PU signal, the image frame requested by the display controller may be an incomplete image frame.
Optionally, after continuously reading M second image frames in the second buffer, the display controller may further output a second signal, where M is an integer greater than 0, for requesting a new image frame (for writing into the second buffer).
For ease of understanding, the following description will be given in detail of the read/write process of two buffers by way of illustration, taking two buffers as examples.
In an example one, as shown in fig. 6, fig. 6 is a schematic diagram of a read-write process for a buffer according to an embodiment of the present application, where a solid line represents a read waveform for the buffer, and a dotted line represents a write waveform for the buffer. It can be seen that in the read-write process shown in fig. 6, the write speed is greater than the read speed (i.e., the angle between the solid line and the positive direction of the horizontal axis is smaller than the angle between the broken line and the positive direction of the horizontal axis). The two buffer areas independently complete read-write operation, and the first buffer area and the second buffer area can store data in a crossing mode or display data in a crossing mode.
If the last time the write (read) operation was performed in the first buffer, the write (read) operation is performed in the second buffer. For example, the first frame is read in the first buffer (i.e., read # 0), and the next frame is read in the second buffer (i.e., read # 1). The rest of the image frames and so on, as shown in particular in fig. 6.
The TE signal is output at the end of the frame of the display (dashed write waveform) with the result that each frame of the display generates a TE signal for requesting a new image frame to be written.
Further, the TE signal may be specifically an FU signal or a PU signal according to the integrity of the new image frame.
For example, after reading the 1 st frame (i.e. read # 0), since the written 2 nd frame is a (i.e. write # 2) complete frame, the output TE signal is the FU signal, i.e. the complete picture is displayed after the read second frame.
For another example, after reading the 2 nd frame (i.e., read # 1), the TE signal is output as the PU signal because the next frame written is a local frame. Namely: when the second buffer is in a state where reading of the 2 nd image frame is finished (or a state where reading is about to be finished) and the PU signal is transmitted, the 3 rd frame is displayed as "Picture-in-Picture (PiP)" in the display screen. The picture-in-picture technology is to arrange the auxiliary picture in the main picture, and use a mode of overlapping two video pictures, namely a large picture and a small picture, to simultaneously present two video signals. I.e., one or more compressed sub-pictures are simultaneously inserted on a normally viewed main picture, so that other channels are monitored while enjoying the main picture.
As can be seen from fig. 6, the read speed is slower because the write speed is greater than the read speed. At this time, after 1 reading operation is performed on one buffer area, a first signal is generated to request a new image frame, so that the image can be written in as soon as possible, the display quality is ensured, and the tearing phenomenon is avoided.
In example two, as shown in fig. 7, fig. 7 is a schematic diagram of another read-write process for a buffer according to an embodiment of the present application, where a solid line represents a read waveform for the buffer, and a dotted line represents a write waveform for the buffer.
It can be seen that in the read-write process shown in fig. 7, the write speed is smaller than the read speed (i.e., the angle between the solid line and the positive direction of the horizontal axis is larger than the angle between the broken line and the positive direction of the horizontal axis). The two buffer areas independently complete read-write operation, and the first buffer area and the second buffer area can store data in a crossing mode or display data in a crossing mode.
If the last time the write (read) operation was performed in the first buffer, the write (read) operation is performed in the second buffer. For example, the first frame is read in the first buffer (i.e., read # 0), and the next frame is read in the second buffer (i.e., read # 1).
The TE signal is output at the end of the frame of the display (dashed write waveform) with the result that each frame of the display generates a TE signal for requesting a new image frame to be written.
Further, the TE signal may be specifically an FU signal or a PU signal according to the integrity of the new image frame.
For example, after reading frame 1 (i.e. read # 0), since frame 2 is written (i.e. write # 2) as a complete frame, the output TE signal is the FU signal, i.e. the complete picture is displayed after reading the second frame.
For another example, after reading the 2 nd frame (i.e., read # 1), the TE signal is output as the PU signal because the next frame written is a local frame. Namely: when the second buffer is in a state where reading of the 2 nd image frame is finished (or a state where reading is about to be finished) and the PU signal is transmitted, the 3 rd frame is displayed as "Picture-in-Picture (PiP)" in the display screen. The picture-in-picture technology is to arrange the auxiliary picture in the main picture, and use a mode of overlapping two video pictures, namely a large picture and a small picture, to simultaneously present two video signals. I.e., one or more compressed sub-pictures are simultaneously inserted on a normally viewed main picture, so that other channels are monitored while enjoying the main picture.
As shown in fig. 7, it can be seen that since the read speed is greater than the write speed, the read speed is faster. At this time, after 2 times of reading operation are performed on a buffer area, a first signal is generated to request a new image frame, so that the speed of image reading can adapt to the speed of image writing, and therefore the possibility of tearing phenomenon can be reduced.
In the embodiment of the application, after the display controller receives the TE signal, the frame start instruction of the command mode of the image is sent, and the data is basically of fixed delay, and the delays of different display controllers may be different. The frame rate at which the TE signal is generated is based on the display refresh frequency. The LCDC starts to be refreshed continuously and uninterruptedly according to a fixed frame rate after starting to display, and the next frame starts to be started after the last frame is ended, so that the input speed of the same display controller is fixed and cannot be changed dynamically.
In the embodiment of the application, the possibility of tearing phenomenon can be reduced by alternately writing a plurality of image frames through a plurality of buffer areas. For example, if there are two buffers (which are called a first buffer and a second buffer for convenience of distinction), if a write (read) operation is performed in the first buffer last time, a write (read) operation is performed in the second buffer at this time, so when a read operation is performed in one buffer, a write operation can be performed in the other buffer, so that the read operation can be performed after the write operation is completed, thereby avoiding a tearing phenomenon and improving the smoothness of image display.
In addition, the method can also adjust the number of times of reading operation on one buffer zone according to the writing speed and the reading speed. For example, when the writing speed is faster than the reading speed, N may be 1, and after 1 reading operation is performed on one buffer area, a first signal is generated to request a new image frame, so that the image can be written as soon as possible, the display quality is ensured, and no tearing phenomenon occurs; for example, when the reading speed is faster than the writing speed, N may be 2 (or greater), and at this time, after 2 times of reading operations are performed on one buffer, a first signal is generated to request a new image frame, so that the image reading speed can adapt to the image writing speed, and thus the possibility of tearing phenomenon can be reduced, and since the image frame of the reading operation is complete, it is ensured that the image quality of the displayed image is not greatly lost.
The foregoing details the method of embodiments of the present application and the apparatus of embodiments of the present application are provided below.
It will be understood that, in order to implement the functions in the above method embodiments, the multiple devices provided in the embodiments of the present application, for example, a display control device, include a hardware structure, a software module, or a combination of a hardware structure and a software structure that perform respective functions.
Those of skill in the art will readily appreciate that the elements and algorithm steps of the examples described in connection with the embodiments disclosed herein may be implemented as hardware or combinations of hardware and computer software. Whether a function is implemented as hardware or computer software driven hardware depends upon the particular application and design constraints imposed on the solution. The skilled person may implement the foregoing method embodiments in different usage scenarios using different device implementations, which should not be considered to be beyond the scope of the embodiments of the present application.
The embodiment of the application can divide the functional modules of the device. For example, each functional module may be divided corresponding to each function, or two or more functions may be integrated in one functional module. The integrated modules may be implemented in hardware or in software functional modules. It should be noted that, in the embodiment of the present application, the division of the modules is schematic, which is merely a logic function division, and other division manners may be implemented in actual implementation.
For example, in the case of dividing the individual functional modules of the device in an integrated manner, the present application exemplifies several possible processing devices.
Referring to fig. 8, fig. 8 is a schematic structural diagram of a display control device 80 according to an embodiment of the present application, where the display control device 80 may be a server or a user device, or may be a device in the server or the user device, such as a chip, a software module, an integrated circuit, etc. The apparatus 80 is used to implement the display control method described above, such as the display control method of the embodiment shown in fig. 5.
In one possible embodiment, the display control apparatus 80 may include an input unit 801, a processing unit 802, and an output unit 803. The device is used for realizing the display control method, for example, the display control method of the embodiment shown in fig. 5. It should be understood that the division of the plurality of modules shown in fig. 8 is only one logical division according to functions, and is not a limitation of a specific structure of the probe apparatus. In a specific implementation, part of the modules may be subdivided into more tiny functional modules, and part of the functional modules may be combined into one functional module. For example, the processing unit may be subdivided into a writing unit and a reading unit.
In a possible implementation manner, the plurality of buffers are used for alternately and alternately writing the image frames;
the processing unit 802 is configured to write a first image frame to a first buffer, where the first buffer is any buffer of the plurality of buffers;
the processing unit 802 is configured to sequentially read the first image frames from the first buffer N times to display a first image;
the output unit 803 is configured to output a first signal, where the first signal is used to request a new image frame, N is an integer greater than 0, and N is related to a writing speed and a reading speed of the first image frame.
In the embodiment of the application, the possibility of tearing phenomenon can be reduced by alternately writing a plurality of image frames through a plurality of buffer areas.
For example, if there are two buffers (which are called a first buffer and a second buffer for convenience of distinction), if a write (read) operation is performed in the first buffer last time, a write (read) operation is performed in the second buffer at this time, so when a read operation is performed in one buffer, a write operation can be performed in the other buffer, so that the read operation can be performed after the write operation is completed, thereby avoiding a tearing phenomenon and improving the smoothness of image display.
In addition, the number of read operations to one buffer may be adjusted according to the writing speed and the reading speed. For example, when the writing speed is faster than the reading speed, N may be 1, and after 1 reading operation is performed on one buffer, a first signal is generated to request a new image frame, so that the image can be written as soon as possible, the display quality is ensured, and no tearing phenomenon occurs.
In another possible implementation manner, the processing unit is further configured to write a second image frame in the second buffer after the writing of the first image frame in the first buffer, where the second buffer belongs to the plurality of buffers;
the processing unit 802 is further configured to, after the N times of continuous reading of the first image frames, continuously read M times of the second image frames from the second buffer area to display a second image;
the output unit 803 is further configured to output a second signal, where the second signal is used to request a new image frame, and M is an integer greater than 0.
In the embodiment of the application, the possibility of tearing phenomenon can be reduced by alternately writing a plurality of image frames through a plurality of buffer areas.
For example, if there are two buffers (which are called a first buffer and a second buffer for convenience of distinction), if a write (read) operation is performed in the first buffer last time, a write (read) operation is performed in the second buffer at this time, so when a read operation is performed in one buffer, a write operation can be performed in the other buffer, so that the read operation can be performed after the write operation is completed, thereby avoiding a tearing phenomenon and improving the smoothness of image display.
In addition, the number of read operations to one buffer may be adjusted according to the writing speed and the reading speed. For example, when the writing speed is faster than the reading speed, M may be 1, and after 1 reading operation is performed on one buffer, a first signal is generated to request a new image frame, so that the image can be written as soon as possible, the display quality is ensured, and no tearing phenomenon occurs.
In yet another possible implementation, n=1 when the writing speed of the first image frame is greater than the reading speed of the first image frame.
In the embodiment of the application, the number of times of performing a read operation on one buffer area can also be adjusted according to the writing speed and the reading speed. For example, when the writing speed is faster than the reading speed, N may be 1, and after 1 reading operation is performed on one buffer, a first signal is generated to request a new image frame, so that the image can be written as soon as possible, the display quality is ensured, and no tearing phenomenon occurs.
In yet another possible implementation, N > 1 when the writing speed of the first image frame is less than the reading speed of the first image frame.
It will be appreciated that when the read speed is faster than the write speed, N may be 2 (or greater), and at this time, after 2 reads are performed on one buffer, a new image frame is requested by generating a first signal, so that the speed of image reading can adapt to the speed of image writing, and thus the possibility of tearing can be reduced, and since the image frame of the read operation is complete, it is ensured that the image quality of the displayed image is not greatly lost.
In yet another possible implementation, when the new image frame is a complete image frame, the first signal updates the FU signal for the complete frame;
when the new image frame is a local image frame, the first signal is a local frame update PU signal.
In yet another possible implementation, the input unit 801 is configured to receive a frame start command for a full image frame, where the frame start command is configured to instruct to start reading the image frame at the first frame rate to display an image.
For the embodiment of the application, after the display controller receives the TE signal, the frame start instruction of the command mode of the image is sent, the data is basically a fixed delay, and the delays of different display controllers may be different. The frame rate at which the TE signal is generated is based on the display refresh frequency. The LCDC starts to be refreshed continuously and uninterruptedly according to a fixed frame rate after starting to display, and the next frame starts to be started after the last frame is ended, so that the input speed of the same display controller is fixed and cannot be changed dynamically.
Referring to fig. 9, fig. 9 is a schematic structural diagram of a display control device 90 according to an embodiment of the present application, where the display control device 90 may be a stand-alone device (e.g. one or more of a server, a user device, etc.), or may be a component (e.g. a chip, a software module, a hardware module, etc.) inside the stand-alone device. The display control device 90 may include at least one processor 901. Optionally, at least one memory 903 may also be included. Further alternatively, the display control apparatus 90 may further include a communication interface 902. Still further optionally, a bus 904 may be included, wherein the processor 901, the communication interface 902, and the memory 903 are coupled by the bus 904.
The processor 901 is a module for performing arithmetic operation and/or logic operation, and may specifically be one or more of a central processing unit (Central Processing Unit, CPU), a picture processor (Graphics Processing Unit, GPU), a microprocessor (Microprocessor Unit, MPU), an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), a field programmable gate array (Field Programmable Gate Array, FPGA), a complex programmable logic device (Complex Programmable Logic Device, CPLD), a coprocessor (assisting the central processing unit to perform corresponding processing and application), a micro control unit (Microcontroller Unit, MCU), and other processing modules.
The communication interface 902 may be used to provide information input or output to the at least one processor. And/or the communication interface 902 may be configured to receive data sent from and/or send data to the outside, which may be a wired link interface including, for example, an ethernet cable, or may be a wireless link (Wi-Fi, bluetooth, universal wireless transmission, vehicle-mounted short-range communication technology, and other short-range wireless communication technologies, etc.) interface. Optionally, the communication interface 902 may also include a transmitter (e.g., radio frequency transmitter, antenna, etc.) or a receiver, etc. coupled to the interface.
The memory 903 is used to provide storage space in which data such as an operating system and computer programs can be stored. The Memory 903 may be one or more of a random access Memory (Random Access Memory, RAM), a Read-only Memory (ROM), an erasable programmable Read-only Memory (EPROM), or a portable Read-only Memory (Compact Disc Read-only Memory, CD-ROM), etc.
At least one processor 901 in the apparatus 90 is configured to perform the methods described above, such as the method described in the embodiment depicted in fig. 5.
Alternatively, the processor 901 may be a processor (for convenience of distinction, referred to as a dedicated processor) dedicated to performing the methods, or may be a processor that performs the methods by calling a computer program, for example, a general-purpose processor. In the alternative, the at least one processor may also include both special purpose and general purpose processors. Alternatively, in the case of a computing device comprising at least one processor 901, the above-described computer program may be present in the memory 903.
In one possible design, the display control device 90 may be a display controller in the foregoing embodiment.
In one possible implementation, at least one processor 901 in the computing device 90 is configured to execute call computer instructions to:
writing, by the display control device, a first image frame to a first buffer, the first buffer being any one of the plurality of buffers; continuously reading the first image frames from the first buffer N times by the display control apparatus to display a first image;
a first signal is output by the display control device, the first signal being for requesting a new image frame, N being an integer greater than 0 and N being related to a writing speed and a reading speed of the first image frame.
In the embodiment of the application, the possibility of tearing phenomenon can be reduced by alternately writing a plurality of image frames through a plurality of buffer areas. For example, if there are two buffers (which are called a first buffer and a second buffer for convenience of distinction), if a write (read) operation is performed in the first buffer last time, a write (read) operation is performed in the second buffer at this time, so when a read operation is performed in one buffer, a write operation can be performed in the other buffer, so that the read operation can be performed after the write operation is completed, thereby avoiding a tearing phenomenon and improving the smoothness of image display.
In addition, the number of times of performing a read operation to one buffer can be adjusted according to the writing speed and the reading speed. For example, when the writing speed is faster than the reading speed, N may be 1, and after 1 reading operation is performed on one buffer area, a first signal is generated to request a new image frame, so that the image can be written as soon as possible, the display quality is ensured, and no tearing phenomenon occurs; for example, when the reading speed is faster than the writing speed, N may be 2 (or greater), and at this time, after 2 times of reading operations are performed on one buffer, a first signal is generated to request a new image frame, so that the image reading speed can adapt to the image writing speed, and thus the possibility of tearing phenomenon can be reduced, and since the image frame of the reading operation is complete, it is ensured that the image quality of the displayed image is not greatly lost.
In a possible implementation manner, after the writing of the first image frame to the first buffer, writing a second image frame to the second buffer, wherein the second buffer belongs to the plurality of buffers;
after the N consecutive readings of the first image frame, M consecutive readings of the second image frame from the second buffer to display a second image;
And outputting a second signal through the display control device, wherein the second signal is used for requesting a new image frame, and M is an integer greater than 0.
Writing multiple image frames alternately across multiple buffers may reduce the likelihood of tearing. For example, if there are two buffers (which are called a first buffer and a second buffer for convenience of distinction), if a write (read) operation is performed in the first buffer last time, a write (read) operation is performed in the second buffer at this time, so when a read operation is performed in one buffer, a write operation can be performed in the other buffer, so that the read operation can be performed after the write operation is completed, thereby avoiding a tearing phenomenon and improving the smoothness of image display.
In yet another possible implementation, n=1 when the writing speed of the first image frame is greater than the reading speed of the first image frame.
In this embodiment of the present application, when the writing speed is faster than the reading speed, N may be 1, and after performing a reading operation on a buffer for 1 time, a first signal is generated to request a new image frame, so that an image may be written as soon as possible, and display quality is ensured without tearing phenomenon.
In yet another possible implementation, N > 1 when the writing speed of the first image frame is less than the reading speed of the first image frame.
In this embodiment of the present application, when the reading speed is faster than the writing speed, N may be 2 (or greater), and at this time, after 2 times of reading operations are performed on one buffer, a first signal is generated to request a new image frame, so that the speed of image reading can adapt to the speed of image writing, and thus the possibility of tearing phenomenon can be reduced, and since the image frame of the reading operation is complete, it is ensured that the image quality of the displayed image is not greatly lost.
In yet another possible implementation, when the new image frame is a complete image frame, the first signal updates the FU signal for the complete frame;
when the new image frame is a local image frame, the first signal is a local frame update PU signal.
In the embodiment of the present application, the TE signal may be an FU signal or a PU signal according to the integrity of the new image frame. For example, after reading the 1 st frame, since the written 2 nd frame is a complete frame, the output TE signal is the FU signal, i.e., the complete picture is displayed after the read second frame.
For another example, after reading the 2 nd frame, since the next frame written is a local frame, the TE signal outputted is a PU signal. Namely: when the second buffer is in a state where reading of the 2 nd image frame is finished (or a state where reading is about to be finished) and the PU signal is transmitted, the 3 rd frame is displayed as "Picture-in-Picture (PiP)" in the display screen. The picture-in-picture technology is to arrange the auxiliary picture in the main picture, and use a mode of overlapping two video pictures, namely a large picture and a small picture, to simultaneously present two video signals. I.e., one or more compressed sub-pictures are simultaneously inserted on a normally viewed main picture, so that other channels are monitored while enjoying the main picture.
In yet another possible embodiment, a frame start command for a full image frame is received by the display control device, the frame start command indicating that reading of the image frame is started at the first frame rate to display an image.
For the embodiment of the application, after the display controller receives the TE signal, the frame start instruction of the command mode of the image is sent, the data is basically a fixed delay, and the delays of different display controllers may be different. The frame rate at which the TE signal is generated is based on the display refresh frequency. The LCDC starts to be refreshed continuously and uninterruptedly according to a fixed frame rate after starting to display, and the next frame starts to be started after the last frame is ended, so that the input speed of the same display controller is fixed and cannot be changed dynamically.
The present application also provides a computer readable storage medium having instructions stored therein that when executed on at least one processor implement the aforementioned display control method, such as the method described in fig. 5.
The present application also provides a computer program product comprising computer instructions which, when executed by a computing device, implement the aforementioned display control method, such as the method described in fig. 5.
In the embodiments of the present application, words such as "exemplary" or "such as" are used to mean serving as examples, illustrations, or descriptions. Any embodiment or design described herein as "exemplary" or "for example" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.
Reference to "at least one" in embodiments herein means one or more, and "a plurality" means two or more. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b, or c may represent: a. b, c, (a and b), (a and c), (b and c), or (a and b and c), wherein a, b, c may be single or plural. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: three cases of a alone, a and B together, and B alone, wherein A, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship.
And, unless otherwise indicated, the use of ordinal numbers such as "first," "second," etc., in the embodiments herein are used for distinguishing between multiple objects and not for defining a sequence, timing, priority, or importance of the multiple objects. For example, the first device and the second device are for ease of description only and are not meant to be a representation of differences in the structure, importance, etc. of the first device and the second device, and in some embodiments, the first device and the second device may also be the same device.
As used in the above embodiments, the term "when … …" may be interpreted to mean "if … …" or "after … …" or "in response to determination … …" or "in response to detection … …" depending on the context. The foregoing description of the preferred embodiments is merely exemplary in nature and is in no way intended to limit the invention, its application, to the form and details of construction and the arrangement of the preferred embodiments, and thus, any and all modifications, equivalents, and alternatives falling within the spirit and principles of the present application.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program for instructing relevant hardware, where the program may be stored in a computer readable storage medium, and the storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
While the invention has been described with reference to certain preferred embodiments, it will be understood by those skilled in the art that various changes and substitutions of equivalents may be made and equivalents will be apparent to those skilled in the art without departing from the scope of the invention. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (7)

1. A display control method applied to a display control apparatus including a plurality of buffers for alternately interleaving a plurality of image frames, the method comprising:
writing a first image frame to a first buffer, the first buffer being any one of the plurality of buffers;
continuously reading the first image frames from the first buffer N times to display a first image;
outputting a first signal for requesting a new image frame, N being an integer greater than 0 and N being related to a writing speed and a reading speed of the first image frame;
writing a second image frame in a second buffer after said writing the first image frame to the first buffer, said second buffer belonging to said plurality of buffers;
After the N consecutive readings of the first image frame, M consecutive readings of the second image frame from the second buffer to display a second image;
outputting a second signal for requesting a new image frame, M being an integer greater than 0;
when the new image frame is a complete image frame, the first signal updates the FU signal for the complete frame;
when the new image frame is a local image frame, the first signal is a local frame update PU signal.
2. The method of claim 1, wherein N = 1 when the writing speed of the first image frame is greater than the reading speed of the first image frame.
3. The method of claim 1, wherein N > 1 when the writing speed of the first image frame is less than the reading speed of the first image frame.
4. A method according to any one of claims 1-3, wherein the method further comprises:
a frame start command for a full image frame is received, the frame start command being for instructing reading of the image frame to display an image at a first frame rate.
5. A display control apparatus, characterized in that the display control apparatus comprises a plurality of buffers, a processing unit, and an output unit, wherein:
The buffer areas are used for alternately and alternately writing the image frames;
the processing unit is configured to write a first image frame into a first buffer, where the first buffer is any buffer of the plurality of buffers;
the processing unit is used for continuously reading the first image frames from the first buffer area for N times so as to display a first image;
the output unit is used for outputting a first signal, wherein the first signal is used for requesting a new image frame, N is an integer greater than 0 and is related to the writing speed and the reading speed of the first image frame;
the processing unit is further configured to write a second image frame in a second buffer after the writing of the first image frame to the first buffer, where the second buffer belongs to the plurality of buffers;
the processing unit is further configured to continuously read M times the second image frames from the second buffer area after the N times of continuous reading of the first image frames, so as to display a second image;
the output unit is further configured to output a second signal, where the second signal is used to request a new image frame, and M is an integer greater than 0;
when the new image frame is a complete image frame, the first signal updates the FU signal for the complete frame;
When the new image frame is a local image frame, the first signal is a local frame update PU signal.
6. A display control device comprising a processor and a memory, the memory for storing computer instructions, the processor for invoking the computer instructions to implement the method of any of claims 1-4.
7. A computer readable storage medium having instructions stored therein which, when executed on at least one processor, implement the method of any one of claims 1-4.
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