CN114143931B - LED driving circuit - Google Patents
LED driving circuit Download PDFInfo
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- CN114143931B CN114143931B CN202111546574.5A CN202111546574A CN114143931B CN 114143931 B CN114143931 B CN 114143931B CN 202111546574 A CN202111546574 A CN 202111546574A CN 114143931 B CN114143931 B CN 114143931B
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Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
- H05B45/30—Driver circuits
- H05B45/32—Pulse-control circuits
- H05B45/325—Pulse-width modulation [PWM]
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
- H05B45/30—Driver circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
- H05B45/30—Driver circuits
- H05B45/345—Current stabilisation; Maintaining constant current
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
- H05B45/40—Details of LED load circuits
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
- Y02B20/40—Control techniques providing energy savings, e.g. smart controller or presence detection
Abstract
The present invention provides an LED driving circuit, comprising: the power switching tube comprises a power switching tube, a sampling resistor, a control module and a driving module, wherein the control module generates an effective sampling control signal when a first switching period of the power switching tube is ended and a second switching period is started, and generates effective switching period control signals in the first two periods of the power switching tube; the driving module is used for generating a driving signal, controlling the power switch tube to work for at least two switching periods, and generating an effective comparison trigger signal when the sampling voltage is larger than the compensation voltage. By the LED driving circuit, when PWM dimming is carried out, the stability of the circuit and the constant current characteristic of the LED are improved.
Description
Technical Field
The invention relates to the technical field of power electronics, in particular to an LED driving circuit.
Background
The LED is used as a light source, and is very suitable for being applied to occasions of dimming and toning. With the popularization and gradual popularization of intelligent illumination, consumers have higher requirements on dimming quality, so that higher requirements are put on the stability and reliability of an LED driving circuit required during dimming.
At present, a commonly used LED dimming mode is PWM dimming, and the working principle of the LED dimming mode is that a PWM signal is used for controlling an LED driving circuit, and LED current is regulated by regulating the duty ratio of the PWM signal. Many existing LED driving circuits with PWM dimming use an inductor current continuous mode, in which the PWM signal is maintained at a high level and the system is stabilized, the valley of the inductor current is greater than 0. When the PWM signal is in a low level and is maintained for a long time, the power switch tube is in an off state, and the inductance current in the circuit is reduced to 0; at this time, if the PWM signal changes from low level to high level, the power switching tube is turned on, and in the first switching period when the power switching tube starts to operate, the inductor current starts to rise from 0, so that the average value of the inductor current in the first switching period is smaller than the average value after the system is stabilized, if the system is stabilized, a plurality of switching periods need to be passed, and in the plurality of switching periods when the system is stabilized, the compensation voltage output in the circuit has oscillation problem, and further the stability of the system is deteriorated.
Therefore, when PWM dimming is performed, how to keep the compensation voltage output by the circuit stable, avoid the fluctuation of inductance current in the circuit, and improve the stability of the system is a technical problem which needs to be solved at present.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an objective of the present invention is to provide an LED driving circuit and method for solving the problem of inductor current fluctuation caused by compensation voltage oscillation and the problem of poor system stability in the PWM dimming circuit in the inductor current continuous mode in the prior art.
To achieve the above and other related objects, the present invention provides an LED driving circuit comprising: the power switch tube, the sampling resistor, the control module and the driving module,
the control end of the power switch tube receives a driving signal, the first connecting end receives current of the load LED end, and the second connecting end is grounded through a sampling resistor and generates sampling voltage;
the control module receives a PWM signal, a comparison trigger signal and the driving signal, and is used for generating an effective sampling control signal at the end of a first switching period and the beginning of a second switching period of the power switch tube based on the comparison trigger signal and the driving signal when the PWM signal is changed from low level to high level, and generating effective switching period control signals in the first two switching periods of the power switch tube;
the driving module is used for receiving the sampling control signal, the sampling voltage and the switching period control signal, generating a compensation voltage based on the sampling voltage when the sampling control signal is effective, generating the driving signal based on the compensation voltage, the sampling voltage and the switching period control signal, controlling the power switching tube to work for at least two switching periods, and generating an effective comparison trigger signal when the sampling voltage is greater than the compensation voltage.
Optionally, the control module includes a reset signal generating unit, a sampling control unit and a switching period control unit, where the reset signal generating unit is configured to generate a reset signal with a narrow pulse width when the PWM signal changes from a low level to a high level;
the sampling control unit receives the reset signal, the comparison trigger signal and the driving signal, is used for carrying out reset operation according to the reset signal, generates an effective pre-stage sampling control signal when the comparison trigger signal is effective, and generates an effective sampling control signal when a first switching period of the power switching tube is ended and a second switching period is started through carrying out logic operation on the pre-stage sampling control signal and the driving signal;
the switching period control unit receives the reset signal, the comparison trigger signal, the pre-stage sampling control signal and the PWM signal, and is used for generating an effective switching period control signal according to the reset signal and maintaining that the switching period control signal is effective in at least two first switching periods of the power switch tube according to the comparison trigger signal, the pre-stage sampling control signal and the PWM signal.
Optionally, the driving module includes a compensation voltage generating unit and a driving control unit, where the compensation voltage generating unit receives the sampling control signal and the sampling voltage, and is configured to perform error amplification on the sampling voltage and the reference voltage to generate a compensation voltage when the sampling control signal is valid;
the driving control unit receives the compensation voltage, the sampling voltage and the switching period control signal, is used for comparing the compensation voltage with the sampling voltage, generates a front-stage driving signal according to a comparison result, generates an effective comparison trigger signal when the sampling voltage is larger than the compensation voltage, and controls the power switching tube to work for at least two switching periods by carrying out logic operation on the front-stage driving signal and the switching period control signal to generate the driving signal.
Optionally, the reset signal generating unit includes a first resistor, a first capacitor, an inverter and a nand gate, where one end of the first resistor is connected to the PWM signal, the other end of the first resistor is connected to the input end of the inverter and grounded through the first capacitor, the output end of the inverter is connected to the first input end of the nand gate, the second input end of the nand gate is connected to the PWM signal, and the output end of the nand gate outputs the reset signal.
Optionally, the sampling control unit includes a first D flip-flop and a first and gate, where a reset end of the first D flip-flop is connected to the reset signal, a clock end of the first D flip-flop is connected to the comparison trigger signal, a data end of the first D flip-flop is connected to a high level, an in-phase output end of the first D flip-flop is connected to a first input end of the first and gate and outputs the preceding sampling control signal, a second input end of the first and gate is connected to the driving signal, and an output end of the first and gate outputs the sampling control signal.
Optionally, the switching period control unit includes a second D flip-flop and an or gate, where a reset end of the second D flip-flop is connected to the reset signal, a clock end of the second D flip-flop is connected to the comparison trigger signal, a data end of the second D flip-flop is connected to the pre-sampling control signal, an inverted output end of the second D flip-flop is connected to a first input end of the or gate, a second input end of the or gate is connected to the PWM signal, and an output end of the or gate outputs the switching period control signal.
Optionally, the compensation voltage generating unit includes a switch tube, a second resistor, a second capacitor and an error amplifier, where a gate of the switch tube is connected to the sampling control signal, a drain of the switch tube is connected to the sampling voltage, a source of the switch tube is connected to an inverting input end of the error amplifier through the second resistor, the inverting input end of the error amplifier is connected to an output end of the error amplifier through the second capacitor, a non-inverting input end of the error amplifier is connected to a reference voltage, and an output end of the error amplifier outputs the compensation voltage.
Optionally, the driving control unit includes a comparator, an RS trigger and a second and gate, where an inverting input end of the comparator is connected to the compensation voltage, an non-inverting input end of the comparator is connected to the sampling voltage, an output end of the comparator is connected to a reset end of the RS trigger and outputs the comparison trigger signal, a setting end of the RS trigger is connected to a clock signal, an non-inverting output end of the RS trigger is connected to a first input end of the second and gate, a second input end of the second and gate is connected to the switching period control signal, and an output end of the second and gate outputs the driving signal.
Optionally, the LED driving circuit further includes a load module, where the load module includes a diode, an LED, and an inductor, the anode of the LED is connected to a power supply voltage and connected to the cathode of the diode, the cathode of the LED is connected to the anode of the diode through the inductor, and the anode of the diode is further connected to the drain of the power switch tube.
Optionally, the LED driving circuit further includes a clock signal generating module for generating the clock signal.
As described above, the LED driving circuit and method of the present invention have the following advantages: the circuit has simple structure and easy realization, and the compensation voltage output by the error amplifier can be kept stable and unchanged when PWM dimming is carried out, so that inductance current fluctuation caused by oscillation of the compensation voltage is avoided, the stability of a system is improved, and the constant current characteristic of an LED is improved.
Drawings
Fig. 1 shows a conventional LED driving circuit diagram.
Fig. 2 shows a waveform diagram of a conventional LED driving circuit.
Fig. 3 shows a circuit diagram of an LED driving circuit of the present invention.
Fig. 4 is a waveform diagram of an LED driving circuit according to the present invention.
Fig. 5 is a waveform diagram showing the LED driving circuit of the present invention when a narrow pulse is input to the PWM signal.
Description of element reference numerals
21. Control module
211. Reset signal generating unit
212. Sampling control unit
213. Switching cycle control unit
22. Driving module
221. 11 Compensation Voltage generating Unit
222. 12 drive control unit
23. Clock signal generating module
24. Load module
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 1-5. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
Fig. 1 is an LED driving circuit with PWM dimming function, which includes a compensation voltage generating unit 11, a driving control unit 12, a power tube NM11 AND a sampling resistor Rcs, wherein the compensation voltage generating unit 11 includes an NMOS tube NM12, a resistor R11, a capacitor C11, an error amplifier EA AND a reference voltage Vref, AND the driving control unit 12 includes a comparator CMP, an RS trigger, AND an AND gate AND11.
Since the current through the LED is equal to the average value of the inductor current, the current flowing through the LED can be detected by detecting the average value of the inductor current in the circuit, and the average value can be maintained at a stable value by adjusting the compensation voltage generated in the circuit, thereby allowing the LED to output a constant current.
When the power tube NM11 is conducted in the LED driving circuit, a path is formed by the voltage Vin, the LED, the inductor L, the power tube NM11 and the sampling resistor Rcs, and inductive current is generated in the circuit; when the power tube NM11 is turned off, the LED, the inductor L, and the diode D11 form a path, and the inductor L discharges. The on AND off states of the power tube NM11 are controlled by a driving signal DRV output by the AND gate AND11, when the driving signal DRV output by the AND gate AND11 is at a high level, the power tube NM11 is conducted, the inductance current in the circuit is increased linearly, AND the inductance current flows through the sampling resistor Rcs to generate a sampling voltage Vcs; when the driving signal DRV output from the AND gate AND11 is at a low level, the power transistor NM11 is turned off, AND the sampling voltage Vcs drops to 0.
Since the gate of the NMOS transistor NM12 and the gate of the power transistor NM11 are both connected to the driving signal DRV, when the power transistor NM11 is turned off, the NMOS transistor N12 is turned off, and the compensation voltage generating unit 11 maintains the previous working state, so that the compensation voltage Vcomp output by the error amplifier EA remains unchanged; when both the power transistor NM11 and the NMOS transistor NM12 are turned on, the compensation voltage generating unit 11 starts to operate and generates the compensation voltage Vcomp, and at this time, if the sampling voltage Vcs is smaller than the reference voltage Vref, the output voltage Vcomp of the error amplifier EA increases; if the sampling voltage Vcs is greater than the reference voltage Vref, the output voltage Vcomp of the error amplifier is reduced; the output voltage Vcomp of the error amplifier EA remains substantially unchanged when the system reaches a steady state of operation.
In the on-state of the power transistor NM11, when the sampling voltage Vcs increases linearly to be higher than the compensation voltage Vcomp, the driving control unit 12 generates the driving signal DRV of a low level, so that the power transistor NM11 is turned off, and after the power transistor NM11 is turned off, the sampling voltage Vcs drops to 0, and the output signal of the comparator CMP becomes a low level.
The LED driving circuit further includes an oscillator OSC, where an output end of the oscillator is connected to a set end of the RS flip-flop, AND when the narrow pulse clock signal CLK changes from low level to high level, an output signal of the RS flip-flop changes from low level to high level, so that the driving signal DRV output by the AND gate AND11 changes from low level to high level, AND the power tube NM11 is turned on.
As can be seen from fig. 2, the operation mode of the LED driving circuit is an inductor current continuous mode, in which the PWM signal is maintained at a high level and the valley value of the inductor current is greater than 0 after the system is stabilized. Since the low level of the PWM signal is typically maintained for a longer period of time, the inductor current in the circuit can drop to 0 when the PWM signal is low. After the PWM signal changes from low level to high level, the power tube NM11 is turned on, and in the first switching period when the power tube NM11 starts to operate, the inductor current in the circuit starts to rise from 0, so that the average value of the inductor current in the first switching period is smaller than the average value after the system is stabilized, and the compensation voltage Vcomp output by the error amplifier EA increases in the first switching period of the power tube NM11, and therefore, from the second switching period of the power tube NM11, the compensation voltage generating unit 11 adjusts the compensation voltage Vcomp generated in the first switching period, so that the compensation voltage Vcomp gradually stabilizes after several oscillations.
Therefore, in the existing PWM dimming circuit, in several switching periods after the PWM signal is changed from low level to high level in the inductor current continuous mode, the compensation voltage output by the error amplifier has an oscillation problem, so that the inductor current in the circuit fluctuates, and the stability of the system is poor. Therefore, it is necessary to provide an LED driving circuit that avoids the inductor current fluctuation caused by the compensation voltage oscillation, thereby improving the stability of the system and improving the constant current characteristics of the LED.
As shown in fig. 3, according to the defect existing in the conventional LED driving circuit, the present embodiment proposes an LED driving circuit, which includes: power switching tube NM21, sampling resistor Rcs, control module 21 and driving module 22.
The control end of the power switch tube NM21 receives a driving signal DRV, the first connection end of the power switch tube NM21 receives an inductance current of the load LED end, and the second connection end of the power switch tube NM21 is grounded through the sampling resistor Rcs and generates a sampling voltage Vcs.
In this embodiment, the control end of the power switch tube NM21 receives a driving signal DRV, when the driving signal DRV is at a high level, the power switch tube NM21 is turned on, and the inductance current of the load LED end flows through the sampling resistor Rcs through the power switch tube NM21, so as to generate the sampling voltage Vcs; when the driving signal DRV is at a low level, the power switching transistor NM21 is turned off, the current passing through the sampling resistor Rcs is 0, and the sampling voltage Vcs drops to 0. Optionally, the power switch tube NM21 may include an NMOS tube or an NPN transistor, and in this embodiment, the power switch tube NM21 is an NMOS tube.
The control module 21 receives a PWM signal, a comparison trigger signal, and the driving signal, and is configured to generate an effective sampling control signal at the end of a first switching period and at the beginning of a second switching period of the power switching tube NM21 based on the comparison trigger signal and the driving signal when the PWM signal changes from a low level to a high level, and generate effective switching period control signals in the first two switching periods of the power switching tube NM 21.
Specifically, the control module 21 includes a reset signal generating unit 211, a sampling control unit 212, and a switching period control unit 213.
The Reset signal generating unit 211 is configured to generate a Reset signal Reset with a narrow pulse width when the PWM signal changes from a low level to a high level.
Specifically, the Reset signal generating unit 211 includes a first resistor R21, a first capacitor C21, an inverter INV21, and a NAND gate NAND21, where one end of the first resistor R21 is connected to the PWM signal, the other end of the first resistor R21 is connected to the input end of the inverter INV21 and grounded through the first capacitor C21, the output end of the inverter INV21 is connected to the first input end of the NAND gate NAND21, the second input end of the NAND gate NAND21 is connected to the PWM signal, and the output end of the NAND gate NAND21 outputs the Reset signal Reset.
In this embodiment, when the PWM signal changes from low level to high level, the PWM signal passes through a delay circuit formed by the first resistor R21 and the first capacitor C21, and then passes through the inverter INV21 and the nand gate ANAD21 to logically operate to output a Reset signal Reset with a narrow pulse width, where the Reset signal Reset is valid at low level, and the Reset signal Reset is high level in other periods when the PWM signal is at high level.
The sampling control unit 212 receives the Reset signal Reset, the comparison trigger signal and the driving signal DRV, and is configured to perform a Reset operation according to the Reset signal Reset, generate an effective pre-sampling control signal countA when the comparison trigger signal is effective, and generate an effective sampling control signal when a first switching cycle of the power switching tube ends and a second switching cycle begins by performing a logic operation on the pre-sampling control signal countA and the driving signal DRV.
Specifically, the sampling control unit 212 includes a first D flip-flop D21 AND a first AND gate AND21, where a Reset end of the first D flip-flop D21 is connected to the Reset signal Reset, a clock end of the first D flip-flop D21 is connected to the comparison trigger signal, a data end of the first D flip-flop D21 is connected to a high level "1", an in-phase output end of the first D flip-flop D21 is connected to a first input end of the first AND gate AND21 AND outputs the previous sampling control signal countA, a second input end of the first AND gate AND21 is connected to the driving signal DRV, AND an output end of the first AND gate outputs the sampling control signal.
In this embodiment, in the first switching period of the power switch tube NM21, the first D flip-flop D21 is connected to the Reset signal Reset to achieve zero clearing, and outputs the low-level pre-sampling control signal countA, where the sampling control signal countA and the driving signal DRV output a low-level sampling control signal through logical and operation. When the comparison trigger signal accessed by the first D flip-flop D21 is valid, that is, the comparison trigger signal changes from low level to high level, the pre-sampling control signal countA changes from low level to high level; starting from the second switching period of the power switching transistor NM21, the previous stage sampling control signal countA maintains a high level, AND the first AND gate AND21 generates an active sampling control signal.
The switching period control unit 213 receives the Reset signal Reset, the comparison trigger signal, the pre-sampling control signal countA, and the PWM signal, and is configured to generate an effective switching period control signal according to the Reset signal, and maintain that the switching period control signal is effective in at least two first switching periods of the power switching tube NM21 according to the comparison trigger signal, the pre-sampling control signal, and the PWM signal.
Specifically, the switching period control unit 213 includes a second D flip-flop D22 and an OR gate OR, where a Reset end of the second D flip-flop D22 is connected to the Reset signal Reset, a clock end of the second D flip-flop D22 is connected to the comparison trigger signal, a data end of the second D flip-flop D22 is connected to the pre-sampling control signal countA, an inverting output end of the second D flip-flop D22 is connected to a first input end of the OR gate OR21, a second input end of the OR gate OR21 is connected to the PWM signal, and an output end of the OR gate OR21 outputs a switching period control signal.
In this embodiment, in the first switching period of the power switch tube NM21, the second D flip-flop D22 is accessed to the Reset signal Reset to realize zero clearing, and outputs a high-level previous-stage switching period control signal countB. Since the previous stage sampling control signal countA accessed by the data terminal of the second D flip-flop D22 is at a low level, when the comparison trigger signal accessed by the second D flip-flop D22 is valid, the previous stage switching period control signal countB maintains at a high level; during the second switching period of the power switching transistor NM21, the pre-stage switching period control signal countB generated by the second D flip-flop D22 maintains a high level, and when the comparison trigger signal to which it is connected is valid, the pre-stage switching period control signal countB changes from a high level to a low level. Since the previous stage switching period control signal countB is at a high level in the first two periods of the power switching tube NM21, the switching period control signal is at a high level, so that it is ensured that the power switching tube NM21 can realize at least two switching periods.
Specifically, the driving module 22 includes a compensation voltage generating unit 221 and a driving control unit 222.
The compensation voltage generating unit 221 receives the sampling control signal and the sampling voltage Vcs, and is configured to perform error amplification on the sampling voltage Vcs and the reference voltage Vref to generate the compensation voltage Vcomp when the sampling control signal is active.
Specifically, the compensation voltage generating unit 221 includes a switching tube NM22, a second resistor R22, a second capacitor C22, and an error amplifier EA, where a gate of the switching tube NM22 is connected to the sampling control signal, a drain of the switching tube NM22 is connected to the sampling voltage Vcs, a source of the switching tube NM22 is connected to an inverting input terminal of the error amplifier EA through the second resistor R22, an inverting input terminal of the error amplifier EA is connected to an output terminal of the error amplifier EA through the second capacitor C22, a non-inverting input terminal of the error amplifier EA is connected to the reference voltage Vref, and an output terminal of the error amplifier EA outputs the compensation voltage Vcomp. Optionally, the switching tube NM22 includes, but is not limited to, an NMOS tube, and in this embodiment, the switching tube NM22 is an NMOS tube.
In this embodiment, when the sampling control signal is at a low level, the switching tube NM22 is in an off state, and the voltage across the second capacitor C22 is kept unchanged, so that the compensation voltage Vcomp at the output end of the error amplifier EA is kept unchanged; when the sampling control signal is at a high level, the switching tube NM22 is in a conducting state, and the sampling voltage Vcs and the reference voltage Vref are error amplified by the error amplifier EA to generate the compensation voltage Vcomp. Alternatively, any circuit or device capable of generating the reference voltage Vref is suitable for use in the present embodiment, which preferably employs a voltage source as the reference voltage Vref.
Specifically, the driving control unit 222 receives the compensation voltage Vcomp, the sampling voltage Vcs, and the switching period control signal, and is configured to compare the compensation voltage Vcomp with the sampling voltage Vcs, generate a pre-stage driving signal according to a comparison result, and generate an effective comparison trigger signal when the sampling voltage is greater than the compensation voltage, and perform a logic operation on the pre-stage driving signal and the switching period control signal to generate the driving signal DRV, so as to control the power switching transistor NM21 to operate for at least two switching periods.
Specifically, the driving control unit 222 includes a comparator CMP, an RS flip-flop, AND a second AND gate AND22, where an inverting input terminal of the comparator CMP is connected to the compensation voltage Vcomp, a non-inverting input terminal of the comparator CMP is connected to the sampling voltage Vcs, an output terminal of the comparator CMP is connected to a reset terminal of the RS flip-flop AND outputs the comparison trigger signal, a setting terminal of the RS flip-flop is connected to the clock signal CLK, a non-inverting output terminal of the RS flip-flop is connected to a first input terminal of the second AND gate AND22, a second input terminal of the second AND gate AND22 is connected to the switching period control signal, AND an output terminal of the second AND gate AND22 outputs the driving signal DRV.
In this embodiment, the comparator CMP compares the compensation voltage Vcomp with the sampling voltage Vcs and generates the comparison trigger signal, when the sampling voltage Vcs is lower than the compensation voltage Vcomp, the comparison trigger signal generated by the comparator CMP is at a low level, and the RS flip-flop outputs the pre-stage driving signal according to the received clock signal CLK and performs a logical and operation with the switching period control signal to generate the driving signal DRV; when the sampling voltage Vcs is higher than the compensation voltage Vcomp, the comparison trigger signal output by the comparator CMP changes from low level to high level, the RS flip-flop outputs the pre-stage driving signal of low level according to the received comparison trigger signal, and performs a logical and operation with the switching period control signal to generate the driving signal DRV of low level.
Specifically, the LED driving circuit further includes a clock signal generating module 23 configured to generate the clock signal CLK, where the clock signal CLK is a narrow pulse width signal, and when the clock signal CLK generated by the clock signal generating module 23 changes from a low level to a high level, the front driving signal output by the RS flip-flop is a high level, and the front driving signal and the switching period control signal output the driving signal DRV after logical and operation, so as to control the power switching tube NM21 to be turned on and off. Alternatively, the clock signal generating module 23 includes any circuit or device capable of generating the clock signal CLK, and in this embodiment, the clock signal generating module 23 is an oscillator.
Specifically, the LED driving circuit further includes a load module 24, where the load module 24 includes a diode D21, an LED, and an inductor L, the anode of the LED is connected to a power supply voltage and is connected to the cathode of the diode D21, the cathode of the LED is connected to the anode of the diode D21 through the inductor L, and the anode of the diode D21 is further connected to the drain of the power switch NM 21.
As shown in fig. 3 to 5, the working process of the LED driving circuit in this embodiment is as follows:
when the PWM signal changes from low level to high level, the Reset signal generating unit 211 generates a Reset signal Reset with a narrow pulse width, the switching period control unit 213 receives the Reset signal Reset to zero and outputs a high-level previous switching period control signal countB, and the previous switching period control signal countB maintains the high level in the first two switching periods of the power switching tube NM21, so that the power switching tube NM21 realizes at least 2 switching periods.
The power switch tube NM21 is in the first switch period:
the sampling control unit 212 receives the Reset signal Reset to generate a low-level previous-stage sampling control signal countA, so that the sampling control signal is low, and the switching tube NM22 is in an off state, the compensation voltage generating unit 221 does not operate, and the compensation voltage Vcomp at the output end thereof remains unchanged. The comparator CMP in the driving control unit 222 compares the connected compensation voltage Vcomp with the sampling voltage Vcs, and generates a valid comparison trigger signal when the sampling voltage Vcs is greater than the compensation voltage Vcomp, at this time, the driving control unit 222 generates a low-level driving signal DRV, so that the power switching transistor NM21 is turned off.
When the power switching tube NM21 is in the second switching period:
the sampling control unit 212 generates an effective sampling control signal, and the compensation voltage generating unit 221 receives the effective sampling control signal and starts to operate to generate the compensation voltage Vcomp, and the valley value and the peak value of the inductor current are consistent with the state when the system is stable in the second switching period of the power switching tube NM21, so that the compensation voltage Vcomp generated by the compensation voltage generating unit 221 is kept stable. The comparator CMP in the driving control unit 222 compares the connected compensation voltage Vcomp with the sampling voltage Vcs, and generates a valid comparison trigger signal when the sampling voltage Vcs is greater than the compensation voltage Vcomp, at this time, the driving control unit 222 generates a low-level driving signal DRV, so that the power switching transistor NM21 is turned off.
In the LED driving circuit according to the present embodiment, when PWM dimming is performed, the compensation voltage generating unit 221 does not operate in the first switching period of the power switching transistor NM21, but starts to operate from the second switching period, and generates the compensation voltage Vcomp. Moreover, in the first 2 switching periods when the PWM signal changes from low level to high level, the switching period control signal countB generated by the switching period control unit 213 is at high level, and in these 2 switching periods, even if the PWM signal changes to low level, the switching period control signal remains at high level, so that the power switching transistor NM21 realizes at least two switching periods, thereby achieving the purpose of accurately detecting the output current of the LED driving circuit, and maintaining the feedback loop in the circuit to work normally. After 2 switching cycles, the previous switching cycle control signal countB changes from high level to low level, and the on and off states of the power switching tube NM21 change with the potential of the PWM signal.
In summary, the circuit has a simple structure and is easy to realize, and when PWM dimming is performed, the output signal of the error amplifier can be kept stable and unchanged, so that the fluctuation of inductance current caused by the output oscillation of the error amplifier is avoided, the stability of the system is improved, and the constant current characteristic of the LED is improved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (10)
1. An LED driving circuit, comprising: the power switch tube, the sampling resistor, the control module and the driving module,
the control end of the power switch tube receives a driving signal, the first connecting end receives current of the load LED end, and the second connecting end is grounded through a sampling resistor and generates sampling voltage;
the control module receives a PWM signal, a comparison trigger signal and the driving signal, and is used for generating an effective sampling control signal at the end of a first switching period and the beginning of a second switching period of the power switch tube based on the comparison trigger signal and the driving signal when the PWM signal is changed from low level to high level, and generating effective switching period control signals in the first two switching periods of the power switch tube;
the driving module is used for receiving the sampling control signal, the sampling voltage and the switching period control signal, generating a compensation voltage based on the sampling voltage when the sampling control signal is effective, generating the driving signal based on the compensation voltage, the sampling voltage and the switching period control signal, controlling the power switching tube to work for at least two switching periods, and generating an effective comparison trigger signal when the sampling voltage is greater than the compensation voltage.
2. The LED driving circuit of claim 1, wherein the control module comprises a reset signal generating unit, a sampling control unit, and a switching period control unit, wherein,
the reset signal generating unit is used for generating a reset signal with narrow pulse width when the PWM signal is changed from low level to high level;
the sampling control unit receives the reset signal, the comparison trigger signal and the driving signal, is used for carrying out reset operation according to the reset signal, generates an effective pre-stage sampling control signal when the comparison trigger signal is effective, and generates an effective sampling control signal when a first switching period of the power switching tube is ended and a second switching period is started through carrying out logic operation on the pre-stage sampling control signal and the driving signal;
the switching period control unit receives the reset signal, the comparison trigger signal, the pre-stage sampling control signal and the PWM signal, and is used for generating an effective switching period control signal according to the reset signal and maintaining that the switching period control signal is effective in at least two first switching periods of the power switch tube according to the comparison trigger signal, the pre-stage sampling control signal and the PWM signal.
3. The LED driving circuit of claim 1, wherein the driving module comprises a compensation voltage generating unit and a driving control unit, wherein,
the compensation voltage generation unit receives the sampling control signal and the sampling voltage and is used for carrying out error amplification on the sampling voltage and the reference voltage to generate a compensation voltage when the sampling control signal is effective;
the driving control unit receives the compensation voltage, the sampling voltage and the switching period control signal, is used for comparing the compensation voltage with the sampling voltage, generates a front-stage driving signal according to a comparison result, generates an effective comparison trigger signal when the sampling voltage is larger than the compensation voltage, and controls the power switching tube to work for at least two switching periods by carrying out logic operation on the front-stage driving signal and the switching period control signal to generate the driving signal.
4. The LED driving circuit of claim 2, wherein the reset signal generating unit comprises a first resistor, a first capacitor, an inverter and a nand gate, wherein one end of the first resistor is connected to the PWM signal, the other end of the first resistor is connected to the input end of the inverter and grounded through the first capacitor, the output end of the inverter is connected to the first input end of the nand gate, the second input end of the nand gate is connected to the PWM signal, and the output end of the nand gate outputs the reset signal.
5. The LED driving circuit of claim 2, wherein the sampling control unit comprises a first D flip-flop and a first and gate, wherein a reset terminal of the first D flip-flop is connected to the reset signal, a clock terminal of the first D flip-flop is connected to the comparison trigger signal, a data terminal of the first D flip-flop is connected to a high level, an in-phase output terminal of the first D flip-flop is connected to a first input terminal of the first and gate and outputs the preceding sampling control signal, a second input terminal of the first and gate is connected to the driving signal, and an output terminal of the first and gate outputs the sampling control signal.
6. The LED driving circuit of claim 2, wherein the switching period control unit comprises a second D flip-flop and an or gate, a reset terminal of the second D flip-flop is connected to the reset signal, a clock terminal of the second D flip-flop is connected to the comparison trigger signal, a data terminal of the second D flip-flop is connected to the pre-stage sampling control signal, an inverting output terminal of the second D flip-flop is connected to a first input terminal of the or gate, a second input terminal of the or gate is connected to the PWM signal, and an output terminal of the or gate outputs the switching period control signal.
7. The LED driving circuit of claim 3, wherein the compensation voltage generating unit comprises a switching tube, a second resistor, a second capacitor and an error amplifier, wherein the gate of the switching tube is connected to the sampling control signal, the drain of the switching tube is connected to the sampling voltage, the source of the switching tube is connected to the inverting input terminal of the error amplifier through the second resistor, the inverting input terminal of the error amplifier is connected to the output terminal of the error amplifier through the second capacitor, the non-inverting input terminal of the error amplifier is connected to the reference voltage, and the output terminal of the error amplifier outputs the compensation voltage.
8. The LED driving circuit of claim 3, wherein the driving control unit comprises a comparator, an RS flip-flop, and a second and gate, wherein an inverting input terminal of the comparator is connected to the compensation voltage, a non-inverting input terminal of the comparator is connected to the sampling voltage, an output terminal of the comparator is connected to a reset terminal of the RS flip-flop and outputs the comparison trigger signal, a set terminal of the RS flip-flop is connected to a clock signal, a non-inverting output terminal of the RS flip-flop is connected to a first input terminal of the second and gate, a second input terminal of the second and gate is connected to the switching period control signal, and an output terminal of the second and gate outputs the driving signal.
9. The LED driving circuit of claim 1, further comprising a load module, wherein the load module comprises a diode, an LED, and an inductor, wherein the anode of the LED is connected to a power supply voltage and to the cathode of the diode, wherein the cathode of the LED is connected to the anode of the diode through the inductor, and wherein the anode of the diode is further connected to the drain of the power switch.
10. The LED driving circuit of claim 1, further comprising a clock signal generation module for generating the clock signal.
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