CN114142872A - LDPC decoding apparatus and method thereof, and low-orbit satellite receiving device - Google Patents

LDPC decoding apparatus and method thereof, and low-orbit satellite receiving device Download PDF

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CN114142872A
CN114142872A CN202111477740.0A CN202111477740A CN114142872A CN 114142872 A CN114142872 A CN 114142872A CN 202111477740 A CN202111477740 A CN 202111477740A CN 114142872 A CN114142872 A CN 114142872A
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soft information
ldpc
decoder
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CN114142872B (en
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朱凯
汪永明
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Shanghai Yuanxin Satellite Technology Co ltd
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    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105Decoding
    • H03M13/1108Hard decision decoding, e.g. bit flipping, modified or weighted bit flipping
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105Decoding
    • H03M13/1128Judging correct decoding and iterative stopping criteria other than syndrome check and upper limit for decoding iterations
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B7/00Radio transmission systems, i.e. using radiation field
    • H04B7/14Relay systems
    • H04B7/15Active relay systems
    • H04B7/185Space-based or airborne stations; Stations for satellite systems
    • H04B7/1851Systems using a satellite or space-based relay
    • H04B7/18517Transmission equipment in earth stations

Abstract

The disclosure relates to the field of satellite communication, and discloses an LDPC decoding device and a method thereof, and low-orbit satellite receiving equipment, which improve LDPC decoding to realize enhanced physical layer error correction performance. The decoding apparatus includes: the system comprises a convolutional decoder and an LDPC decoder which are coupled with each other, wherein the convolutional decoder is configured to perform convolutional decoding according to received channel soft information or second external soft information from the LDPC decoder to obtain first external soft information and output the first external soft information to the LDPC decoder; the LDPC decoder is configured to perform LDPC decoding according to first external soft information output by the convolutional decoder to obtain second external soft information, output the second external soft information to the convolutional decoder for iterative decoding when a preset iteration end condition is not met, and output the second external soft information as third external soft information when the iteration end condition is met.

Description

LDPC decoding apparatus and method thereof, and low-orbit satellite receiving device
Technical Field
The present disclosure relates to the field of satellite communications, and more particularly to LDPC decoding techniques.
Background
This section is intended to provide a background or context to the embodiments of the disclosure recited in the claims. The description herein is not admitted to be prior art by inclusion in this section.
Non-geostationary orbit (NGSO) satellites or Low Earth Orbit (LEO) satellites are currently one direction of development for hot spot communications. The greatest difference between satellite communication systems and the most advanced terrestrial networks (e.g., 5G NR) is that the Satellite Base Stations (SBS) are usually located in the earth's orbit at an orbital height of 600-.
As shown in fig. 1a, the NGSO Satellite operates in orbit at a speed of about 7.5km/s, is connected with a Satellite Gateway station (Satellite Gateway) by a Feeder link, and is connected with a user terminal on the ground by an Access/service link to provide a communication service for the user terminal. The user terminal may be any terminal having a wired or wireless communication function, including, but not limited to, a Satellite terminal (Satellite terminal), a cell phone, a computer, a personal digital assistant, a game console, a wearable device, an in-vehicle communication device, a Machine Type Communication (MTC) device, a device-to-device (D2D) communication device, and a sensor, etc. A user terminal may also be referred to as a UE, a mobile station, a subscriber station, a mobile terminal, a terminal device, a wireless device, or the like.
A simplified schematic diagram of the processing performed at the transmitting device 120 and the receiving device 130 of the wireless communication system is shown in fig. 1 b. A satellite, satellite gateway station, or user terminal on the ground in fig. 1a may serve as the transmitting device 120 and/or the receiving device 130.
As shown in fig. 1b, to ensure reliable transfer of data (including control signaling), the transmitting device channel encodes (140) the data to be transmitted to introduce redundancy against distortion that may be introduced in the transmission channel (e.g., the link between the satellite and the terrestrial user terminal). In addition, the channel-coded data may be further channel interleaved (150) before being transmitted to rearrange the coded bits prior to transmission so that successive bits in the data are scattered. The interleaved data may then be modulated (160). At the receiving device, the reverse process is performed as for the transmitting device, i.e., the received signal is demodulated (170), deinterleaved (180), and decoded (190) to recover the transmitted data.
The propagation time of the electromagnetic waves between the terrestrial user terminal and the SBS is provided in table 1. It is clear that the propagation delay of a satellite communication system is much higher than that of a terrestrial communication system. Longer propagation distances introduce additional delay with concomitant degradation in delay jitter, resulting in a degraded user experience.
TABLE 1 platform height and one-way propagation delay
Platform Typical height Propagation delay
LEO satellite 600km ~12.9ms
GSO satellite 35 786km ~270ms
In this case, the satellite communication system relies more on forward error control techniques, since conventional backward error control, e.g., retransmission schemes with/without explicit ACK/NACK feedback, will result in intolerable additional delays. Thus, modern satellite communication standards, such as DVB S2, provide a technique for a quasi-error free physical layer (PHY).
In recent years, terrestrial network operators have foreseen a tremendous opportunity to replace optical fiber and cable with LEO satellite networks to enable relay and backhaul transport. How to provide the quality of service similar to optical fiber has become an important technical problem to be solved in the design of low-earth orbit satellite systems.
The DVB standard specifies physical layer technology characteristics at the transmitter end where advanced forward error control (combining BCH and LDPC codes) is used. The principle is to correct most random errors using strong LDPC and the remaining errors are corrected by BCH. Therefore, it is apparent that the physical layer performance is mainly determined by the decoding algorithm of the LDPC.
Therefore, the problem that embodiments of the present disclosure need to solve can be summarized as how to improve LDPC decoding to enhance physical layer error correction performance.
Disclosure of Invention
An object of the present disclosure is to provide an LDPC decoding apparatus and method thereof, a low orbit satellite receiving device, which improve LDPC decoding to achieve enhanced physical layer error correction performance.
The present disclosure discloses an LDPC decoding apparatus, comprising: a convolutional decoder and an LDPC decoder coupled to each other, wherein,
the convolutional decoder is configured to perform convolutional decoding according to the received channel soft information or second external soft information from the LDPC decoder to obtain first external soft information, and output the first external soft information to the LDPC decoder;
the LDPC decoder is configured to perform LDPC decoding according to the first external soft information output by the convolutional decoder to obtain second external soft information, output the second external soft information to the convolutional decoder for iterative decoding when a preset iteration end condition is not met, and output the second external soft information as third external soft information when the iteration end condition is met.
In a preferred embodiment, the apparatus is used for decoding LDPC signals conforming to the digital video broadcasting S2 or S2X standard.
In a preferred embodiment, the LDPC decoder is configured to output the third extrinsic soft information to a hard decision device for the hard decision device to output decoded bits.
In a preferred embodiment, the channel soft information is from a soft demodulator.
In a preferred embodiment, the iteration end condition includes that the number of iterations reaches a preset threshold and/or the decoding index reaches a preset threshold.
In a preferred embodiment, the LDPC decoder further comprises an interleaver and an deinterleaver which are configured between the convolutional decoder and the LDPC decoder;
the interleaving and de-interleaving unit is configured to de-interleave the first extrinsic soft information from the convolutional decoder and output the first extrinsic soft information to the LDPC decoder, and interleave the second extrinsic soft information from the LDPC decoder and output the second extrinsic soft information to the convolutional decoder.
In a preferred example, the channel soft information includes log-likelihood ratios or probabilities, and the external soft information includes log-likelihood ratios or probabilities.
The present disclosure also discloses an LDPC decoding method, comprising:
receiving channel soft information by a convolutional decoder;
the convolutional decoder performs convolutional decoding according to the channel soft information and outputs the obtained first external soft information to the LDPC decoder;
the LDPC decoder performs LDPC decoding according to the first external soft information output by the convolutional decoder to obtain second external soft information;
if the LDPC decoder determines that the preset iteration ending condition is not met, the second external soft information is output to the convolutional decoder for iterative decoding;
and if the LDPC decoder determines that a preset iteration end condition is met, outputting the second external soft information as third external soft information.
In a preferred embodiment, the method is used for decoding LDPC signals conforming to the digital video broadcasting S2 or S2X standard.
In a preferred embodiment, the method further includes the step of making a hard decision by the hard decision device according to third external soft information output by the LDPC decoder to obtain decoded bits.
In a preferred embodiment, the outputting the obtained first extrinsic soft information to the LDPC decoder further includes:
the interleaving and de-interleaving device is used for de-interleaving the first external soft information from the convolutional decoder and outputting the de-interleaved first external soft information to the LDPC decoder;
said outputting said second extrinsic soft information to said convolutional decoder for iterative decoding further comprises:
and the interleaving and de-interleaving device interleaves the second external soft information from the LDPC decoder and outputs the interleaved second external soft information to the convolutional decoder.
In a preferred embodiment, the external soft information comprises an external log-likelihood ratio or probability identified in the linear domain;
the external soft information includes information from a soft demodulator.
The present disclosure also discloses a low orbit satellite receiving device, including:
the soft demodulator is configured to perform soft demodulation on a signal from a transmitting end to obtain channel soft information;
the LDPC decoding apparatus as described above, configured to receive the channel soft information output by the soft demodulator and output third external soft information;
a hard decision device configured to perform a hard decision on the third external soft information to obtain decoded bits.
The present disclosure also discloses a non-transitory machine-readable medium having computer instructions, which when executed by a hardware processor, cause the hardware processor to perform operations in a method as previously described.
In the embodiment of the disclosure, the LDPC decoding method has better error correction capability for the LDPC decoding of DVB S2/S2X standard, and the error rate of the obtained decoding result is lower, so that the method is particularly suitable for low-orbit satellite communication.
The respective technical features disclosed in the above summary, the respective technical features disclosed in the following embodiments and examples, and the respective technical features disclosed in the drawings can be freely combined with each other to constitute various new technical solutions (which should be regarded as having been described in the present specification) unless such a combination of the technical features is technically impossible. For example, in one example, the feature a + B + C is disclosed, in another example, the feature a + B + D + E is disclosed, and the features C and D are equivalent technical means for the same purpose, and technically only one feature is used, but not simultaneously employed, and the feature E can be technically combined with the feature C, then the solution of a + B + C + D should not be considered as being described because the technology is not feasible, and the solution of a + B + C + E should be considered as being described.
Drawings
The objects, advantages and other features of the present invention will become more fully apparent from the following disclosure and appended claims. A non-limiting description of the preferred embodiments is given herein, by way of example only, with reference to the accompanying drawings, in which:
figure 1a shows a schematic diagram of NGSO satellite communications;
FIG. 1b shows a simplified schematic diagram of processing performed at a transmitting device and a receiving device of a wireless communication system;
FIG. 2 illustrates a schematic structural diagram of an LDPC decoding apparatus according to an embodiment of the present disclosure;
FIG. 3 shows a schematic structural diagram of an LDPC decoding apparatus according to an embodiment of the present disclosure;
FIG. 4 shows a flow diagram of an LDPC decoding method according to an embodiment of the present disclosure;
FIG. 5 shows a schematic structural diagram of a low-orbit satellite receiving device according to one embodiment of the present disclosure;
fig. 6 illustrates a block diagram of a communication device suitable for implementing some embodiments of the present disclosure.
Detailed Description
In the following description, numerous technical details are set forth in order to provide a better understanding of the present disclosure. However, it will be understood by those of ordinary skill in the art that the claimed embodiments of the present disclosure may be practiced without these specific details and with various changes and modifications based on the following embodiments.
Description of the partial abbreviations:
DVB (digital video broadcasting): digital Video Broadcasting, Digital Video Broadcasting.
BCH: Bose-Chaudhuri-Hocquenghem code, Bose-Chaudhuri-Hocquenghem.
NGSO: Non-GeoStationary Orbit, Non-GeoStationary Orbit.
GSO: GeoStationary Orbit, GeoStationary Orbit.
LDPC: low Density Parity Check Code, Low Density Parity Check Code.
LEO: low Earth Orbit, Low Earth Orbit.
LNA: low Noise Amplifier, Low-Noise Amplifier.
LLR: Log-Likelihood Ratio, Log-likeliohood Ratio.
NR: the New wireless air interface, New Radio, refers to a 5G wireless air interface technology.
RAN: radio Access Network, Radio Access Network.
FEC: forward Error Control, Forward Error Control.
PDU: protocol Data Unit, Protocol Data Unit.
PHY: physical Layer, Physical Layer.
The following outlines some of the innovative points of the embodiments of the present disclosure:
as is well known in the art, decoding of LDPC is of course a direct use of LDPC decoders. However, the inventor of the present disclosure finds that, for an LDPC encoder conforming to DVB S2/S2X standard, the LDPC encoder can be equivalently decomposed into a combination of an irregular LDPC encoder and a convolutional encoder, and according to this inventive discovery, an LDPC decoder conforming to DVB S2/S2X standard can be equivalently implemented by a combination of a convolutional decoder and an LDPC decoder, which has a better error correction capability and a lower error rate of decoding results than a conventional implementation directly using an LDPC encoder, and is particularly suitable for low-orbit satellite communication.
To make the objects, technical solutions and advantages of the present disclosure more apparent, embodiments of the present disclosure will be described in further detail below with reference to the accompanying drawings.
A first embodiment of the present disclosure relates to an LDPC decoding apparatus having a structure as shown in fig. 2, the apparatus including: a convolutional decoder and an LDPC decoder coupled to each other, wherein,
the convolution decoder is configured to perform convolution decoding according to the received channel soft information or second external soft information from the LDPC decoder to obtain first external soft information, and output the first external soft information to the LDPC decoder. The convolutional decoding may use a soft decoding method such as Viterbi, max-a-posteriori, etc.
The LDPC decoder is configured to perform LDPC decoding according to first external soft information output by the convolutional decoder to obtain second external soft information, output the second external soft information to the convolutional decoder for iterative decoding when a preset iteration end condition is not met, and output the second external soft information as third external soft information when the iteration end condition is met. In one embodiment, the first extrinsic soft information is forwarded as an a priori to an LDPC decoder that initializes the LDPC variable nodes and computes a second extrinsic LLR/probability using various existing iterative LDPC decoding algorithms, e.g., sum-product, min-sum, etc.
In one embodiment, there are two levels of iteration in the decoding apparatus: the first layer is a plurality of internal iterations inside the LDPC decoder so as to carry out LDPC decoding according to the first external soft information to obtain second external soft information; the second layer is a plurality of external iterations between the LDPC encoder and the convolutional decoder so as to continuously optimize the obtained second external soft information, and the final second external soft information is output to the hard decision device as third external soft information when the iteration is finished. In one embodiment, the number of internal iterations within the LDPC adder may be different for each external iteration between the LDPC adder and the convolutional decoder.
In some special cases, the LDPC decoder may satisfy the iteration end condition after first solving the second external soft information, and at this time, the second external soft information may be directly output as the third external soft information without performing external iteration between the LDPC encoder and the convolutional decoder.
Optionally, in one embodiment, the apparatus is used to decode LDPC signals that conform to the DVB S2 or S2X standards. Optionally, in other embodiments, the apparatus may also be used to decode LDPC signals like the DVB S2 or S2X standards.
Optionally, in an embodiment, the LDPC decoder outputs the third external soft information to the hard decision device, for the hard decision device to output the decoded bits.
Optionally, in one embodiment, the channel soft information is from a soft demodulator. The soft demodulator receives as input a complex baseband signal, the corresponding output of the demodulation being channel soft information. There may be time and frequency synchronization operations prior to demodulation, and the complex baseband signal may be filtered and amplified by a Low Noise Amplifier (LNA) before entering the demodulator. The synchronization operations, filtering and amplification etc. are prior art and will not be described in detail here.
Optionally, in an embodiment, the iteration end condition includes that the number of iterations reaches a preset threshold and/or the decoding index reaches a preset threshold.
Optionally, in an embodiment, the apparatus further includes an interleaver and an deinterleaver disposed between the convolutional decoder and the LDPC decoder. The interleaving and de-interleaving unit is configured to de-interleave the first extrinsic soft information from the convolutional decoder and output the first extrinsic soft information to the LDPC decoder, and interleave the second extrinsic soft information from the LDPC decoder and output the second extrinsic soft information to the convolutional decoder. As shown in fig. 3, the interleaver and deinterleaver include an interleaver and an deinterleaver corresponding to each other.
Alternatively, in one embodiment, the channel soft information may be log-likelihood ratio LLRs or probabilities, and the external soft information may be log-likelihood ratio LLRs or probabilities.
Optionally, in one embodiment, the LDPC decoding algorithm used by the LDPC decoder may be enhanced.
One enhancement is various additional post-processing of log-likelihood ratios (LLRs) used in the well-known min-sum algorithm, which can lead to a number of variations.
Specifically, assuming that a ═ ln (a) and B ═ ln (B) are LLRs, the 'min-sum' algorithm described above performs the following approximation in the logarithmic domain:
Figure BDA0003394135880000091
where sign (X) represents the sign or polarity of X, min (X, Y) represents the minimum between X and Y, | X | represents the magnitude of X, exp is an exponential function based on a natural constant e, ln is a natural logarithmic function, and the g term can be expressed as
g=ln(1+exp(-|A+B|))-ln(1+exp(-|A-B|)) (2)
In implementation, since the g term is difficult to calculate by using a circuit, formula 1 usually ignores the operation content of the g term to perform certain simplification, and such simplification inevitably incurs performance loss. Therefore, compensating for the error between the approximation and the true value of equation 1, i.e., the term g in equation 2, is a common way to recover some of the performance loss.
Variant 1: the magnitude of f in equation 1 is calculated using equation 3, and the polarity of f is determined by the product of all incoming LLR symbols.
Figure BDA0003394135880000101
Variant 2: equation 1 is approximated as equation 4, with the additional correction factor C being greater than or equal to 0. This method is equivalent to introducing a fixed offset to the approximate calculation of equation 1. The optimum value of C may be set empirically.
f≈sign(A)sign(B)max(min(|A|,|B|)-C,0) (4)
Variant 3: equation 1 is approximated as equation 5, where the correction coefficient C is a constant greater than 1, which is equivalent to scaling down the result of the approximation of equation 1. The optimum value of C may be set empirically.
f≈sign(A)sign(B)min(|A|,|B|)/C (5)
The second enhancement focuses on the scheduling of LDPC decoding, specifically the scheduling of soft information exchange order when performing variable node updates and check node updates, which forms a class of LDPC decoding schemes using "layered decoding".
A second embodiment of the present disclosure relates to an LDPC decoding method, a flow of which is shown in fig. 4, the method including:
in step 301, a convolutional decoder receives channel soft information.
Then, step 302 is entered, and the convolutional decoder performs convolutional decoding according to the channel soft information and outputs the obtained first external soft information to the LDPC decoder.
Then, step 303 is entered, and the LDPC decoder performs LDPC decoding according to the first external soft information output by the convolutional decoder to obtain second external soft information.
Then, the process proceeds to step 304, where the LDPC decoder determines whether a preset iteration ending condition is satisfied, and if so, the process proceeds to step 305, where the LDPC decoder outputs the second external soft information to the convolutional decoder for iterative decoding, and returns to step 302, otherwise, the LDPC decoder proceeds to step 305.
In step 305, the LDPC decoder determines that a predetermined iteration end condition is satisfied, and outputs the second extrinsic soft information as third extrinsic soft information.
Optionally, in one embodiment, the method is used for decoding LDPC signals that conform to the digital video broadcast S2 or S2X standards.
Optionally, in an embodiment, after step 306, the method further includes: and the hard decision device carries out hard decision according to the third external soft information output by the LDPC decoder to obtain decoded bits.
Optionally, in an embodiment, the outputting the obtained first external soft information to the LDPC decoder in step 301 further includes:
the interleaving and de-interleaving device de-interleaves the first external soft information from the convolutional decoder, and outputs the de-interleaved first external soft information to the LDPC decoder.
In step 305, outputting the second extrinsic soft information to the convolutional decoder for iterative decoding further comprises:
the interleaving and de-interleaving unit interleaves the second external soft information from the LDPC decoder and outputs the interleaved second external soft information to the convolutional decoder.
Optionally, in one embodiment, the external soft information includes an external log-likelihood ratio or probability identified in the linear domain. The external soft information includes information from the soft demodulator.
This embodiment is a method embodiment corresponding to the first embodiment, and the technical details in the first embodiment may be applied to this embodiment, and the technical details in this embodiment may also be applied to the first embodiment.
A third embodiment of the present disclosure relates to a low-orbit satellite receiving apparatus, including:
and the soft demodulator is configured to perform soft demodulation on the signal from the transmitting end to obtain channel soft information.
The LDPC decoding apparatus according to the first embodiment is configured to receive the channel soft information output by the soft demodulator and output third external soft information.
And the hard decision device is configured to perform hard decision on the third external soft information to obtain decoded bits.
Fig. 6 illustrates a block diagram of a communication device 1700 suitable for implementing embodiments of the present disclosure. Device 1700 may be used to implement a transmitting device or a receiving device in embodiments of the present disclosure, such as the low-orbit satellite receiving device shown in fig. 6.
As shown in the example in fig. 6, the device 1700 includes a processor 1710. Processor 1710 controls the operation and function of device 1700. For example, in certain embodiments, the processor 1710 may perform various operations by way of instructions 1730 stored in the memory 1720 coupled thereto. The memory 1720 may be of any suitable type suitable to the local technical environment and may be implemented using any suitable data storage technology, including but not limited to semiconductor-based memory devices, magnetic memory devices and systems, optical memory devices and systems. Although only one memory unit is shown in FIG. 6, there may be multiple physically distinct memory units within device 1700.
The processors 1710 may be of any suitable type suitable to the local technical environment and may include, but are not limited to, general purpose computers, special purpose computers, microcontrollers, digital signal controllers (DSPs), and one or more cores in a controller-based multi-core controller architecture. The device 1700 may also include multiple processors 1710. The processor 1710 may also be coupled with a transceiver 1740, which transceiver 1740 may enable receiving and transmitting information via one or more antennas 1750 and/or other components.
The processor 1710 and the memory 1720 may operate cooperatively to implement the methods described above according to embodiments of the present disclosure. It will be understood that all of the features described above apply to the device 1700 and are not described in detail herein.
It should be noted that, as will be understood by those skilled in the art, the functions of the modules shown in the above embodiments of the LDPC decoding apparatus may be implemented by a program (executable instructions) running on a processor, and may also be implemented by a specific logic circuit. In the embodiment of the present disclosure, the LDPC decoding apparatus may be stored in a computer-readable storage medium if it is implemented in the form of a software functional module and sold or used as an independent product. Based on such understanding, the technical solutions of the embodiments of the present disclosure may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the methods described in the embodiments of the present disclosure. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read Only Memory (ROM), a magnetic disk, or an optical disk. Thus, embodiments of the present disclosure are not limited to any specific combination of hardware and software.
Accordingly, embodiments of the present disclosure also provide a computer-readable storage medium having stored therein computer-executable instructions that, when executed by a processor, implement the method embodiments of the present disclosure. Computer-readable storage media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), Digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, a computer readable storage medium does not include a transitory computer readable medium such as a modulated data signal and a carrier wave.
In addition, embodiments of the present disclosure also provide an LDPC decoding apparatus, which includes a memory for storing computer-executable instructions, and a processor; the processor is configured to implement the steps of the method embodiments described above when executing the computer-executable instructions in the memory. The Processor may be a Central Processing Unit (CPU), other general-purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), or the like. The aforementioned memory may be a read-only memory (ROM), a Random Access Memory (RAM), a Flash memory (Flash), a hard disk, or a solid state disk. The steps of the method disclosed in the embodiments of the present invention may be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules in the processor.
By way of example, embodiments of the disclosure may also be described in the context of machine-executable instructions, such as those included in program modules, being executed in devices on target real or virtual processors. Generally, program modules include routines, programs, libraries, objects, classes, components, data structures, etc. that perform particular tasks or implement particular abstract data types. In various embodiments, the functionality of the program modules may be combined or divided between program modules as described. Machine-executable instructions for program modules may be executed within local or distributed devices. In a distributed facility, program modules may be located in both local and remote memory storage media.
Computer program code for implementing the methods of the present disclosure may be written in one or more programming languages. These computer program codes may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the program codes, when executed by the computer or other programmable data processing apparatus, cause the functions/acts specified in the flowchart and/or block diagram block or blocks to be performed. The program code may execute entirely on the computer, partly on the computer, as a stand-alone software package, partly on the computer and partly on a remote computer or entirely on the remote computer or server.
It is noted that, in the present disclosure, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the use of the verb "comprise a" to define an element does not exclude the presence of another, same element in a process, method, article, or apparatus that comprises the element. In the present disclosure, if it is mentioned that a certain action is performed according to a certain element, it means that the action is performed at least according to the element, and two cases are included: performing the action based only on the element, and performing the action based on the element and other elements. The expression of a plurality of, a plurality of and the like includes 2, 2 and more than 2, more than 2 and more than 2.
The sequence numbers used in describing the steps of the method do not in themselves constitute any limitation on the order of the steps. For example, the step with the larger sequence number is not necessarily executed after the step with the smaller sequence number, and the step with the larger sequence number may be executed first and then the step with the smaller sequence number may be executed in parallel, as long as the execution sequence is reasonable for those skilled in the art. As another example, the plurality of steps (e.g., step 301, step 302, step 303, etc.) having consecutive numbered sequence numbers do not limit other steps that may be performed therebetween, e.g., there may be other steps between step 301 and step 302.
This specification includes combinations of the various embodiments described herein. Separate references to embodiments (e.g., "one embodiment" or "some embodiments" or "a preferred embodiment"); however, these embodiments are not mutually exclusive, unless indicated as mutually exclusive or as would be apparent to one of ordinary skill in the art. It should be noted that the term "or" is used in this specification in a non-exclusive sense unless the context clearly dictates otherwise.
All documents mentioned in this specification are to be considered as being integrally included in the disclosure of the present disclosure so as to be able to be a basis for modification as necessary. It should be understood that the above description is only a preferred embodiment of the present disclosure, and is not intended to limit the scope of the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of one or more embodiments of the present disclosure should be included in the scope of protection of one or more embodiments of the present disclosure.
In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may also be possible or may be advantageous.

Claims (14)

1. An LDPC decoding apparatus, comprising: a convolutional decoder and an LDPC decoder coupled to each other, wherein,
the convolutional decoder is configured to perform convolutional decoding according to the received channel soft information or second external soft information from the LDPC decoder to obtain first external soft information, and output the first external soft information to the LDPC decoder;
the LDPC decoder is configured to perform LDPC decoding according to the first external soft information output by the convolutional decoder to obtain second external soft information, output the second external soft information to the convolutional decoder for iterative decoding when a preset iteration end condition is not met, and output the second external soft information as third external soft information when the iteration end condition is met.
2. The LDPC decoding apparatus of claim 1, wherein the apparatus is configured to decode an LDPC signal compliant with a digital video broadcast S2 or S2X standard.
3. The LDPC decoding apparatus of claim 1 wherein the LDPC decoder is configured to output the third extrinsic soft information to a hard decision for the hard decision to output decoded bits.
4. The LDPC decoding apparatus of claim 1 wherein the channel soft information is from a soft demodulator.
5. The LDPC decoding apparatus of claim 1, wherein the iteration end condition includes a number of iterations reaching a preset threshold and/or a decoding index reaching a preset threshold.
6. The LDPC decoding apparatus of claim 1, further comprising an interleaver and an deinterleaver disposed between the convolutional decoder and the LDPC decoder;
the interleaving and de-interleaving unit is configured to de-interleave the first extrinsic soft information from the convolutional decoder and output the first extrinsic soft information to the LDPC decoder, and interleave the second extrinsic soft information from the LDPC decoder and output the second extrinsic soft information to the convolutional decoder.
7. The LDPC decoding apparatus of any one of claims 1-6, wherein the channel soft information comprises log-likelihood ratios or probabilities and the external soft information comprises log-likelihood ratios or probabilities.
8. An LDPC decoding method, comprising:
receiving channel soft information by a convolutional decoder;
the convolutional decoder performs convolutional decoding according to the channel soft information and outputs the obtained first external soft information to the LDPC decoder;
the LDPC decoder performs LDPC decoding according to the first external soft information output by the convolutional decoder to obtain second external soft information;
if the LDPC decoder determines that the preset iteration ending condition is not met, the second external soft information is output to the convolutional decoder for iterative decoding;
and if the LDPC decoder determines that a preset iteration end condition is met, outputting the second external soft information as third external soft information.
9. The LDPC decoding method of claim 8, wherein the method is used to decode an LDPC signal compliant with a digital video broadcast S2 or S2X standard.
10. The LDPC decoding method of claim 8 further comprising a hard decision unit for making a hard decision based on third extrinsic soft information output from the LDPC decoder to obtain decoded bits.
11. The LDPC decoding method of claim 8, wherein the outputting the resulting first extrinsic soft information to the LDPC decoder further comprises:
the interleaving and de-interleaving device is used for de-interleaving the first external soft information from the convolutional decoder and outputting the de-interleaved first external soft information to the LDPC decoder;
said outputting said second extrinsic soft information to said convolutional decoder for iterative decoding further comprises:
and the interleaving and de-interleaving device interleaves the second external soft information from the LDPC decoder and outputs the interleaved second external soft information to the convolutional decoder.
12. The LDPC decoding method of claim 8 wherein the extrinsic soft information comprises an extrinsic log-likelihood ratio or probability identified in a linear domain;
the external soft information includes information from a soft demodulator.
13. A low-orbit satellite receiving apparatus, comprising:
the soft demodulator is configured to perform soft demodulation on a signal from a transmitting end to obtain channel soft information;
the LDPC decoding apparatus of any one of claims 1 to 7 configured to receive channel soft information output by the soft demodulator and to output third external soft information;
a hard decision device configured to perform a hard decision on the third external soft information to obtain decoded bits.
14. A non-transitory machine-readable medium having computer instructions, which when executed by a hardware processor, cause the hardware processor to perform operations in a method as recited in any one of claims 8 to 12.
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