CN114142870A - Decoding method and device of LDPC (Low Density parity check) code, storage medium and SSD (solid State disk) equipment - Google Patents
Decoding method and device of LDPC (Low Density parity check) code, storage medium and SSD (solid State disk) equipment Download PDFInfo
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- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
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- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
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Abstract
The invention provides a decoding method, a device, a storage medium and SSD equipment of LDPC codes, wherein the method comprises the following steps: updating the confidence information of the variable nodes in the current check layer of the check matrix by adopting a row-layer minimum sum algorithm; judging corresponding bits according to the updated confidence information; comparing whether the results of the current check layer before and after the iteration judgment are the same; if the results before and after the current iteration judgment of the current check layer are different, updating the check result corresponding to the bit with the changed judgment result by adopting the judgment result of the current iteration process; judging whether the check results of all bits pass; and stopping iterative verification if the verification results of all the bits pass. The invention can improve the check reliability, and simultaneously identify the iteration suspension condition in time, reduce the calculated amount and improve the decoding performance.
Description
Technical Field
The present invention relates to the field of encoding and decoding technologies, and in particular, to a decoding method and apparatus for an LDPC code, a storage medium, and an SSD device.
Background
The LDPC (Low Density Parity Check Code) has good comprehensive performance in several key indexes of error correction capability, decoding throughput and algorithm complexity, and is widely applied to mobile and fixed network standards after 2000 years, and is also a mainstream error correction Code of the current solid-state storage controller. LDPC codes may be defined by a check matrix. For each parity check matrix H, there is a corresponding Tanner (bipartitle Tanner graph). The Tanner graph includes two kinds of nodes, VN (variable node) and CN (check node). Each VN represents a column in H, and each CN represents a row in H; when the element in a row and a column in H is 1, VN and CN in the Tanner graph are connected by a "side". Fig. 1 is a diagram illustrating a mapping relationship from the parity check matrix H to the corresponding Tanner graph.
Currently, most decoding algorithms used by LDPC decoders are various algorithms derived from min-sum algorithms. For example: the normalized min-sum algorithm and the row-layered min-sum algorithm. The LDPC decoding generally comprises the following procedures that firstly, a decoder receives channel data and initializes the channel data; and updating check nodes, judging, checking node information, finishing decoding if the check equation is satisfied, updating bit nodes and correcting errors if the check equation is not satisfied and the maximum iteration number is not reached, and starting the next iteration. And when the check equation is still satisfied after the iteration times are large, the decoding fails. In most cases, the decoder does not run to the upper limit of the maximum number of iterations to successfully decode. For example, to reduce the number of iterations, reduce power consumption, and increase throughput, a decoder usually needs to identify whether the current decoding is successful, and then stops the iteration in advance.
In the prior art, the methods for terminating the early iteration are generally as follows:
a) standard algorithms: in each iteration, let the hard decision result of sum _ llr after t-layer decoding be
After the check nodes, variable nodes and decision values are updated in all layers, the values are obtained
Determine whether it satisfies the check formula
If yes, the check is correct. Because the iterative process of the row-layered min-sum algorithm is completely carried out, the method is the safest oneThe termination condition of (1). But two negative effects occur: a cannot identify whether successful decoding occurs in advance in one iteration process. When the original data contains few errors, a complete iteration is usually not used, and all errors can be corrected by only a few layers of operations. Having to wait until the iteration is complete to perform the check will undoubtedly greatly increase the number of clock cycles that the decoder runs. The b-check operation has considerable computation amount and needs a plurality of clock cycles. Concentrating it between iterations reduces the data throughput rate of the decoder.
b) One layer of verification:
let Mb denote the number of layers of the check matrix, HtIs a sub-matrix of the check matrix H, where t is 1 … Mb. The hard decision result of the LLR value after the t-th layer decoding is set as
After each layer of check node update, variable node update and decision value, hard decision is carried out on the decoded LLR value to obtain
Checking the result value stIs composed of
If satisfy stIf 0, the check of this layer passes.
Let theta be the number of layers passing the check, for theta ≧ 1, for some t, if satisfied
st＝st+1＝…＝st+θ-1＝0
Then successive theta layers check through and the iteration terminates. The larger θ, the more secure the policy. One layer (θ ═ 1) has a high check risk, and error floor (error floor) is easy to occur. The multi-layer check is safe, but has larger time delay and the upper reliability limit is only equal to that of the standard algorithm. It is not suitable for environments requiring extremely high reliability, such as in storage systems.
c) And (4) multi-layer verification:
taking two layers as an example, let the check matrix H submatrix of two-layer check be Ht,t+1＝[Ht,Ht+1],t＝1…Mb. Let the two-layer check result value be st,t+1＝[st,st+1]After the variable node is updated and the variable node is judged, two-layer check is performed once every time the check node of one layer is updated. Hard decision result of LLR value after t layer decoding
When multiplied by the check matrix, except for calculating the check result s of the current layertBesides, the next layer of check result s is calculated in advancet+1I.e. by
If satisfy st,t+1If 0, the check of this layer passes.
For theta ≧ 1, for some t, if satisfied
st,t+1＝st+1,t+2＝…＝st+θ-1,t+θ＝0
Then successive theta layers check through and the iteration terminates. The same layer checks similarly, the larger θ, the more secure the policy. The complexity of this algorithm is several times that of one layer of check, but the upper reliability limit is only equal to that of the standard algorithm.
d)sign stability(SS)：
SS is a limitation of adding symbols on the basis of a one-layer check principle, and besides checking the current layer, the SS also needs to make a hard decision result of LLR (LLR) values decoded by the previous layer
And the hard decision result of the LLR value after the current layer decoding
Comparing to determine whether they are equal, i.e. satisfy
t*Is the last layer of the last iteration and k is the number of iterations. When the current layer of the verification is the first layer of the first iteration, the hard decision result values of the two layers are not compared, and only s is satisfiedtWhen the current layer check is 0, the current layer check is passed; when the current layer of the verification is the first layer and is not the first iteration, formula (11) and s are satisfied simultaneouslytWhen the current layer check is 0, the current layer check is passed; when the verified current layer is not the first layer, both equations (12) and s are satisfiedtWhen 0, the current layer check passes.
And for theta to be more than or equal to 1, and for some t, if the continuous theta layer check is passed, the iteration is terminated.
After the first-layer check is improved, the misjudgment rate is lower and the safety is higher in a high signal-to-noise ratio area. But symbol decision requires extra space to store the compared symbol information. In addition, its upper reliability limit is only equal to the standard algorithm.
Fig. 2 shows the comparison of decoding simulation of schemes a to d, where the abscissa is the signal-to-noise ratio of the sequence input to the decoder, it can be seen that one layer has the worst reliability of check, and its code-free flat layer is the highest, and several other methods have FER (frame error rate) in the high signal-to-noise ratio region inferior to scheme a.
In addition, there is another scheme e, specifically, after each iteration process is finished, if the current hard decision result does not satisfy the check equation, the check node reliability value is calculated, if the relative error between the reliability value and the reliability value of the last iteration process is smaller than a certain threshold value, the count value of the stop counter is increased by 1, otherwise, the value of the stop counter returns to zero, if the value of the stop counter is larger than a certain threshold value, the iteration process is stopped, the current hard decision result is output as the decoding result of the decoder, otherwise, the next iteration process is started. The judgment cycle of the method is one iteration, only confidence judgment is added, the reliability is slightly better than that of the method a, but the calculated amount is larger.
In summary, the existing method is difficult to balance reliability, computation amount and timeliness of stopping iteration. In the methods a and e, complete check operation is performed only after each iteration is finished, the termination condition cannot be identified in time in the iteration process, and the operation period of the decoder is increased by performing the check operation in a centralized manner. Although the abort condition can be identified in the iterative process, the check result is not reliable because only a small part of the check matrix is used for checking, even if various remedial measures are adopted, the risk still exists, and the finally introduced check operation amount is not necessarily smaller than that of the method a.
Disclosure of Invention
In view of the above problems, the present invention has been made to provide a decoding method, apparatus, storage medium, and SSD device of LDPC codes that overcome or at least partially solve the above problems.
In one aspect of the present invention, a method for decoding an LDPC code is provided, the method including:
updating the confidence information of the variable nodes in the current check layer of the check matrix by adopting a row-layer minimum sum algorithm;
judging corresponding bits according to the updated confidence information;
comparing whether the results of the current check layer before and after the iteration judgment are the same;
if the results before and after the current iteration judgment of the current check layer are different, updating the check result corresponding to the bit with the changed judgment result by adopting the judgment result of the current iteration process;
judging whether the check results of all bits pass;
and stopping iterative verification if the verification results of all the bits pass.
Further, the method further comprises:
if the results of the current check layer before and after the current iteration judgment are the same or bits which do not pass the detection exist, judging whether the maximum iteration times or the maximum operation layer number is reached;
and if the maximum iteration times or the maximum operation layer number is not reached, continuously adopting the row-layering minimum sum algorithm to carry out iterative verification on the next verification layer of the verification matrix, and otherwise, stopping the iterative verification.
Further, after deciding the corresponding bit according to the updated confidence information, the method further includes:
and storing the judgment result of the current iteration process of the current check layer in a preset storage position.
Further, the method further comprises:
after the confidence information of all variable nodes in the current check layer is updated, performing the operation of judging corresponding bits according to the updated confidence information and comparing whether the results before and after the current iteration judgment of the current check layer are the same; or
In the process of updating the confidence information of the variable nodes in the current check layer, the updated partial confidence information is synchronously and parallelly executed to judge corresponding bits according to the updated confidence information, and whether the judgment of partial judgment results obtained by the current iteration of the current check layer is the same or not is compared.
Further, the method further comprises:
and updating the confidence information of the variable nodes by adopting a pipeline technology, judging corresponding bits according to the updated confidence information, and comparing whether the judgment results of partial judgment results obtained by the current iteration of the current check layer are the same before and after the judgment.
Further, the updating the check result corresponding to the bit with the changed decision result by using the decision result of the current iteration process includes:
if the historical check result corresponding to the bit with the changed judgment result is 0, updating the historical check result to 1;
and if the historical check result corresponding to the bit with the changed judgment result is 1, updating the historical check result to be 0.
In a second aspect of the present invention, there is provided an apparatus for decoding an LDPC code, the apparatus comprising:
the calculation module is used for updating the confidence information of the variable nodes in the current check layer of the check matrix by adopting a row-layer minimum sum algorithm;
the judgment module is used for judging the corresponding bit according to the updated confidence coefficient information;
the comparison module is used for comparing whether the results of the current check layer before and after the iteration judgment are the same;
the execution module is used for updating the verification result corresponding to the bit with the changed judgment result by adopting the judgment result of the iteration process if the results before and after the iteration judgment of the current verification layer are different;
the judging module is used for judging whether the check results of all bits pass;
and the execution module is further used for stopping iterative verification if the verification results of all the bits pass.
Further, the judging module is further configured to judge whether the maximum iteration number or the maximum number of calculation layers is reached when results before and after the current iteration decision of the current check layer are the same or bits which fail to be checked exist;
and the execution module is further used for continuously adopting the row-layering minimum sum algorithm to carry out iterative verification on the next verification layer of the verification matrix if the maximum iteration times or the maximum operation layer number is not reached, and otherwise, stopping the iterative verification.
In another aspect of the present invention, there is provided a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the decoding method of the LDPC code as above.
In still another aspect of the present invention, there is also provided an SSD device comprising a storage controller including a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps of the decoding method of the LDPC code as above when executing the computer program.
The decoding method, the decoding device, the storage medium and the SSD for the LDPC code provided by the embodiment of the invention only need to change the check result related to the variable node with the changed judgment result after each layer of operation, judge whether the updated check result passes the check, and stop the iterative check if the check result of all bits passes.
The foregoing description is only an overview of the technical solutions of the present invention, and the embodiments of the present invention are described below in order to make the technical means of the present invention more clearly understood and to make the above and other objects, features, and advantages of the present invention more clearly understandable.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
fig. 1 is a schematic diagram of a mapping relationship from a parity check matrix H to a corresponding Tanner graph;
FIG. 2 is a diagram illustrating a comparison of results of an early iteration termination algorithm in a conventional LDPC decoding method;
FIG. 3 is a flowchart of a decoding method of an LDPC code according to an embodiment of the present invention;
FIG. 4 is a flowchart of a decoding method of an LDPC code according to another embodiment of the present invention;
FIG. 5 is a graph comparing the throughput of a decoder using both the early termination methods of the present invention and the prior art;
fig. 6 is a block diagram of a decoding apparatus for LDPC codes according to the present invention.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Fig. 3 schematically shows a flowchart of a decoding method of an LDPC code according to an embodiment of the present invention. Referring to fig. 3, the decoding method of the LDPC code according to the embodiment of the present invention specifically includes the following steps:
s11, updating confidence information of the variable nodes in the current check layer of the check matrix by adopting a row-layered minimum sum algorithm;
and S12, judging the corresponding bit according to the updated confidence coefficient information. Specifically, after the confidence information of the relevant bits is updated, whether the corresponding bit is 1 or 0 is determined according to the confidence information.
S13, comparing whether the results before and after the current iteration judgment of the current check layer are the same;
if the results before and after the current iteration judgment of the current check layer are different, executing a step S14, otherwise executing a step S16;
s14, updating the check result corresponding to the bit with the changed judgment result by adopting the judgment result of the iteration process;
s15, judging whether the check results of all bits pass;
if the check result of all bits passes, performing step S18, and if there is a bit that fails the check, performing step S16;
s16, judging whether the maximum iteration number or the maximum calculation layer number is reached, if not, executing a step S17, otherwise, executing a step S18;
and S17, performing iterative check on the next check layer of the check matrix by adopting a row-layered minimum sum algorithm.
And S18, stopping iterative verification.
The decoding method of the LDPC code provided by the embodiment of the invention only needs to change the check result related to the variable node with the changed judgment result after each layer of operation, judges whether the updated check result passes the check, and stops the iterative check if the check result of all bits passes the check.
The decoding method of the LDPC code provided by the invention can provide an early termination method which is equal to a standard algorithm in reliability and can identify termination conditions in an iteration process. The invention uses the whole check matrix during checking, so that the reliability of the check result is not damaged. In addition, the invention only changes the check result related to the variable node with the changed judgment result after each layer of operation, and the check operation amount is far lower than that of the prior method.
In the embodiment of the invention, for each bit with different judgment results before and after the operation of the current layer, the latest judgment result is used for updating and calculating the check result participated by the bits, namely the check result corresponding to the bit with the changed judgment result is updated by adopting the judgment result of the iteration process. An optional implementation method is that if the historical check result corresponding to the bit with the changed decision result is 0, the historical check result is updated to 1; and if the historical check result corresponding to the bit with the changed judgment result is 1, updating the historical check result to be 0.
In this embodiment of the present invention, after deciding the corresponding bit according to the updated confidence information, the method further includes: and storing the judgment result of the current iteration process of the current check layer in a preset storage position.
In the process of implementing the invention, a group of memories is needed to be added to store the bit judgment result of the current layer, and a group of comparison circuits is also needed to be added to compare whether the results before and after the current iteration judgment of the current check layer are the same.
In the embodiment of the invention, after the confidence information of all variable nodes in the current check layer is updated, the corresponding bit is judged according to the updated confidence information, and the operation of comparing whether the results before and after the current iteration judgment of the current check layer are the same is executed.
In another embodiment of the present invention, the decision and comparison process may also be started after updating part of the decision information. In the process of updating the confidence information of the variable nodes in the current check layer, the updated partial confidence information is synchronously and parallelly executed to judge corresponding bits according to the updated confidence information, and whether the judgment results of partial judgment results obtained by the current iteration of the current check layer are the same or not is compared.
Fig. 4 schematically shows a flowchart of a decoding method of an LDPC code of an embodiment of the present invention. Referring to fig. 4, the decoding method of the LDPC code according to the embodiment of the present invention specifically includes the following steps:
s21, updating confidence information of partial variable nodes in the current check layer of the check matrix by adopting a row-layered minimum sum algorithm;
s22, judging the corresponding bit according to the updated confidence information;
s33, comparing whether the judgment result obtained by the current iteration of the current check layer is the same before and after judgment;
if the judgment of the partial judgment result obtained by the current iteration of the current check layer is different, executing a step S24, otherwise executing a step S26;
s24, updating the check result corresponding to the bit with the changed judgment result by adopting the judgment result of the iteration process;
s25, judging whether the check results of all bits pass;
if the check result of all bits passes, performing step S29, and if there is a bit that fails the check, performing step S26;
s26, judging whether the confidence information of all variable nodes in the current check layer is updated or not, and finishing bit judgment;
if the confidence information of all the variable nodes in the current check layer is updated and the bit judgment is completed, executing the step S27, otherwise, returning to the step S21;
s27, judging whether the maximum iteration number or the maximum calculation layer number is reached, if not, executing a step S28, otherwise, executing a step S29;
and S28, performing iterative check on the next check layer of the check matrix by adopting a row-layered minimum sum algorithm.
And S29, stopping iterative verification.
In the embodiment of the invention, the pipeline technology can be adopted to update the confidence information of the variable nodes, judge corresponding bits according to the updated confidence information and compare whether the judgment results of partial judgment results obtained by the current iteration of the current check layer are the same before and after judgment, so that the operational parallelism is improved.
It can be seen that in the decoding method of the LDPC code provided in the embodiment of the present invention, after bit decision information is given by each layer of operation of the decoder, only the check results of the check formulas involving the bits whose decision results change are corrected, and if all the check formulas pass, iteration is stopped; in addition, the iteration is stopped in advance in the embodiment of the invention, and the iteration can be stopped after the end of the first-layer operation or in the middle of the first-layer operation.
Compared with the existing standard algorithm for early iteration termination, the embodiment of the invention is equivalent in verification reliability. But the average iteration times of the decoding method adopting the scheme is obviously reduced, especially under the condition of relatively few errors. Fig. 5 shows a graph comparing the throughput of the decoder using two early termination methods. In this specific example, the decoder is for a solid state hard disk controller, the code rate of the low density parity check code used is about 0.89, the code length is slightly larger than 4KB, and the operating dominant frequency is assumed to be 800 MHz. When the decoding method is adopted, the pipeline technology is applied.
Referring to fig. 5, wherein the abscissa RBER is raw bit error rate, the raw bit error rate of the input decoder is represented, and the smaller the value, the smaller the average of the raw error number. The ordinate is the output throughput of the decoder. Therefore, in the region from 2E-5 to 6E-3 of the RBER, the decoder adopting the scheme of the invention achieves higher throughput rate, and particularly in the region with lower RBER, the throughput rate can be improved by 2-3 times.
For simplicity of explanation, the method embodiments are described as a series of acts or combinations, but those skilled in the art will appreciate that the embodiments are not limited by the order of acts described, as some steps may occur in other orders or concurrently with other steps in accordance with the embodiments of the invention. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred and that no particular act is required to implement the invention.
Fig. 6 is a schematic diagram showing the structure of an LDPC code decoding apparatus according to an embodiment of the present invention. Referring to fig. 6, the decoding apparatus of the LDPC code according to the embodiment of the present invention specifically includes a calculating module 201, a deciding module 202, a comparing module 203, an executing module 204, and a determining module 205, where:
the calculation module 201 is configured to update the confidence information of the variable node in the current check layer of the check matrix by using a row-layer minimum sum algorithm;
a decision module 202, configured to decide a corresponding bit according to the updated confidence information;
the comparison module 203 is configured to compare whether results before and after the current iteration decision of the current check layer are the same;
the execution module 204 is configured to update, if the results before and after the current iteration decision of the current check layer are different, the check result corresponding to the bit with the changed decision result by using the decision result of the current iteration process; for example, if the history check result corresponding to the bit whose decision result has changed is 0, the history check result is updated to 1, and if the history check result corresponding to the bit whose decision result has changed is 1, the history check result is updated to 0.
A judging module 205, configured to judge whether the check results of all bits pass;
the executing module 204 is further configured to stop the iterative check if the check results of all the bits pass.
In this embodiment of the present invention, the determining module 205 is further configured to determine whether the maximum iteration number or the maximum number of calculation layers is reached when the results before and after the current iteration decision of the current check layer are the same or bits that fail to be detected exist;
the execution module 204 is further configured to continue to perform iterative verification on a next verification layer of the check matrix by using the row-level minimum sum algorithm if the maximum iteration number or the maximum operation layer number is not reached, and otherwise, stop the iterative verification.
In the embodiment of the present invention, the apparatus further includes:
and the storage module is configured to store the decision result of the current iteration process of the current check layer in a preset storage location after the decision module 202 decides the corresponding bit according to the updated confidence information.
In this embodiment, after the calculation module 201 has updated the confidence information of all the variable nodes in the current check layer, the decision module 202 performs an operation of deciding corresponding bits according to the updated confidence information, the decision module 202 performs an operation of comparing whether the results before and after the current iteration decision of the current check layer are the same, or during the process of updating the confidence information of the variable nodes in the current check layer by the calculation module 201, the decision module 202 performs an operation of synchronously and concurrently performing a decision on corresponding bits according to the updated confidence information on the updated partial confidence information, and the decision module 202 performs an operation of comparing whether the results of partial decisions obtained by the current iteration of the current check layer are the same before and after the decision. Specifically, the calculation module 201, the decision module 202, and the comparison module 203 may adopt a pipeline technique to update the confidence information of the variable node, decide corresponding bits according to the updated confidence information, and compare whether the partial decision results obtained by the current iteration of the current check layer are the same before and after the decision.
For the device embodiment, since it is basically similar to the method embodiment, the description is simple, and for the relevant points, refer to the partial description of the method embodiment.
Furthermore, an embodiment of the present invention also provides a computer-readable storage medium, on which a computer program is stored, which when executed by a processor implements the steps of the method as described above.
In this embodiment, if the module/unit integrated with the decoding apparatus of the LDPC code is implemented in the form of a software functional unit and sold or used as an independent product, it may be stored in a computer-readable storage medium. Based on such understanding, all or part of the flow of the method according to the embodiments of the present invention may also be implemented by a computer program, which may be stored in a computer-readable storage medium, and when the computer program is executed by a processor, the steps of the method embodiments may be implemented. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, usb disk, removable hard disk, magnetic disk, optical disk, computer Memory, Read-Only Memory (ROM), Random Access Memory (RAM), electrical carrier wave signals, telecommunications signals, software distribution medium, and the like. It should be noted that the computer readable medium may contain content that is subject to appropriate increase or decrease as required by legislation and patent practice in jurisdictions, for example, in some jurisdictions, computer readable media does not include electrical carrier signals and telecommunications signals as is required by legislation and patent practice.
In addition, an embodiment of the present invention further provides an SSD device, which includes a storage controller, where the storage controller includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the steps of the method when executing the program. Such as steps S11-S18 shown in fig. 1. Alternatively, the processor implements the functions of each module/unit in the decoding apparatus embodiment of the LDPC code when executing the computer program, for example, the calculating module 201, the deciding module 202, the comparing module 203, the executing module 204, and the judging module 205 shown in fig. 6.
The decoding method, the decoding device, the storage medium and the SSD for the LDPC code provided by the embodiment of the invention only need to change the check result related to the variable node with the changed judgment result after each layer of operation, judge whether the updated check result passes the check, and stop the iterative check if the check result of all bits passes.
The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware. With this understanding in mind, the above-described technical solutions may be embodied in the form of a software product, which can be stored in a computer-readable storage medium such as ROM/RAM, magnetic disk, optical disk, etc., and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the methods described in the embodiments or some parts of the embodiments.
Furthermore, those skilled in the art will appreciate that while some embodiments herein include some features included in other embodiments, rather than other features, combinations of features of different embodiments are meant to be within the scope of the invention and form different embodiments. For example, any of the claimed embodiments may be used in any combination.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A method for decoding an LDPC code, the method comprising:
updating the confidence information of the variable nodes in the current check layer of the check matrix by adopting a row-layer minimum sum algorithm;
judging corresponding bits according to the updated confidence information;
comparing whether the results of the current check layer before and after the iteration judgment are the same;
if the results before and after the current iteration judgment of the current check layer are different, updating the check result corresponding to the bit with the changed judgment result by adopting the judgment result of the current iteration process;
judging whether the check results of all bits pass;
and stopping iterative verification if the verification results of all the bits pass.
2. The method of claim 1, further comprising:
if the results of the current check layer before and after the current iteration judgment are the same or bits which do not pass the detection exist, judging whether the maximum iteration times or the maximum operation layer number is reached;
and if the maximum iteration times or the maximum operation layer number is not reached, continuously adopting the row-layering minimum sum algorithm to carry out iterative verification on the next verification layer of the verification matrix, and otherwise, stopping the iterative verification.
3. The method of claim 1, wherein after deciding the corresponding bit according to the updated confidence information, the method further comprises:
and storing the judgment result of the current iteration process of the current check layer in a preset storage position.
4. The method according to any one of claims 1-3, further comprising:
after the confidence information of all variable nodes in the current check layer is updated, performing the operation of judging corresponding bits according to the updated confidence information and comparing whether the results before and after the current iteration judgment of the current check layer are the same; or
In the process of updating the confidence information of the variable nodes in the current check layer, the updated partial confidence information is synchronously and parallelly executed to judge corresponding bits according to the updated confidence information, and whether the judgment of partial judgment results obtained by the current iteration of the current check layer is the same or not is compared.
5. The method of claim 4, further comprising:
and updating the confidence information of the variable nodes by adopting a pipeline technology, judging corresponding bits according to the updated confidence information, and comparing whether the judgment results of partial judgment results obtained by the current iteration of the current check layer are the same before and after the judgment.
6. The method according to any one of claims 1 to 3, wherein the updating of the check result corresponding to the bit with the changed decision result by using the decision result of the current iteration process includes:
if the historical check result corresponding to the bit with the changed judgment result is 0, updating the historical check result to 1;
and if the historical check result corresponding to the bit with the changed judgment result is 1, updating the historical check result to be 0.
7. An apparatus for decoding an LDPC code, the apparatus comprising:
the calculation module is used for updating the confidence information of the variable nodes in the current check layer of the check matrix by adopting a row-layer minimum sum algorithm;
the judgment module is used for judging the corresponding bit according to the updated confidence coefficient information;
the comparison module is used for comparing whether the results of the current check layer before and after the iteration judgment are the same;
the execution module is used for updating the verification result corresponding to the bit with the changed judgment result by adopting the judgment result of the iteration process if the results before and after the iteration judgment of the current verification layer are different;
the judging module is used for judging whether the check results of all bits pass;
and the execution module is further used for stopping iterative verification if the verification results of all the bits pass.
8. The apparatus according to claim 1, wherein the determining module is further configured to determine whether a maximum iteration number or a maximum number of operation layers is reached when results before and after the current iteration decision of the current check layer are the same or bits that fail to be checked exist;
and the execution module is further used for continuously adopting the row-layering minimum sum algorithm to carry out iterative verification on the next verification layer of the verification matrix if the maximum iteration times or the maximum operation layer number is not reached, and otherwise, stopping the iterative verification.
9. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 8.
10. An SSD device, characterized in that it comprises a storage controller comprising a memory, a processor and a computer program stored on the memory and executable on the processor, which when executed by the processor implements the steps of the method according to any of claims 1-8.
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