CN114141544A - Electrode material of on-chip integrated super capacitor and preparation method thereof - Google Patents
Electrode material of on-chip integrated super capacitor and preparation method thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G11/00—Hybrid capacitors, i.e. capacitors having different positive and negative electrodes; Electric double-layer [EDL] capacitors; Processes for the manufacture thereof or of parts thereof
- H01G11/22—Electrodes
- H01G11/24—Electrodes characterised by structural features of the materials making up or comprised in the electrodes, e.g. form, surface area or porosity; characterised by the structural features of powders or particles used therefor
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G11/00—Hybrid capacitors, i.e. capacitors having different positive and negative electrodes; Electric double-layer [EDL] capacitors; Processes for the manufacture thereof or of parts thereof
- H01G11/22—Electrodes
- H01G11/30—Electrodes characterised by their material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G11/00—Hybrid capacitors, i.e. capacitors having different positive and negative electrodes; Electric double-layer [EDL] capacitors; Processes for the manufacture thereof or of parts thereof
- H01G11/22—Electrodes
- H01G11/30—Electrodes characterised by their material
- H01G11/46—Metal oxides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G11/00—Hybrid capacitors, i.e. capacitors having different positive and negative electrodes; Electric double-layer [EDL] capacitors; Processes for the manufacture thereof or of parts thereof
- H01G11/84—Processes for the manufacture of hybrid or EDL capacitors, or components thereof
- H01G11/86—Processes for the manufacture of hybrid or EDL capacitors, or components thereof specially adapted for electrodes
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
- Y02E60/13—Energy storage using capacitors
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Abstract
The invention discloses an electrode material of an on-chip integrated super capacitor and a preparation method thereof, wherein the electrode material comprises a graphical nano conducting layer and an ordered nano double-layer coaxial tube array, and the ordered nano double-layer coaxial tube array consists of nano double-layer coaxial tubes vertically grown on the nano conducting layer; the nanometer double-layer coaxial tube comprises a transition metal nanotube and a transition metal oxide nanotube growing on the inner side of the transition metal nanotube; the nano double-layer coaxial tube is provided with a secondary structure formed by nano holes. The electrode material has an orderly and controllable structure and a large specific surface area, provides more energy storage reaction points and improves the energy storage density; the nanotube and the secondary structure pore channel provide an ion transport channel, so that the charge and discharge efficiency is improved; the three-dimensional nanometer current collector formed by the nanometer conducting layer and the transition metal nanometer tube layer is directly conducted with the energy storage material to form a good charge conduction path, can be compatible with an on-chip plane process, and has the characteristics of on-chip integrated and flexible graphical preparation.
Description
Technical Field
The invention relates to the technical field of energy storage materials and devices, in particular to an electrode material of an on-chip integrated super capacitor and a preparation method thereof.
Background
The super capacitor is a novel green energy storage device, and is widely concerned by researchers due to the advantages of high charging and discharging speed, long cycle life, high power density, safety, reliability and the like. As a core component of a supercapacitor, an electrode has a critical influence on the energy storage performance of the supercapacitor. The micro super capacitor based On-chip (On-chip) energy storage application is a novel development direction in the field of energy storage, and the existing integration scheme based On the micro super capacitor is usually prepared by coating energy storage materials On a three-dimensional current collector which is prepared in a pre-separation manner, or by adopting a dealloying technology, or by adopting a flexible electrode material and by means of 3D printing and other methods. However, these solutions generally require separate steps independent of the on-chip processing, with limited integration; meanwhile, the technical bottlenecks of low utilization rate of the energy storage material caused by disordered accumulation of the energy storage material, random influence on charge transfer caused by contact between the active material in the electrode and a current collector and the like exist; in addition, in the conventional technical scheme, the slurry coating of the energy storage material and the dealloying technology are limited in that the preparation of the current collector is difficult to realize the direct patterning of the on-chip electrode, the 3D printing can realize the patterning more flexibly but is limited by the special printing material with good rheological property and conductivity, the available energy storage material is generally limited by a lower theoretical specific capacitance value, and the energy density and the power density are not satisfactory. Moreover, the conventional super capacitor applied to on-chip energy storage is developed towards a flexible substrate, and an electrode material and a preparation process of the super capacitor which are compatible with mainstream non-flexible substrates, such as integration, imaging and high performance of a common Si sheet of a semiconductor chip, are lacked. Therefore, development of a supercapacitor electrode material having high storage performance and suitable for on-chip patterning and integration and a preparation scheme for simple large-scale preparation of on-chip integration application are urgently needed.
Disclosure of Invention
The invention aims to solve the problems of low energy storage performance, complex preparation process, low integration level and the like in the existing on-chip integration application-oriented micro supercapacitor electrode material and the preparation process thereof in the prior art, and provides an on-chip integration supercapacitor electrode material and a preparation method thereof.
In order to achieve the above purpose, the invention provides the following technical scheme:
an electrode material of an on-chip integrated micro supercapacitor comprises a patterned nano conducting layer and an ordered nano double-layer coaxial tube array, wherein the ordered nano double-layer coaxial tube array is composed of nano double-layer coaxial tubes vertically grown on the nano conducting layer; the nanometer double-layer coaxial tube comprises a transition metal nanotube and a transition metal oxide nanotube growing on the inner side of the transition metal nanotube; the transition metal nanotube is composed of transition metal or transition metal alloy; the transition metal oxide nanotube is composed of an oxide with energy storage performance in a transition metal or a transition metal alloy of the transition metal nanotube; the wall of the nanometer double-layer coaxial tube is provided with a secondary structure formed by nanometer holes.
The electrode material comprises a patterned nano conducting layer prepared on a substrate and an ordered nano double-layer coaxial tube array directly and vertically grown on the nano conducting layer, wherein the ordered nano double-layer coaxial tube is composed of a transition metal nanotube and a transition metal oxide directly grown on the inner layer of the transition metal nanotube; the transition metal nanotube and the nanometer conducting layer in the nanometer double-layer coaxial tube are conducted to form a current collector of an on-chip integrated graphical three-dimensional nanostructure, and the transition metal oxide nanotube in the nanometer double-layer coaxial tube forms an energy storage functional layer and is in close and ordered contact with the transition metal nanotube. Transition metal oxides in the on-chip patterned electrode have large theoretical specific capacitance values and are orderly and directly coaxially grown in the transition metal nano tube to form mutual close contact, thereby avoiding disordered accumulation of energy storage materials and poor contact of the electrode, improving the utilization rate of the nano energy storage materials and simultaneously forming a stable and reliable charge transfer path; the transition metal nanotube and the nano conductive layer are conducted to form a graphical three-dimensional nano current collector, so that the specific surface area of the electrode material is effectively increased; the hollow structure of the nano coaxial tube provides a channel for charge and discharge reaction ion transportation; the wall of the transition metal nanotube and the transition metal oxide nanotube is provided with a secondary structure formed by nano holes with controllable size and distribution, so that the specific surface area of the electrode material is further increased, an additional ion transport channel is provided, the reaction activity is improved, and the charging and discharging efficiency is improved; the electrode material can be directly prepared on a substrate through a nano conductive layer and a precursor material layer which are prepared on a sheet in a patterning mode, and can realize patterning according to requirements and be compatible with on-sheet integration and patterning application.
The secondary structure on the nano double-layer coaxial tube is formed by self-assembly in the growth of the nano double-layer coaxial tube; the mechanism of the formation utilizes hydrogen precipitation and the space confinement effect of the nano-pore of the sacrificial layer when the transition metal nano-tube is prepared by the electrochemical deposition method, the hydrogen bubbles form a dynamic negative template and are limited by the space of nano-pores of the template, so that the pore distribution of nano-micropores along the growth direction of the nano-double-layer coaxial tube is changed from large to small, and the number of the pores is changed from small to large, and the formation of a secondary structure can be modulated by controlling the voltage and/or current density in the preparation process of the electrochemical deposition method.
Furthermore, the nano conductive layer and the precursor material layer can be subjected to different patterning according to different requirements in the practical application process by adopting a general exposure-etching planar micro-nano patterning process of a semiconductor process.
Further, the nano conductive layer is composed of one or more of an inactive metal film, an organic conductive film, an inorganic non-metal conductive film or an organic-metal composite film. Still further, the inactive metal is preferably Au or Pt or Cu or Cr, and the inorganic non-metallic conductive thin film is preferably graphene or a conductive two-dimensional material or various oxide conductive thin films such as ITO, RuO, etc.
Further, the transition metal is preferably one of Ni, Co, Fe, and Mn, and the transition metal alloy is preferably one of a Ni alloy, a Co alloy, a Fe alloy, and a Mn alloy.
Further, the transition metal oxide is one or more of Ni oxide, Co oxide, Fe oxide, Mn oxide, or Ni alloy, Co alloy, Fe alloy, Mn oxide with energy storage performance. Further, the transition metal oxide nanotubes are preferably NiO, CoO, FeO, Fe2O3、Fe3O4、Co2O3、Co3O4、Mn2O3、MnO2、Mn3O4Or alloy oxide CoFeO4、NiFeO4、FeNiO4、CoNiO4FeCoO4、FeNiO4And the like in one or more combinations.
On the other hand, the invention provides a preparation method of an electrode material of an on-chip integrated micro super capacitor, which comprises the following steps:
s10, preparing a nano conductive layer and a precursor material layer on the substrate in sequence by adopting a physical vapor deposition method, a chemical vapor deposition method, chemical wet growth or a spin coating method;
s20, obtaining a patterned nano conductive layer and a patterned precursor material layer on the substrate with the nano conductive layer and the precursor material layer obtained in the step S10 by adopting an ultraviolet exposure-etching planar micro-nano patterning process;
s30, on the basis of the patterned nano conducting layer and the patterned precursor material layer obtained in the step S20, oxidizing the precursor material layer by using an electrochemical anode to obtain an ordered nano porous one-way insulating template, and then etching the insulating barrier layer at the bottom of the holes of the ordered nano porous one-way insulating template by adopting electrochemical or chemical wet etching to obtain the insulating barrier layer with the thickness dTThe sacrificial layer having an aperture of ΦTAnd the ordered nano-porous template takes the nano-conductive layer as the bottom;
s40, preparing the length L and the wall thickness d by taking the sacrificial layer as a template by adopting an electrochemical deposition method on the basis of the sacrificial layer prepared in the step S30TMForming a tube wall having a secondary structureThe ordered transition metal nanotube array of (1), wherein L is not more than dT，dTM<0.5ΦT；
S50, preparing transition metal oxide nanotubes on the inner wall of the transition metal nanotube obtained in the step S40 to form an ordered nano double-layer coaxial tube array, wherein the outer layer of the nano double-layer coaxial tube is d'TMThe inner layer of the transition metal nanotube has a wall thickness dTMOxOf d'TM<dTM，dTMOx<0.5ΦT-dTM；
And S60, cleaning the ordered nano double-layer coaxial tube array obtained in the step S50, removing the sacrificial layer through selective etching, cleaning and drying to obtain the electrode material of the on-chip integrated micro supercapacitor.
The preparation method of the electrode material comprises the following steps: (1) preparing a nano conductive layer and a precursor material layer on a substrate, (2) patterning the nano conductive layer and the precursor material layer, (3) electrochemically anodizing the precursor material layer to prepare a sacrificial layer, (4) preparing a transition metal nanotube with a secondary structure in a template formed by the sacrificial layer by adopting an electrochemical deposition method, preparing an ordered nano double-layer coaxial tube array of transition metal/transition metal oxide with a double-layer coaxial tubular structure by adopting an integrated method, and (5) finally, selectively etching to remove the sacrificial layer. The invention adopts the early-stage sacrificial layer, so that a plurality of nano double-layer coaxial tubes can form an ordered array vertically growing on the nano conductive layer; the nano conductive layer and the ordered nano double-layer coaxial tube array can be integrally prepared on a chip to form an on-chip applied patterned micro supercapacitor electrode material; according to the invention, when the nano double-layer coaxial tube is prepared by an electrochemical deposition method, the thickness and the secondary structure of the nano double-layer coaxial tube can be adjusted by controlling the potential or current, the reaction time and the reaction temperature, so that different requirements for the super capacitor can be met.
Further, the substrate is Si or Si/SiO2Substrate or other chip substrate material.
Further, the thickness d of the nano conductive layerCIs 10 nm-500 nm.
Further, the precursor material layer is one of a Si thin film layer, an Al thin film layer and a Ti thin film layer, or a composite multilayer thin film layer composed of two or three of Si, Al and Ti, and the thickness d of the precursor material layerS50 nm-500 mu m.
Further, in the step S20, the nano conductive layer and the precursor material layer having the planar patterned structure are obtained by using not only an exposure etching planar micro-nano patterning process, but also a patterning mask method in the process of preparing the nano conductive layer and the precursor material layer by using a vapor deposition method or a chemical wet growth method in the step S10, so as to obtain the nano conductive layer and the precursor material layer having the planar patterned structure.
Further, the sacrificial layer is a porous silicon template, an aluminum oxide template (AAO), a titanium oxide Template (TAO) or a multi-layer composite porous template formed by the porous silicon template, the aluminum oxide template (AAO) and the titanium oxide Template (TAO).
Furthermore, the sacrificial layer is an ordered nano-porous single-pass insulating template which is prepared by performing electrochemical anodic oxidation on a precursor material layer grown on the nano-conductive layer and takes the nano-conductive layer as a base, and the aperture phi of the ordered nano-pores in the sacrificial layerTIs 50nm to 500nm, and the thickness d of the sacrificial layerTAnd the thickness d of the precursor material layerSThe same is true.
Further, the thickness of the transition metal nanotube is d'TM<dTMOf d'TMNot less than 5nm, preferably, the thickness d 'of the transition metal nanotube'TMIs 50 nm; wall thickness d of the transition metal oxide nanotubesTMOx<0.5ΦT-d'TM(ii) a The axial length of the nano double-layer coaxial tube in the ordered nano double-layer coaxial tube array is L, and L is not more than dTStill more preferably, L ═ 1 μm.
Further, in the step S50, the method for preparing the transition metal oxide nanotube on the inner wall of the transition metal nanotube includes: and after the ordered transition metal nanotube array prepared in the step S40 is finished, adding a buffering agent into the electrolyte system according to the electrolyte system Brieberry diagram to adjust the pH value of the electrolyte system, and then performing electrochemical deposition on the inner wall of the transition metal nanotube to form the ordered nano double-layer coaxial tube array.
Further, in the step S50, the method for preparing the transition metal oxide nanotube on the inner wall of the transition metal nanotube may further include: and (4) cleaning the ordered transition metal nanotube array prepared in the step (S40), soaking the ordered transition metal nanotube array in an oxidant solution, and carrying out oxidation reaction on the inner wall of the transition metal nanotube to form an ordered nano double-layer coaxial tube array. Furthermore, the oxidant solution is one or more of hydrogen peroxide, potassium permanganate and potassium dichromate.
Further, in the step S50, the method for preparing the transition metal oxide nanotube on the inner wall of the transition metal nanotube may further include: cleaning the ordered transition metal nanotube array prepared in the step S40, and then annealing at an annealing temperature T in an oxygen-containing atmosphereaAt 50-900 ℃ for an annealing time taIs 120 s-7200 s.
Further, in the S60 step, the alkaline solution is one or more of hydrofluoric acid, potassium hydroxide, sodium hydroxide, and the like.
Compared with the prior art, the invention has the beneficial effects that:
1. the electrode material provided by the invention has an arrayed and patterned three-dimensional nano-structure current collector, and the specific surface area of the electrode material can be effectively increased; the transition metal oxide can provide a large theoretical specific capacitance value; the coaxial structure enables the transition metal oxide layer with the energy storage function to directly grow on the inner layer of the transition metal nanotube to form a close contact and good charge transfer path; the coaxial nanotube structure in the ordered nano array also effectively avoids low utilization rate of the energy storage material and unsmooth charge transfer caused by random connection of the energy storage material and the current collector in the traditional technical scheme; the pore structure of the orderly arranged nanotubes and the secondary structure of the nanotubes further provide a transmission channel for ion transportation, increase the specific surface area and reaction points, and improve the energy storage performance of the super capacitor.
2. The nano conductive layer and the precursor material layer deposited on the wafer are subjected to physical vapor deposition compatible with a semiconductor chip, such as thermal evaporation or magnetron sputtering, and can be directly patterned on the wafer according to needs by a general exposure etching process. Compared with the traditional slurry coating, the method can not only avoid the disordered accumulation of energy storage materials and the performance deterioration caused by loose connection with electrodes, but also be better compatible with on-chip graphical integrated preparation; compared with the supercapacitor electrode on the chip prepared based on 3D printing, the method is not limited by material rheology and conductivity, and a metal oxide energy storage functional material with a large theoretical specific capacitance value can be selected.
3. The electrode material is directly prepared on the substrate of the chip, so that the defects of complex process, low integration level and difficult flexible imaging as required caused by a plurality of separation steps in the scheme of firstly preparing the electrode material of the micro super capacitor and then transferring and connecting the electrode material to the chip in the prior art are overcome.
4. In addition, the electrode material is prepared by electrochemistry or electrochemistry combined with thermal oxidation, has the advantages of low cost and convenient operation, and can be integrally prepared in an electrochemical device, thereby being beneficial to industrial automatic preparation.
Description of the drawings:
FIG. 1 is a schematic diagram of the preparation of the electrode material of the on-chip integrated micro supercapacitor provided by the invention;
FIG. 2 is a schematic structural diagram of an electrode material of an on-chip integrated micro supercapacitor provided by the invention;
FIG. 3 is a longitudinal sectional view of a medium-order nano double-layer coaxial tube of the electrode material of the on-chip integrated micro supercapacitor provided by the invention;
FIG. 4 shows the results of constant current charging and discharging tests of the electrode material prepared in example 2 of the present invention in a three-electrode system;
FIG. 5 is a graph of energy density versus power density performance for an electrode material prepared in example 2 of the present invention;
the labels in the figure are: 1-substrate, 2-nano conductive layer, 3-precursor material layer, 4-sacrificial layer, 5-transition metal nanotube, 6-transition metal oxide nanotube.
Detailed Description
The present invention will be described in further detail with reference to test examples and specific embodiments, but it should not be construed that the scope of the above-described subject matter of the present invention is limited to the following examples, and that techniques realized based on the contents of the present invention are within the scope of the present invention.
The electrode material prepared in the embodiment of the invention adopts an interdigital type during the imaging, and different imaging can be carried out according to specific requirements in the practical application process. In the embodiment, the electrochemical deposition method for preparing the ordered transition metal nanotube array adopts a three-electrode aqueous solution system electrochemical deposition device, the material of a device main body is made of acid-base resistant and electrochemically stable inert materials, preferably polytetrafluoroethylene and the like, and three electrodes are respectively a working electrode, a counter electrode and a reference electrode; the counter electrode is preferably a platinum mesh electrode, a graphite electrode and the like, the reference electrode is a calomel electrode or an Ag/AgCl electrode and the like, and the oxygen-free conductive copper sheet is in close contact with the nano conductive layer of the template to form the working electrode. The electrolyte can be prepared before use, and can be recycled or recovered after deposition is finished.
Example 1
The preparation process of the electrode material of this example is shown in FIG. 1.
S10, depositing on Si/SiO by physical vapor deposition method such as magnetron sputtering2Depositing a 100nm Au layer on the substrate as a nano conductive layer, and growing a 1 μm Al layer as a precursor material layer by physical vapor deposition such as thermal evaporation;
s20, preparing a photoetching plate with an interdigital pattern according to the requirement, spin-coating photoresist on the substrate for preparing the Au layer and the Al layer, carrying out ultraviolet exposure by using the interdigital photoetching plate, and developing, fixing and drying the photoresist to obtain a patterned photoresist layer on the Au/Al layer; removing the Au/Al layer which is not protected by the patterned photoresist layer by ion etching to obtain Si/SiO2An interdigital nano conductive layer/precursor material layer of photoresist, Au/Al, is covered on the substrate; ultrasonic cleaning is carried out for 15s in an acetone soaking solution to dissolve the photoresist, and the interdigital nano conductive layer/precursor material layer (Au/Al) on the chip is obtained through deionized water cleaning and drying;
s30, preparing the interdigital patterned Au/Al layer Si/SiO2Putting the substrate into an electrochemical reaction tank for anodic oxidation, wherein an Al film sample is taken as an anode, a graphite rod is taken as a cathode, 0.5mol/L oxalic acid solution is taken as electrolyte, and applying 50V voltage for primary anodic oxidation for 4-10h (15 ℃), preferably 5-7 h; cleaning a sample by using deionized water after primary oxidation, soaking the sample in a mixed solution (60 ℃) of 6mol/L phosphoric acid and 1.8mol/L chromic acid for 2h to remove a primary oxidation film, then performing secondary oxidation under the same oxidation condition for 2h, gradually reducing the oxidation voltage at the last stage of the secondary oxidation at the rate of 1 min/time, reducing the oxidation voltage to 1-2V from 50V to 18V at each time, reducing the oxidation voltage to 10V at 2 min/time, reducing the oxidation voltage to 8V at the rate of 3 min/time, stopping reducing the oxidation voltage at 8V, soaking the sample in 5% phosphoric acid for 1-2 h after 10min at 8V, etching to remove the insulation barrier layer remained at the bottom after the primary anodic oxidation, washing the sample by using deionized water, and drying to prepare the aperture phi based on the nano conductive layerTObtaining a 200-250 nm ordered nano-porous single-pass insulation template sacrificial layer2And the sacrificial layer of the Au/ordered porous anodic alumina with the interdigital pattern on the substrate is Au/AAO.
S40, in the electrochemical reaction tank, CE adopts a platinum net anode, an Ag/AgCl reference electrode, an oxygen-free conductive copper sheet and a nano conductive layer are tightly contacted to form a working cathode, a three-electrode system electrochemical deposition device is assembled to connect an electrochemical workstation and each electrode, and a certain amount of 0.3mol/LMnSO is injected4And 0.5mol/L (NH)4)2SO4And standing for 5-60 min after the electrolytic deposition solution is mixed, so that the electrolytic deposition solution and the interdigital integrated Au/AAO layer are fully soaked. By means of a constant pressure VdepDepositing a sacrificial layer-based Mn nanotube layer at a voltage higher than hydrogen evolution overpotential, maintaining the deposition at room temperature T-25 deg.C for a deposition time Tdep＝3600s, deionized cleaning and drying to obtain the ordered Mn nanotube array with a secondary structure, the average wall thickness d of the Mn nanotubesTM50nm, and an axial length L of 1 μm, wherein the secondary structure is shown in fig. 3.
S50, annealing the ordered Mn nanotube array prepared by the S40 in oxygen atmosphere at the annealing temperature TaAnnealing and oxidizing at 80 deg.C for taHeating up at a speed of 5 ℃/min for 1800s, annealing, and naturally cooling to obtain Mn/MnO2Ordered nano double-layer coaxial tube array, namely obtaining Si/SiO2Au/AAO-Mn @ MnO with interdigital graphics on substrate2。
S60, etching the intermediate AAO template prepared by the S50 selectively by 1mol/LKOH, and repeatedly cleaning and drying the intermediate AAO template by deionized water to obtain the intermediate AAO template integrated on Si/SiO2Interdigital patterned Au/Mn @ MnO on substrate2The electrode material of the ordered nanometer double-layer coaxial tube array super capacitor is shown in figure 2.
Example 2
Steps S10 to S30 of this example are the same as steps S10 to S30 of example 1.
S40, adopting platinum mesh electrode as anode, Ag/AgCl reference electrode, oxygen-free conductive copper sheet and nano conductive layer to form working cathode, assembling three-electrode system electrochemical deposition device, connecting electrochemical workstation and each electrode, injecting a certain amount of 0.038mol/LNiSO4And standing the electrolytic deposition solution for 5-60 min to fully soak the electrolytic deposition solution and the interdigital integrated Au/AAO layer. By means of a constant pressure VdepDepositing Ni nanotube layer based on sacrificial layer at 25 deg.c and room temperature for deposition time Tdep＝3000s, deionized and cleaned to obtain an ordered Ni nanotube array with a secondary structure, wherein the average wall thickness d of the Ni nanotubeTM50nm, axial length L6 μm.
S50, annealing the ordered Ni nanotube array prepared by S40 in oxygen-containing atmosphere at the annealing temperature TaAnnealing and oxidizing at 200 deg.C for taCooling naturally at a temperature rise rate of 5 ℃/min for 1800s to obtain Si/SiO2And the substrate is provided with an Au/AAO-Ni @ NiO ordered nano double-layer coaxial tube array with graphical interdigital.
Step S60 is the same as step S60 of example 1, resulting in an integrated Si/SiO2The electrode material of the supercapacitor is an Au/Ni @ NiO ordered double-layer coaxial tube array with graphical interdigital on a substrate.
Example 3
Steps S10 to S40 of this embodiment are the same as steps S10 to S40 of embodiment 2.
S50, placing the ordered Ni nanotube array prepared by the S40 in hydrogen peroxide (H)2O2) Soaking in solution to make oxidation reaction of inner wall of Ni nano tube to generate NiO nano tube layer, controlling oxidation reaction time tOXNiO nanotube thickness d was obtained 1200s TMOx15 nm-Ni @ NiO ordered nano double-layer coaxial tube array
This embodiment, step S50, oxidation, can be integrated by adding hydrogen peroxide solution directly to the original electrochemical deposition apparatus after removing the electrodes and fully cleaning.
Step S60 is the same as step S60 of example 2, resulting in an integrated Si/SiO2The electrode material of the supercapacitor is an Au/Ni @ NiO ordered double-layer coaxial tube array with graphical interdigital on a substrate.
Example 4
Steps S10 to S30 of this example are the same as steps S10 to S30 of example 1.
S40, adopting platinum net electrode as anode, Ag/AgCl reference electrode, oxygen-free conductive copper sheet and nano conductive layer to form working cathode, assembling three-electrode system electrochemical deposition device, connecting electrochemical workstation and each electrode, injecting a certain amount of 0.038mol/L, pH ═ 6.9(Co (Ac))2) And standing the electrolytic deposition solution for 5-60 min to fully soak the electrolytic deposition solution and the interdigital integrated Au/AAO layer. Adopting constant pressure-1V to deposit a Co nanotube layer based on a sacrificial layer, and keeping the room temperature T at 25 ℃ in the deposition process for a deposition time Tdep3600s, obtaining ordered Co nanotube array with secondary structure, average wall thickness d of Co nanotubeTMAxial length L is 3 μm at 40 nm.
S50, adding a proper amount of sodium acetate buffer into the electrolyte of the ordered Co nanotube array prepared in the step S40, adjusting the pH of the electrolyte to 7.5, and performing constant voltage VdepCo at 1V3O4Depositing the nanotube layer, keeping the room temperature T at 25 ℃ in the deposition process, and depositing for Tdep600s to obtain Co @ Co3O4Nano double layer coaxial tube array, in which Co3O4Thickness d of nanotube wallTMOx～10nm。
Step S60 is the same as step S60 of example 1, resulting in an integrated Si/SiO2Au/Co @ Co patterned with interdigital on substrate3O4An electrode material of a super capacitor of an ordered nano double-layer coaxial tube array.
Examples 5 to 9
Typical preparation parameters of electrode materials of different transition metal/transition metal oxide ordered nano-bilayer coaxial tube arrays of examples 5-9 are given in table 1.
Table 1 typical preparation parameters for example 5-9 electrode materials
The electrode material prepared in example 2 of the present invention was subjected to a discharge test, and the test result is shown in fig. 4, where the power density is 330mW/cm2The energy density is 9.32Whcm2And the specific capacitance value is 1125F/g @3A/g, and according to the results of the power density and the energy density of the electrode material, the electrode material provided by the invention meets the requirements of the electrode material of the super capacitor on the remote communication chip, as shown in figure 5.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (10)
1. The electrode material of the on-chip integrated micro supercapacitor is characterized by comprising a graphical nano conducting layer and an ordered nano double-layer coaxial tube array, wherein the ordered nano double-layer coaxial tube array is formed by nano double-layer coaxial tubes vertically growing on the nano conducting layer; the nanometer double-layer coaxial tube comprises a transition metal nanotube and a transition metal oxide nanotube growing on the inner side of the transition metal nanotube; the transition metal nanotube is composed of transition metal or transition metal alloy; the transition metal oxide nanotube is composed of transition metal of the transition metal nanotube or oxide with energy storage performance in the alloy thereof; the wall of the nanometer double-layer coaxial tube is provided with a secondary structure formed by nanometer holes.
2. The electrode material of the on-chip integrated micro supercapacitor as claimed in claim 1, wherein the nano conductive layer is composed of one or more of an inactive metal thin film, an organic conductive thin film, an inorganic non-metal conductive thin film or an organic-metal composite thin film; thickness d of nano conductive layercIs 10 nm-10 μm.
3. The electrode material of the on-chip integrated micro supercapacitor according to claim 1, wherein the transition metal is preferably one of Ni, Co, Fe and Mn, and the transition metal alloy is preferably one of Ni alloy, Co alloy, Fe alloy and Mn alloy.
4. The electrode material of the on-chip integrated micro supercapacitor according to claim 3, wherein the transition metal oxide and alloy oxide nanotube material is NiO, CoO, FeO, Fe2O3、Fe3O4、Co2O3、Co3O4、Mn2O3、MnO2、Mn3O4CoFeO4、NiFeO4、FeNiO4、CoNiO4 FeCoO4、FeNiO4One or more of (a).
5. The electrode material of the on-chip integrated micro supercapacitor as claimed in claim 1, wherein the secondary structure of the wall of the nano double-layer coaxial tube has a distribution characteristic that the average pore diameter is reduced from large to small and the number density of the pores is reduced from small to large along the growth direction of the nano tube.
6. A method for preparing an electrode material of an on-chip integrated micro supercapacitor according to any one of claims 1 to 5, comprising the steps of:
s10, preparing the thickness d on the substrate by adopting a physical vapor deposition method, a chemical wet growth method or a spin coating method in sequencecAnd thickness d of the nano-conductive layerSA precursor material layer of (a);
s20, obtaining a patterned nano conductive layer and a patterned precursor material layer on the substrate with the nano conductive layer and the precursor material layer obtained in the step S10 by adopting an ultraviolet exposure-etching planar micro-nano patterning process;
s30, on the basis that the graphical nano conducting layer and the graphical precursor material layer are obtained in the step S20, oxidizing the precursor material layer by using an electrochemical anode to obtain the ordered nano porous single-pass insulation template, and then etching the ordered nano porous single-pass insulation template hole bottom insulation barrier layer by adopting electrochemical or chemical wet etching to obtain the insulation barrier layer with the thickness dTThe sacrificial layer has an aperture phiTAnd the ordered nano-porous template takes the nano-conductive layer as the bottom;
s40, preparing the length L and the wall thickness d by taking the sacrificial layer as a template by adopting an electrochemical method on the basis of the sacrificial layer prepared in the step S30TMForming an ordered transition metal nanotube array, wherein L is not more than dT，dTM<0.5ΦT；
S50, preparing transition metal oxide nanotubes on the inner wall of the transition metal nanotube obtained in the step S40 to form an ordered nano double-layer coaxial tube array, wherein the outer layer of the nano double-layer coaxial tube is d'TMThe inner layer of the transition metal nanotube has a wall thickness dTMOxOf d'TM<dTM，dTMOx<0.5ΦT-dTM；
And S60, cleaning the ordered nano double-layer coaxial tube array obtained in the step S50, removing the sacrificial layer through selective etching, cleaning and drying to obtain the patterned electrode material of the on-chip integrated micro supercapacitor.
7. The method for preparing the electrode material of the on-chip integrated micro supercapacitor according to claim 6, wherein the precursor material layer is one of a Si thin film layer, an Al thin film layer and a Ti thin film layer, or a multi-layer composite thin film layer consisting of Si, Al and Ti, and the thickness d of the precursor material layerS50 nm-500 mu m.
8. The method for preparing the electrode material of the on-chip integrated micro supercapacitor according to claim 6, wherein the sacrificial layer is an ordered nano-porous single-pass insulating template which is prepared by electrochemically anodizing a precursor material layer grown on a nano-conductive layer and takes the nano-conductive layer as a bottom, and the diameter phi of the ordered nano-pores in the sacrificial layerTIs 50nm to 500nm, and the thickness d of the sacrificial layerTAnd the thickness d of the precursor material layerSThe same is true.
9. The method for preparing the electrode material of the on-chip integrated micro supercapacitor according to claim 8, wherein the wall thickness d 'of the transition metal nanotube'TMNot less than 5 nm; wall thickness d of the transition metal oxide nanotubesTMOx≤0.5ΦT-d'TM(ii) a The axial length of the nano double-layer coaxial tube in the ordered nano double-layer coaxial tube array is L, and L is not more than dT。
10. The method for preparing an electrode material of an on-chip integrated micro supercapacitor according to claim 6, wherein in the step of S50, the method for preparing the transition metal oxide nanotube on the inner wall of the transition metal nanotube comprises: after the ordered transition metal nanotube array prepared in the step S40 is finished, adding a buffering agent into an electrolyte system according to a electrolyte system Brieberry pattern to adjust the pH value of the electrolyte system, and then carrying out electrochemical deposition on the inner wall of the transition metal nanotube to grow a transition metal oxide so as to form an ordered nano double-layer coaxial tube array;
or cleaning the ordered array of the transition metal nanotube prepared in the step S40, placing the cleaned ordered array of the transition metal nanotube in an oxidant solution, and performing oxidation reaction on the inner wall of the transition metal nanotube to form an ordered nano double-layer coaxial tube array;
or cleaning the ordered transition metal nanotube array prepared in the step S40, and then annealing at the annealing temperature T in the oxygen-containing atmosphereaAt 50-900 ℃ for an annealing time taIs 120 s-7200 s.
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