CN114138667A

CN114138667A - Automatic test system and test method for SOC chip driving program

Info

Publication number: CN114138667A
Application number: CN202111500355.3A
Authority: CN
Inventors: 徐毅松; 李冠; 刘树伟; 王彬
Original assignee: Qingdao Fangcun Microelectronic Technology Co ltd; Shandong Fangcun Microelectronics Technology Co ltd
Current assignee: Qingdao Fangcun Microelectronic Technology Co ltd; Shandong Fangcun Microelectronics Technology Co ltd
Priority date: 2021-12-09
Filing date: 2021-12-09
Publication date: 2022-03-04

Abstract

An automated test system for SOC chip drivers, comprising: a PC end test system and an SOC end test board; the PC terminal test system comprises an automatic test program module and an operating system interface; the automated test program module comprises: the system comprises a test control module, a test case generation module, a cross compiling module, an SOC downloading module and a test monitoring program library; the system comprises a test case generation module, a drive source code library, a drive rule library and an SOC basic test framework, wherein the drive source code library, the drive rule library and the SOC basic test framework are used for inputting signals to the test case generation module; the SOC end test board includes: the SOC chip and the FPGA monitoring unit are connected through a peripheral interface and are respectively connected with the operating system interface through a PC communication interface. When the test system is used, test source code acquisition, test case generation, test firmware compilation, version information processing, test environment preparation, test operation, test report generation and the like are automatically completed by the test system, so that the manual intervention degree is reduced, the test efficiency is improved, and the complexity of test operation is reduced.

Description

Automatic test system and test method for SOC chip driving program

Technical Field

The invention discloses an automatic test system and a test method for a SOC (system on chip) chip driving program, belonging to the technical field of automatic test of SOC chips.

Background

With the development of computer technology, various SOC chips are widely used in various electronic systems. The SOC chip generally has the features of high integration level, abundant modules, strong specificity, etc. The SOC driving program is the basis of various SOC functional programs, and the whole function and stability of the electronic system are directly influenced if the driving program is perfect and stable. The comprehensive and efficient test is one of important means for ensuring the quality of the driving program.

The SOC module driver is highly specific and usually consists of a plurality of function functions, each function can transmit different parameters to implement different functions.

The SOC driver test is the final review of the drive requirement analysis, the design specification description and the code before the SOC driver is released, and is a key step for ensuring the program quality. The test is a process of executing a program under a specified condition for finding an error, that is, a process of elaborately designing a batch of test cases (i.e., input data and expected output results thereof) according to a specification and an internal structure of the program, and running the program using the test cases to find a program error. According to different test case design methods, the test is divided into: black box test, white box test and grey box test. Black-box testing, also known as functional testing or data-driven testing, treats the system as a Black box, and checks whether the function of the program meets its functional specifications only according to the requirements of the specification, regardless of the internal logic of the program. White-box testing, also known as structural testing or logic-driven testing, allows testers to design and select test cases for the internal logic structure and related information of a program and to test the logic path of the program. The Gray-box testing (Gray-box testing) is a testing strategy combining white box testing and black box testing, and is also called a hybrid testing method.

Module-driven testing, also called unit testing, is a minimum unit test, which is the lowest level of testing activity to be performed during system development. In the drive test, each drive unit implemented by the source code is tested to check whether each program module correctly implements a prescribed function, and the purpose is to find various errors that may exist inside each module.

In the traditional test process, a large amount of manual work is usually needed, if functional test is carried out, special test cases are compiled according to different module driving functions, a special test circuit for an SOC module to be tested is built, a test program is compiled, the test program is downloaded to an SOC chip, the test program is operated, and test results are observed and are subjected to statistical analysis. If test items such as coverage rate and random test need to be carried out, a large number of test cases need to be compiled according to different parameter combinations, the test process is repeated, and the test method is high in complexity and low in test efficiency.

Automated testing is a process that translates human-driven test behavior into machine execution. Typically, after a test case is designed and passes review, the test is performed step by a tester according to the procedures described in the test case, resulting in a comparison of the actual results with the expected results. In the process, in order to save manpower, time or hardware resources and improve the testing efficiency, the concept of automatic testing is introduced.

The automatic test and the traditional SOC drive test are combined, the problems of high complexity, low test coverage rate and low test efficiency of manual test are solved, the test quality is improved, and the test cost is reduced.

In view of this, the present technical field discloses the following patent documents:

chinese patent document CN111025129A is an automatic testing tool and testing method for SOC chips based on FPGA, and its key point is to describe how to use FPGA to test SOC chips, that is, how FPGA is connected and interacted with a chip to be tested, how to obtain test results, and the like. In such a test, if the SOC test is to be completed, a monitoring program at the FPGA end is required to be used as a cooperation to send out test excitation, record a test result, and the like. For testing low-speed peripheral interfaces such as UART, TIMER, SPI, I2C and the like, an FPGA end monitoring program is usually simpler, can contain the interface testing function at one time, and is downloaded to an FPGA in advance before the test starts. For high-speed complex modules such as SATA, PCIE, USB, GMAC, and algorithm accelerator, because the functions and test items are complex, the modules are limited by hardware resources of the FPGA device itself, and a single FPGA monitoring program may not include all test functions, so that to implement an automated test, the FPGA monitoring program needs to be dynamically loaded according to a test process in addition to dynamically loading the SOC end test firmware.

In chinese patent document CN111025129A, the internal hardware resources of the FPGA are usually limited, and for a complex interface module, the consumption of the FPGA resources is usually large, and it is not possible to integrate all the modules to be tested and their test functions at one time, so that the FPGA test monitoring program needs to be dynamically changed according to the test requirements. For the correctness test of the low-speed peripheral interface, the test case is usually fixed, no dynamic change is needed, and the correctness of the hardware interface is preferably verified. For the drive function test, the verification of the software interface is emphasized, and the change of the software interface is relatively flexible and the iteration speed is faster, so a set of PC end test system is needed to test in time according to the modification of the drive source code to ensure the development efficiency.

Chinese patent document CN112506793A embedded software unit testing method, system, readable medium and electronic device, which focuses on describing how to receive source code files, compiling rules, unit testing framework static library, unit testing codes and unit testing framework main function files, how to automatically compile test execution files, and rely on the electronic device to perform testing and obtain testing results.

The DSP, DSPD, PLD and the like mentioned in the Chinese patent document CN112506793A all have hardware resource limitation; the mentioned ASIC has relatively fixed hardware resources and cannot be dynamically modified. For embedded unit testing, some function functions are related to the current running environment of SOC hardware besides the code logic function, such as system clock frequency, chip temperature, voltage, etc., and different hardware environments may cause distinct testing results. Therefore, in order to make the test more realistic, the actual operating environment should be simulated as much as possible. If the document wants to achieve higher test randomness and coverage rate, the efficiency of manually compiling the test cases is low, and the test cases need to be compiled in an automatic mode. Meanwhile, the present document has different requirements for version tracing, and the use of version management usually requires that code management tools such as SVN (support vector network) and the like be deployed in advance, and a control function is integrated into a test system, so that the technical implementation is more complex compared with the case that the version management is not used.

In summary, the following technical problems still exist in the prior art:

1) the SOC chips are different, the interface complexity and the test requirements are different greatly, for the test of some complex SOC chips, based on the existing PFGA and other device hardware resources and cost consideration, a large and complete hardware test platform cannot be built, all tests cannot be completed at one time, therefore, test items need to be split, and the test platform is dynamically adjusted according to the test requirements.

2) The test environment and the operating environment are different in approximation degree, and a real hardware operating environment is required to be used for pursuing accuracy.

3) The test quantity of the driving function is large, usually a complex interface, the number of the driving functions is dozens, the parameter range and the parameter combination which can be transmitted by each function can be dozens of, and the efficiency is extremely low by manually writing the test case, so an automatic test case generating mechanism is needed.

4) The drive codes change and are developed and iterated along with requirements, the change is fast, if version management is not performed, the test reports and the test source codes are difficult to correspond, and later-stage tracing is not facilitated, so that version numbers need to be introduced by means of a version management tool.

Disclosure of Invention

Aiming at the defects of the prior art, the invention discloses an automatic test system for a SOC chip driver. The invention is composed of a PC end test main control program, an SOC driving source code library, an automatic test frame, a test target board based on FPGA and the like. The invention can automatically complete the basic function test of the SOC chip interface, the directional test of the driving program, the random test of the parameters, the combination and traversal test of the parameters, the aging test and the like, and generate the test report. The system can replace the traditional manual test, reduce the test complexity and improve the test efficiency.

The invention also discloses a test method of the system.

The detailed technical scheme of the invention is as follows:

an automatic test system for SOC chip drivers, comprising: a PC end test system and an SOC end test board;

the PC terminal test system comprises an automatic test program module and an operating system interface; the automated test program module comprises: the system comprises a test control module, a test case generation module, a cross compiling module, an SOC downloading module and a test monitoring program library; the system comprises a test case generation module, a drive source code library, a drive rule library and an SOC basic test framework, wherein the drive source code library, the drive rule library and the SOC basic test framework are used for inputting signals to the test case generation module;

the test control module respectively controls: the system comprises a test case generation module, a cross compiling module, an SOC downloading module, a test monitoring program library and an operating system interface;

the test case generation module, the cross compiling module, the SOC downloading module and the operating system interface are connected in sequence; the test monitoring program library is connected with the operating system interface;

the SOC end test board includes: the SOC chip and the FPGA monitoring unit are connected through a peripheral interface and are respectively connected with the operating system interface through a PC communication interface.

Preferably, according to the present invention, the test control module is configured to: and controlling the generation, compiling and downloading of SOC test firmware before testing, issuing test commands in testing, collecting and uploading test results and summarizing and outputting the test results.

According to the invention, the driving source code library is used for storing SOC driving source codes, and version management is preferably carried out by using SVN; as the development process of the SOC progresses, the driving source code library is continuously updated; the driving source code library is used as the only output source of the source code to be tested, a tester can select to use the current latest version or appoint a specific version code through the SVN version number for testing, and the corresponding version number is stored in a test report;

the drive rule base is used for determining a function call relation and a function parameter transmission range when a test case is generated, namely used for storing an SOC drive function call rule, a parameter transmission rule and the like, wherein the rule is formulated according to a drive design description and corresponds to a drive function one by one; the driving rule base uses SVN to manage the version, and updates when the function definition or the interface parameter is changed;

the SOC basic test framework is used for providing basic components and program frameworks required by testing, namely providing an initialization program, a test command processing program, a test result processing program and the like based on a specific SOC chip.

According to the invention, preferably, the test case generation module extracts the test source codes from the drive source code library according to the test requirements, generates the test cases according to the corresponding drive rules, merges the test cases with the basic components and the program framework, and finally generates the SOC test firmware source codes;

the cross compiling module is used for compiling the SOC test firmware source code into a binary file which can be executed by an SOC chip;

and the SOC downloading module is used for downloading the SOC chip executable binary file into the SOC chip through the operating system interface and the test chip communication interface.

According to the preferred embodiment of the present invention, the test monitoring program library is configured to detect a test behavior of the SOC chip peripheral module, and return a result under the control of the test control module, and the monitoring test program is extracted from the test monitoring program library and covers all peripheral interfaces of the SOC to be tested.

According to the invention, preferably, all external interfaces of the SOC chip, namely the target chip operated by the tested driver, are connected with the FPGA monitoring unit and are connected with the PC end through a USB or UART; the FPGA monitoring unit is connected with the SOC chip peripheral through pins, and corresponds the same interface function of SOC chip to the pin, for example SOC chip SPI interface connection to FPGA monitoring unit, then FPGA monitoring unit corresponds the pin, realizes being the SPI interface equally for detect SOC end SPI interface drive operation action, simultaneously, FPGA monitoring unit also is connected with the PC end through USB or UART.

Preferably according to the present invention, the PC communication interface includes: testing the chip communication interface and the monitoring unit communication interface: the SOC chip is connected with the operating system interface through a test chip communication interface; the FPGA monitoring unit is connected with the operating system interface through a monitoring unit communication interface.

The test chip communication interface is used for receiving a test binary file, a test command and feeding back a test result; the monitoring unit communication interface is used for receiving a test monitoring program, a test command and feeding back a test result.

The method for testing the SOC chip based on the system is characterized by comprising the following steps:

1) the test case generation module analyzes the test description script and extracts information to be tested, wherein the information to be tested comprises: information of a module to be tested, test type information (directional test, random test, coverage rate test), version information of a test code and the like;

2) the test case generation module extracts a corresponding driving source code according to the information of the module to be tested;

3) the test case generation module generates a test case according to the test type information and the drive rule, and the test case calls the tested drive function and transmits specified parameters;

4) the test case generation module guides the generated test case into an SOC test basic framework to form SOC test firmware source codes;

5) the cross compiling module compiles the SOC test firmware source code into an SOC chip executable binary file;

6) the SOC downloading module calls a PC system driver, and downloads the binary file to an SOC chip through a USB or UART in cooperation with an SOC BOOT program;

7) the test control module downloads the FPGA monitoring program to the FPGA monitoring unit;

8) the test control module respectively sends commands to the SOC chip and the FPGA monitoring unit through the PC communication interface:

controlling the SOC chip to initialize, sequentially executing test cases and returning test results;

for the internal module of the SOC (system on chip) (i.e. no pin is led out, and the internal module is not connected to a monitoring unit, such as DMA (direct memory access), TIMER (TIMER instrumentation) and the like), the test result is counted by the test case and is transmitted back to the PC (personal computer) end test system through the test chip communication interface; for the SOC chip peripheral module (namely pins are led out and connected to the monitoring unit, such as IIC, SPI and the like), interface behaviors are captured by the FPGA monitoring unit, and results are transmitted back to the PC end test system through the monitoring unit communication interface under the control of the test control module.

The SOC chip testing method based on the system is characterized by further comprising the following steps:

9) and the test control module performs statistical output on the collected test information to generate a test report.

The technical advantages of the invention are as follows:

1. based on the test system, developers only need to complete the compiling of the driving source code, formulate the driving rule and complete the compiling of the test description script, and the test system automatically completes the test source code acquisition, the test case generation, the test firmware compilation, the version information processing, the test environment preparation, the test operation, the test report generation and the like, so that the manual intervention degree is reduced, the test efficiency is improved, and the complexity of the test operation is reduced.

2. The test system has a test case generation function, sets rules according to the drive rule base, automatically generates test cases such as interface basic function test, driver oriented test, parameter random test, parameter combination, traversal test, aging test and the like, and improves test coverage and test accuracy.

3. The test system can capture the current test result, automatically generate a test report, label the current test time information, the test environment information, the test item, the test result, the test code version information and the like, and the test process can be controlled and traced.

4. The test source codes, the test rules, the monitoring programs and the like are managed by using an SVN version management tool, developers can update the codes or information at any time according to actual requirements, and the test system has high flexibility.

Drawings

FIG. 1 is a block diagram of an SOC chip driver automation test system according to the present invention;

FIG. 2 is a flow chart of the SOC chip driver automatic test system according to the present invention.

Detailed Description

The invention is described in detail below with reference to the following examples and the accompanying drawings of the specification, but is not limited thereto.

Examples 1,

An automated test system for SOC chip drivers, comprising: a PC end test system and an SOC end test board;

The test control module is used for: and controlling the generation, compiling and downloading of SOC test firmware before testing, issuing test commands in testing, collecting and uploading test results and summarizing and outputting the test results.

The driving source code library is used for storing SOC driving source codes, and preferably uses SVN to perform version management; as the development process of the SOC progresses, the driving source code library is continuously updated; the driving source code library is used as the only output source of the source code to be tested, a tester can select to use the current latest version or appoint a specific version code through the SVN version number for testing, and the corresponding version number is stored in a test report;

The test case generation module extracts test source codes from the drive source code library according to test requirements, generates test cases according to corresponding drive rules, merges the test cases with the basic components and the program framework, and finally generates SOC test firmware source codes;

The test monitoring program library is used for detecting the test behavior of the SOC chip peripheral module and returning the result under the control of the test control module, and the monitoring test program is extracted from the test monitoring program library and covers all peripheral interfaces of the SOC to be tested.

All external interfaces of the SOC chip, namely a target chip operated by the tested driver, are connected with the FPGA monitoring unit and are connected with the PC end through a USB or UART; the FPGA monitoring unit is connected with the SOC chip peripheral through pins, and corresponds the same interface function of SOC chip to the pin, for example SOC chip SPI interface connection to FPGA monitoring unit, then FPGA monitoring unit corresponds the pin, realizes being the SPI interface equally for detect SOC end SPI interface drive operation action, simultaneously, FPGA monitoring unit also is connected with the PC end through USB or UART.

The PC communication interface includes: testing the chip communication interface and the monitoring unit communication interface: the SOC chip is connected with the operating system interface through a test chip communication interface; the FPGA monitoring unit is connected with the operating system interface through a monitoring unit communication interface.

Examples 2,

The method for testing the SOC chip based on the system of the embodiment 1 comprises the following steps:

Examples 3,

Based on the method for testing the SOC chip by the system according to embodiment 2, the method further includes:

Application examples,

Taking the random test of the operating function parameters sent by the SATA interface as an example:

1) the developer completes the SATA sending operation driving function source code compiling and uploads the SVN; the function is shown as follows:

sata_send(address,length，buffer)

sending data in a buffer area inside the SOC to an address of external equipment through an SATA interface, wherein the length of the data is length;

2) a developer formulates a driving rule, in the application example, the value range of the adderss parameter of the sata _ send function is set to be 0-65536, the value range of the length parameter is set to be 0-128, and the value of the buffer parameter is 0/128/256; uploading the SVN according to the set driving rule;

3) a developer/tester compiles a test description script, in the application case, the SATA interface is appointed to be tested, the SATA _ send function is appointed to carry out parameter random test, the number of the parameter random test cases is appointed to be 10, and the latest source code in the current SVN source code library is appointed to be used for testing; the test description script is put into a specified directory of the test system so as to be read by the test system;

4) after the test system starts to operate, under the control of the test control module, the test case generation module, the cross compiling module and the SOC downloading module are called in sequence to carry out the following operations;

4-1) the test case generation module downloads the SATA interface driving source code file in the SVN driving source code library to the SOC test program compiling directory according to the latest version appointed in the test description script, and records the version number of the current file; the driving source code includes the function to be tested sata _ send;

4-2) the test case generation module acquires the test item information in the test description script and downloads the SATA interface driving rule in the SVN driving rule base; the application case is a parameter random test, so that 10 groups of parameter combinations are randomly generated within the range of the values of the address, length and buffer parameters, the parameter combinations are used as incoming parameters, a sata _ send function is called, a test source code file containing 10 cases is formed, and the test source code file is stored in a compiling directory;

4-3) the test case generation module acquires SOC basic test frame source codes from the SVN, stores the SOC basic test frame source codes in a compiling directory, modifies a compiling script, adds the SATA drive source codes and the test case source codes into SOC test firmware for compiling to form finished test firmware source codes;

4-4) compiling the test firmware source code by the cross compiling module according to the compiling script to generate a test binary file executable by the SOC;

4-5) an SOC downloading module, calling a PC system driver, and downloading the binary file into an SOC through a test chip communication interface by matching with an SOC BOOT program;

4-6) the test control module obtains the SATA interface test monitoring program from the SVN test monitoring program library according to the test script description, calls the PC system drive, and downloads the PC system drive to the FPGA monitoring unit through the monitoring unit communication interface;

4-7) the test control module sends a test starting command to the SOC chip and the FPGA monitoring unit, and the command is obtained by the SOC test program and the FPGA test monitoring program; after receiving the command, starting the test;

4-8) after the test is started, the SOC runs to sequentially run 10 test cases, 10 groups of test data are sent to the FPAG monitoring unit through the SATA interface, wherein address, length, buffer and other information,

compiling the test data according to an agreed rule for verifying the correctness;

4-9) the FPGA monitoring unit receives 10 groups of test data, analyzes the check data according to an agreed rule, judges whether the transmission process is normal or not, and records the test result;

4-10) the test control module monitors the test process, reads the test result recorded by the test monitoring unit after the test is finished, and generates a test report, wherein the test report comprises time information, current test code version information, test case information, test operation result and the like;

4-11), the test control module cleans the relevant test environment of the PC end and SOC end test board and waits for the next test.

Claims

1. An automatic test system for SOC chip drivers, comprising: a PC end test system and an SOC end test board;

2. The system of claim 1, wherein the test control module is configured to: and controlling the generation, compiling and downloading of SOC test firmware before testing, issuing test commands in testing, collecting and uploading test results and summarizing and outputting the test results.

3. The system for automatically testing the SOC chip driver of claim 1, wherein the driver source code library is used for storing SOC driver source codes, and preferably performing version management by using SVN;

the driving rule base is used for determining a function calling relation and a function parameter transmission range when a test case is generated;

the SOC basic test framework is used for providing basic components and a program framework required by testing.

4. The system of claim 1, wherein the test case generation module extracts test source codes from a source code library according to test requirements, generates test cases according to corresponding driving rules, merges the test cases with the base component and the program framework, and finally generates SOC test firmware source codes;

5. The system of claim 1, wherein the test monitor library is configured to detect a test behavior of the SOC chip peripheral module and return a result under control of the test control module.

6. The system of claim 1, wherein the SOC chip has all peripheral interfaces connected to the FPGA monitoring unit and connected to the PC terminal via USB or UART.

7. The system of claim 1, wherein the PC communication interface comprises: testing the chip communication interface and the monitoring unit communication interface: the SOC chip is connected with the operating system interface through a test chip communication interface; the FPGA monitoring unit is connected with the operating system interface through a monitoring unit communication interface.

8. The system of claim 1, wherein the test chip communication interface is configured to receive a test binary file, a test command, and a feedback test result; the monitoring unit communication interface is used for receiving a test monitoring program, a test command and feeding back a test result.

9. The method for testing the SOC chip based on the system according to any of claims 1-8, comprising:

1) the test case generation module analyzes the test description script and extracts information to be tested;

6) the SOC downloading module is used for downloading the binary file to the SOC chip through a USB or a UART;

for the internal module of the SOC, the test result is counted by the test case and is transmitted back to the PC end test system through the test chip communication interface; for the SOC chip peripheral module, the interface behavior is captured by the FPGA monitoring unit, and the result is transmitted back to the PC end test system through the monitoring unit communication interface under the control of the test control module.

10. The method for testing an SOC chip according to claim 9, wherein the method further comprises: