CN114138583A

CN114138583A - On-line detection method and device for connectivity between chips, electronic equipment and storage medium

Info

Publication number: CN114138583A
Application number: CN202111497084.0A
Authority: CN
Inventors: 刘熙
Original assignee: Ruijie Networks Co Ltd
Current assignee: Ruijie Networks Co Ltd
Priority date: 2021-12-09
Filing date: 2021-12-09
Publication date: 2022-03-04

Abstract

According to the method, the device, the electronic equipment and the storage medium for detecting connectivity between chips, the corresponding test message is generated through the configuration information of the message detection path, so that the test message carries the port identification information corresponding to all the ports to be tested; inputting a test message into a chipset to be tested, and transmitting an original communication test message among ports to be tested through respective operations such as forwarding and the like executed by a programmable chip and a plurality of heterogeneous chips which form the chipset to be tested; the operation of forwarding the message, packaging the message and feeding back the tracking message, which is executed by the programmable chip, enables each heterogeneous chip to realize the on-line detection of the heterogeneous chip by forwarding the test message under the condition of not influencing the operation of other services of each heterogeneous chip. The method for detecting connectivity between chips on line provided by the embodiment of the application can adapt to different topology changes of the chip set to be tested, and realizes on-line detection, thereby reducing the time cost required by detection.

Description

On-line detection method and device for connectivity between chips, electronic equipment and storage medium

Technical Field

The present application relates to the field of communication detection, and in particular, to an on-line detection method and apparatus for connectivity between chips, an electronic device, and a storage medium.

Background

The generic programmable data plane is a basis for implementing network software and programming, wherein a typical generic programmable data plane concept is a Portable Switch Architecture (PSA), which is evolved from a conventional programmable Protocol Independent Switch Architecture (PISA). Further, a composite Architecture comprising a plurality of PSA sub-architectures, namely a dofenox Native Architecture (TNA), has evolved, and the TNA Architecture is the basis for building heterogeneous chip sets for interconnection of different chip devices.

In the heterogeneous chipset based on the TNA architecture, different chip devices are respectively interconnected with physical ports of each PSA sub-architecture in the TNA architecture, wherein each PSA sub-architecture has a plurality of physical ports, and the PSA sub-architectures are regarded as respective ingress network ports and respective egress network ports corresponding to the PSA sub-architectures according to different port roles. Generally, an external port connected to a heterogeneous chipset sends a message to a corresponding chip device on the heterogeneous chipset, the message is processed by the chip device, then transmitted to an ingress network end of a corresponding PSA sub-architecture, sent to an egress network end of another PSA sub-architecture by the ingress network end of the PSA sub-architecture, and sent by the egress network end to another chip device connected to the PSA sub-architecture for processing, and the above steps are repeated. And after the message is processed by each chip device, the message is sent back to the connected external port to finish all the steps, and the message transmission channel of the heterogeneous chipset is considered to be normal.

Therefore, when the message is transmitted inside the heterogeneous chipset, each chip device obtains the message from the exit network end of the corresponding PSA sub-architecture, and sends the message to the entrance network end of the corresponding PSA sub-architecture after being processed by each chip device. And regarding the connected external port, each entrance network end, each exit network end and each chip device in the heterogeneous chipset as each node on the message transmission channel, and detecting whether the message transmission channels of the heterogeneous chipset are communicated, namely detecting whether the nodes on the message transmission channels are communicated. The connectivity among the nodes is detected, which is beneficial to timely finding out the fault on the message transmission channel, and corresponding processing is carried out according to the found fault, thereby reducing the influence on service forwarding.

The existing detection technology is based on setting corresponding forwarding rules on each involved node. When the message is transmitted to a certain node, the node matches out a corresponding forwarding rule according to a preset field in the current message, forwards the message to the next node according to the forwarding rule, and simultaneously counts the number of the message. The following defects exist in the detection mode:

1. the set forwarding rule needs to be topologically coupled with the connection mode between each chip device in the heterogeneous chipset, that is, for different connection modes, a corresponding forwarding rule needs to be set, so that the detection mode has higher cost in practical application.

2. The existing detection technology can not detect the connectivity of the message transmission channel of the heterogeneous chipset executing the service, i.e. the online detection of the message transmission channel can not be performed, which results in extra time cost.

Disclosure of Invention

The embodiment of the application provides an inter-chip connectivity online detection method, an inter-chip connectivity online detection device, electronic equipment and a storage medium, which can adapt to topological changes of connection modes among chip devices in a heterogeneous chipset and realize online detection, so that the time cost of detection is reduced.

In a first aspect, a first method for detecting connectivity between chips provided in an embodiment of the present application includes:

aiming at a chipset to be tested, obtaining configuration information corresponding to a message detection path preset by the chipset to be tested, wherein the configuration information at least comprises: and port identification information of each appointed port to be tested in the message detection path.

And generating an original connection test message carrying the identification information of each port, and recording the generation time of the original connection test message.

Inputting an original communication test message into a chip set to be tested, transmitting the original communication test message among the ports to be tested according to the arrangement sequence of the ports to be tested in a message detection path through the chip set to be tested until the original communication test message output by the chip set to be tested is received, and recording the receiving time of the original communication test message, wherein a tracking message which is fed back by the chip set to be tested and aims at one port to be tested is received every time the original communication test message passes through one port to be tested.

And calculating corresponding time difference according to the generation time and the receiving time of the original connected test message, and combining each received tracking message to obtain a corresponding detection result.

In a second aspect, a second method for detecting connectivity between chips provided in an embodiment of the present application includes:

the method comprises the steps that a chip set to be tested receives an original communication test message sent by test equipment, wherein the original communication test message at least carries port identification information of each appointed port to be tested, which is preset aiming at a message detection path.

And the chipset to be tested transmits the original communication test message among the ports to be tested according to the arrangement sequence of the ports to be tested in the message detection path, wherein each time the chipset passes through one port to be tested, a tracking message aiming at the port to be tested is fed back to the test equipment.

And the chip set to be tested outputs the original communication test message to the test equipment, so that the test equipment calculates corresponding time difference based on the generation time and the receiving time of the original communication test message, and acquires a corresponding detection result by combining each received tracking message.

In a third aspect, a first apparatus for detecting connectivity between chips provided in an embodiment of the present application includes:

the acquisition module is used for acquiring configuration information corresponding to a message detection path preset by a chipset to be tested aiming at the chipset to be tested, wherein the configuration information at least comprises: and port identification information of each appointed port to be tested in the message detection path.

And the generating module is used for generating original connection test messages carrying the identification information of each port and recording the generating time of the original connection test messages.

The communication module is used for inputting the original communication test message into the chip set to be tested, transmitting the original communication test message among the ports to be tested according to the arrangement sequence of the ports to be tested in the message detection path through the chip set to be tested until the original communication test message output by the chip set to be tested is received, and recording the receiving time of the original communication test message, wherein each time the original communication test message passes through one port to be tested, the communication module receives a tracking message which is fed back by the chip set to be tested and aims at one port to be tested.

And the calculation module is used for calculating corresponding time difference according to the generation time and the receiving time of the original connection test message and obtaining corresponding detection results by combining each received tracking message.

In an optional embodiment, when the generating module generates an original connectivity test packet carrying identification information of each port, the generating module is specifically configured to:

and generating an original communication test message, acquiring identification information of each port, and storing the identification information in an associated area of the original communication test message in a stacking mode according to the arrangement sequence of each port to be tested in the message detection path.

In an optional embodiment, when the corresponding time difference is calculated according to the generation time and the receiving time of the original connection test packet, and a corresponding detection result is obtained by combining each received trace packet, the calculation module is specifically configured to:

and calculating the corresponding time difference according to the generation time and the receiving time of the original connection test message.

When the time difference is within a preset time difference threshold value range, determining that the detection result is as follows: and the message detection paths are communicated.

When the time difference is not within the preset time difference threshold value range, determining a target fault port according to each received tracking message, and determining that the detection result is as follows: the message communication path fails, and the failure port is a target failure port.

In an optional embodiment, when determining the target failure port according to each received trace packet, the calculation module is specifically configured to:

acquiring the number of the received tracking messages, and judging whether the number of the received tracking messages is smaller than the number of the ports to be tested, wherein:

and if the number of the tracking messages is smaller than that of the ports to be tested, determining the subsequent ports to be tested of the ports to be tested corresponding to the latest received tracking messages as target fault ports according to the arrangement sequence of the ports to be tested in the message detection path.

If the data of the trace messages is equal to the number of the ports to be tested, the following operations are executed for each trace message:

and acquiring time information for receiving the tracking message aiming at the tracking message, and acquiring a time difference corresponding to the tracking message according to response information carried by the tracking message, wherein the response information at least comprises the time information for generating the tracking message.

And if the time difference corresponding to the tracking message is greater than a preset time difference threshold value, determining that the port to be tested corresponding to the tracking message is a target fault port according to the arrangement sequence of the ports to be tested in the message detection path.

And if the time difference corresponding to the tracking message is less than or equal to a preset time difference threshold value, receiving the next tracking message.

In a fourth aspect, an on-line detection apparatus for connectivity between chips provided in an embodiment of the present application includes:

the receiving module is used for receiving an original connection test message sent by the test equipment, wherein the original connection test message at least carries port identification information of each specified port to be tested, which is preset aiming at the message detection path.

And the transmission module is used for transmitting the original communication test message among the ports to be tested according to the arrangement sequence of the ports to be tested in the message detection path, wherein each time the original communication test message passes through one port to be tested, a tracking message aiming at one port to be tested is fed back to the test equipment.

And the output module is used for outputting the original connection test message to the test equipment so that the test equipment calculates the corresponding time difference based on the generation time and the receiving time of the original connection test message, and combines each received tracking message to obtain a corresponding detection result.

In an alternative embodiment, the chipset under test comprises: the system comprises a plurality of chips to be tested, a plurality of test control units and a plurality of test control units, wherein the chips to be tested comprise a programmable chip and a plurality of heterogeneous chips; the port to be tested includes: the to-be-tested inlet net end and the to-be-tested outlet net end correspond to the to-be-tested chips respectively;

when the chipset to be tested transfers the original connectivity test packet among the ports to be tested according to the sequence of the ports to be tested in the packet detection path, the transfer module is specifically configured to:

and correspondingly forwarding and packaging the original connection test message by the programmable chip based on the port identification information which is carried in the original connection test message and is set aiming at the programmable chip, wherein a corresponding tracking message is fed back to the test equipment by each port to be tested.

And performing corresponding forwarding operation on the original connection test message through the heterogeneous chips based on the obtained forwarding information which can be respectively identified by the heterogeneous chips, so that the programmable chip can generate a corresponding tracking message according to the original connection test message which is respectively forwarded by the heterogeneous chips and feed back the tracking message to the test equipment.

In an optional embodiment, when the original connectivity test packet is subjected to corresponding forwarding and encapsulation operations by the programmable chip based on the port identification information, which is set for the programmable chip and carried in the original connectivity test packet, the transfer module is specifically configured to:

and acquiring port identification information set for the programmable chip from the received original connection test message by the programmable chip in a pop-up mode, and packaging the original connection test message based on a preset message format.

And transmitting the packaged original connection test message between every two ports to be tested in the programmable chip based on the port identification information set for the programmable chip through the programmable chip, and outputting the original connection test message to at least one heterogeneous chip.

And the programmable chip generates a corresponding trace message according to the original connection test message, generates corresponding response information aiming at the connection condition of the port to be tested in the programmable chip, and feeds back the trace message carrying the response information to the test equipment, wherein the response information at least comprises time information for generating the trace message.

In an optional embodiment, when the forwarding information that can be respectively identified by the plurality of heterogeneous chips is obtained through the plurality of heterogeneous chips, and the original connection test packet is subjected to a corresponding forwarding operation, the transfer module is specifically configured to:

for the plurality of heterogeneous chips, respectively executing the following operations:

and obtaining forwarding information which can be identified by the heterogeneous chip from the received packaged original connection test message.

Based on forwarding information recognizable by the heterogeneous chip, the packaged original connection test message is transmitted between every two ports to be tested in the heterogeneous chip and is output to the programmable chip, so that the programmable chip can generate a corresponding trace message according to the packaged original connection test message output by the heterogeneous chip and feed back the trace message to the test equipment.

In a fifth aspect, an embodiment of the present application further provides an electronic device, which includes a memory and a processor, where the memory stores a computer program that is executable on the processor, and when the computer program is executed by the processor, the processor is enabled to implement the on-line detection method for inter-chip connectivity of the first aspect or the second aspect.

In a sixth aspect, an embodiment of the present application further provides a computer-readable storage medium, where a computer program is stored in the computer-readable storage medium, and when the computer program is executed by a processor, the method for detecting connectivity between chips in the first aspect or the second aspect is implemented.

For technical effects brought by any one implementation manner in the third aspect to the sixth aspect, reference may be made to technical effects brought by a corresponding implementation manner in the first aspect or the second aspect, and details are not described here again.

In the embodiment of the application, a corresponding test message is generated through configuration information of a message detection path, so that the test message carries port identification information corresponding to all ports to be tested; inputting a test message into a chipset to be tested, and transmitting an original communication test message among ports to be tested through respective operations such as forwarding and the like executed by a programmable chip and a plurality of heterogeneous chips which form the chipset to be tested; the generated test message contains the port identification information of each port to be tested in advance, so that the connection mode among the chip devices in the chip set does not need to be considered, the forwarding rule on each chip device is set according to the connection mode, the port identification information is obtained from the test message, the forwarding of the test message is completed according to the obtained port identification information, the mode can better adapt to different topological structure changes among the chip sets, and the universality is stronger. Meanwhile, in the embodiment of the application, the test message is packaged through the programmable chip, so that each heterogeneous chip can obtain the corresponding port identification information based on the packaged test message format, for each heterogeneous chip, only corresponding forwarding operation needs to be executed on the test message, and the forwarding operation does not influence other services executed by the heterogeneous chip per se, so that online detection of each heterogeneous chip in the test chipset can be realized through the method, and online detection of the message channel connectivity among the chips in the test chipset can be realized.

In summary, the method for detecting connectivity between chips provided by the embodiment of the present application can adapt to different topology changes of a chipset to be tested, and realize online detection, thereby reducing the time cost required for detection.

Drawings

FIG. 1 is a diagram of a topology architecture of a chipset under test provided by an embodiment of the present application;

fig. 2 is a schematic diagram of a first method for detecting connectivity between chips in an online manner according to an embodiment of the present disclosure;

fig. 3 is an exemplary diagram of on-line detection of connectivity between chips according to an embodiment of the present disclosure;

fig. 4 is an exemplary diagram of a message test path provided in the embodiment of the present application;

fig. 5 is an exemplary diagram of a package format of an original connectivity test packet according to an embodiment of the present application;

fig. 6 is an exemplary diagram of a trace packet encapsulation format according to an embodiment of the present application;

FIG. 7 is an exemplary diagram of another on-line detection of inter-chip connectivity provided in an embodiment of the present application;

fig. 8 is a schematic diagram illustrating a method for calculating a result of detecting connectivity between chips according to an embodiment of the present disclosure;

fig. 9 is a schematic diagram of a second method for detecting connectivity between chips in an online manner according to an embodiment of the present disclosure;

fig. 10 is a schematic diagram of a first apparatus for detecting connectivity between chips according to an embodiment of the present disclosure;

fig. 11 is a schematic diagram of a second apparatus for detecting connectivity between chips according to an embodiment of the present disclosure;

fig. 12 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

For convenience of understanding, some terms or expressions appearing in the course of describing the embodiments of the present application will be explained as follows:

the programmable chip comprises: the interface chip is capable of controlling the configuration of an interface circuit in the chip by a computer instruction, for example, a general chip resource (e.g., table, counter, meter, register) provided by a programmable chip can be defined by using a P4 language, so as to achieve the purpose of customizing a data plane forwarding function.

Message: the method refers to a data unit exchanged and transmitted in a network, and is used for bearing complete data information to be transmitted, wherein a message is continuously encapsulated into corresponding groups, packets and frames in the transmission process, that is, a message header consisting of some control information is added to the header of the message, so that actually readable contents are often programmed into the middle section of the message before the message is transmitted.

In order to adapt to various topology changes of a chipset to be tested, the inter-chip connectivity online detection method provided in the embodiment of the present application generates an original connectivity test packet carrying port identification information of all ports to be tested on a preset packet detection path, and transmits the original connectivity test packet among the ports to be tested in the chipset to be tested according to the arrangement sequence of the ports to be tested in the packet detection path, receives trace packets sent by the ports to be tested during the transmission process, and determines the connectivity of the packet detection path according to the received trace packets. Meanwhile, the method for detecting connectivity among chips provided by the embodiment of the application can realize synchronous connectivity detection under the condition that the service of the chipset to be tested normally runs, thereby further reducing the detection cost.

Referring to fig. 1, a schematic topology diagram of a chipset to be tested according to an embodiment of the present application is shown, where the chipset to be tested includes: heterogeneous chip 1, heterogeneous chip 2, heterogeneous chip 3 and programmable chip A. On the three heterogeneous chips, each has a corresponding physical port, for example, as shown in table 1 below:

TABLE 1

The programmable chip A is based on a TNA architecture and consists of a plurality of programmable logic blocks with PSA substructures, namely a plurality of pipelines working independently, and each pipeline is respectively interconnected with a corresponding heterogeneous chip. Referring to fig. 1, under the TNA architecture, the programmable chip a has pipeline0, pipeline1, pipeline2 and pipeline3 which work independently, wherein each pipeline has a plurality of physical ports, for example, as shown in table 2 below:

TABLE 2

pipeline	Entrance net end	Outlet net end
			pipeline0	Port 001, port 003	Port 002, port 004
pipeline1	Port 101, port 103	Port 102, port 104
			pipeline2	Port	201, port 203	Port 202, port 204
pipeline3	Port 301, port 303	Port 302, 304

The physical ports of pipeline1, pipeline2 and pipeline3 in the programmable chip a are respectively interconnected with the physical ports of the corresponding heterogeneous chip 1, heterogeneous chip 2 and heterogeneous chip 3, and the physical ports of the pipeline in the programmable chip a are interconnected with each other, so that a chipset to be tested is formed.

Referring to fig. 2, based on the topology structure of the chipset to be tested, the embodiment of the present application provides a first method for detecting connectivity between chips on line for an external detection device connected to the chipset to be tested, including:

step 201: aiming at a chipset to be tested, obtaining configuration information corresponding to a message detection path preset by the chipset to be tested, wherein the configuration information at least comprises: and port identification information of each appointed port to be tested in the message detection path.

Referring to fig. 3, in a chipset to be tested, pipeline0 of a programmable chip is interconnected with an external detection device, and in the detection device as shown in the figure, a first method for detecting connectivity between chips is performed, where the external detection device is an external device with certain computing capability, such as a CPU or a message detector, where a port 0A is an exit end of a message sent by the message detection device, and a port 0B is an entry end of the message detection device receiving a return message.

In an embodiment of the present application, a chipset to be tested includes: the test system comprises a plurality of chips to be tested, and specifically comprises a programmable chip and a plurality of heterogeneous chips. The corresponding port to be tested includes: the programmable chip to be tested comprises a plurality of programmable chips to be tested, a plurality of to-be-tested inlet net ends and to-be-tested outlet net ends, wherein the programmable chips to be tested respectively correspond to the to-be-tested inlet net ends and the to-be-tested outlet net ends, and the to-be-tested inlet net ends and the to-be-tested outlet net ends of the heterogeneous chips respectively.

In the specific embodiment of the present application, for each port in the chipset to be tested, the following ports are selected as the ports to be tested, as shown in table 3 below:

TABLE 3

Specifically, referring to fig. 4, a preset packet detection path in the embodiment of the present application covers each port shown in table 3, and a transmission order of a packet in the packet detection path is as follows:

port 0A (external detection device) -port 001(pipeline0) -port 104(pipeline1) -port 1B (heterogeneous chip 1) -port 1A (heterogeneous chip 1) -port 101(pipeline1) -port 202(pipeline2) -port 2B (heterogeneous chip 2) -port 2A (heterogeneous chip 2) -port 203(pipeline2) -port 302(pipeline3) -port 3B (heterogeneous chip 3) -port 3A (heterogeneous chip 3) -port 301(pipeline3) -port 004(pipeline0) -port 0B (external detection device).

The port identification information represents identification information of each port to be tested in the message detection path, for example, port addressing information. Specifically, for example, for a tofino programmable chip, a PORT is represented using a DEV _ PORT of 9 bits. In the embodiment of the present application, it is assumed that the port identification information corresponding to each port to be tested is shown in table 4 below:

TABLE 4

Based on table 4 above, the designated port identification information is selected.

Step 202: and generating an original connection test message carrying the identification information of each port, and recording the generation time of the original connection test message.

Specifically, an original connection test message is generated, and the identification information of each port is acquired and stored in the association area of the original connection test message in a stack form according to the arrangement sequence of each port to be tested in the message detection path.

Optionally, an original connectivity test packet in a predetermined packet format is generated, for example, the original connectivity test packet in this embodiment is a Ping packet.

In this embodiment, optionally, because each physical port of each heterogeneous chip is interconnected with each physical port of the programmable chip, and the transmission of the packet between the interconnected ports does not involve the packet forwarding, in a logical level, the packet forwarding is not performed, that is, two interconnected ports are regarded as one port, and a detection path involved in the packet forwarding process is:

port 001 (port 0A) -port 104 (port 1B) -port 101 (port 1A) -port 202 (port 2B) -port 203 (port 2A) -port 302 (port 3B) -port 301 (port 3A) -port 004 (port 0B).

And acquiring corresponding port identification information based on the detection path of the message forwarding process, wherein each port identification information can represent a forwarding segment set for the original connection test message, and the forwarding segments jointly form a corresponding forwarding stack. And originally connecting the test message, and transmitting the test message in the chip set to be tested by sequentially obtaining each forwarding segment. Since the initial time of message forwarding is when the original connection test message reaches the port 001, the port identification information corresponding to each forwarding port after the initial is set, that is, the port identification information from the port 104 to the port 004, so that the original connection test message can sequentially pass through each port to be tested on the message detection path, thereby reducing the calculation load. Meanwhile, the obtained port identification information is stored in the associated area of the original connection test packet in a stacking manner, as shown in table 5 below, where the order of each port identification information is consistent with the transmission order of the original connection test packet among the ports to be tested in the packet detection path.

TABLE 5

1	104
		2	101
3	202
		4	203
5	302
		6	301
7	004
		8	0

In table 5, each PORT identification information may also be understood as each corresponding forwarding information required when the original connectivity test packet is forwarded, for example, the PORT identification information DEV _ PORT (104) indicates that the original connectivity test packet needs to be transferred to the PORT 104, and similarly, each PORT identification information in table 5 indicates a meaning as shown in table 6 below:

TABLE 6

Stack order	Port identification information	Means for indicating
			1	104	It is necessary to forward the message to port 104
2	101	It is desirable to allow the message to come back from port 101
			3	202	It is necessary to forward the message to port 202
4	203	It is necessary to make the message come back from the port 203
			5	302	It is necessary to forward the message to port 302
6	301	It is desirable to allow the message to come back from port 301
			7	004	The message needs to be forwarded to port 004
8	0	Sending messages without message return

Optionally, the original connectivity test packet is encapsulated through different protocol formats or a self-defined protocol format, for example, as shown in fig. 5, a 9-bit DEV _ PORT is used to represent PORT identification information, a 7-bit padding field is added to align bytes of the protocol field of the original connectivity test packet, and after encapsulation, the PORT identification information is stored in the original connectivity test packet in a stack manner according to an arrangement sequence of the PORTs to be tested in the packet detection path.

When the above steps are completed, the original test message is generated on the detection device and sent to the chipset to be tested, and the generation time t1 at this time is recorded.

Step 203: inputting an original communication test message into a chipset to be tested, transmitting the original communication test message among the ports to be tested according to the arrangement sequence of the ports to be tested in a message detection path through the chipset to be tested until the original communication test message output by the chipset to be tested is received, and recording the receiving time of the original communication test message, wherein a tracking message which is fed back by the chipset to be tested and aims at one port to be tested is received every time the original communication test message passes through one port to be tested.

Specifically, each time the original test message passes through one PORT to be tested, the programmable chip acquires PORT identification information carried by the original connection test message in a pop-up manner, and packages the original connection test message based on a preset message format, in this embodiment, a format recognizable by the heterogeneous chip 1, the heterogeneous chip 2, and the heterogeneous chip 3, such as a DST _ PORT format, is adopted for packaging. And then, the programmable chip and each heterogeneous chip transmit the original connection test message between the ports to be tested according to the set identification information of each port after packaging.

In order to facilitate understanding of the process of transmitting the original connection test message by the chipset to be tested, a specific situation that the original connection test message is transmitted between each port to be tested in the chipset to be tested is given as follows:

after an original connection test packet is generated by a detection device, and is sent from an exit network end of the detection device, that is, a PORT 0B, the PORT 0B is interconnected with a PORT 101 of pipeline0, and does not involve packet forwarding, so that the original connection test packet directly reaches a physical PORT 001 on the pipeline0, and then, the programmable chip obtains PORT identification information, that is, DEV _ PORT (104), in a pop-up manner, as shown in table 7:

TABLE 7

1

104

As can be seen from table 6 above, the port identification information can mean: the message needs to be forwarded to port 104. According to the port identification information, the original connection test message is sent from the port 001 on the pipeline0 to the port 104 on the pipeline 1. Meanwhile, a Trace message S1 is generated based on the original connection test message, for example, in this embodiment, the original connection test message in the Ping format is packaged into a Trace message in a Trace format as Payload, where the package of the Trace message is shown in fig. 6. The programmable chip generates corresponding response information based on the connection state between the port 001 and the port 104, wherein the response information at least includes time information for generating the trace message S1. The response message is placed in the associated area of the generated trace message S1 and sent to the detection device, so that the detection device can determine whether the port 001 and the port 104 have failed according to the received trace message S1. Optionally, the generated trace message may also be sent to another observation device interconnected with the detection device. For example, in the embodiment of the present application, the generated trace message S1 is sent to the observation apparatus shown in fig. 7.

Next, when the original connectivity test packet reaches the physical PORT 104 on pipeline1, the programmable chip obtains a PORT identifier, i.e. DEV _ PORT (101), again in a pop manner, as shown in table 8:

TABLE 8

2

101

As can be seen from table 6, the port identification information indicates: a message needs to be returned from port 101. Because the message format of the popped PORT identification information DEV _ PORT (101) cannot be directly identified by the heterogeneous chip 1, the programmable chip encapsulates the original connection test message based on the message format that can be identified by the heterogeneous chip 1. Optionally, the popped port identification information is encapsulated. For example, referring to table 4, in the embodiment of the present application, the popped PORT identifier, that is, DEV _ PORT (101), is correspondingly encapsulated as DST _ PORT (1A), and the PORT identifier DST _ PORT (1A) is encapsulated to a corresponding field position of a packet format that can be recognized by the heterogeneous chip 1, and then is sent to the heterogeneous chip 1. Meanwhile, the programmable chip generates a trace message S2 based on the original connection test message, and generates corresponding response information m2 according to the connection condition from the port 104 to the port 1B, and sends the trace message S2 carrying the response information m2 to the specified observation device.

When the original connection test message reaches the heterogeneous chip 1 through the PORT 1B of the heterogeneous chip 1 interconnected with the PORT 101, the heterogeneous chip 1 identifies the DST _ PORT (1A) from the original connection test message. Specifically, the heterogeneous chip 1 identifies a certain key field carried in the encapsulated original connection test packet, where the key field may be PORT identification information used for representing a PORT in the heterogeneous chip 1, such as DST _ PORT (1A), or may be another field (such as a Hash value). According to the identified field, the heterogeneous chip 1 considers that the original connection test message needs to be sent from the PORT 1A, specifically, the original connection test message is sent from the PORT 1A to the PORT 101, that is, the PORT 101 interconnected by the PORT 1A receives the returned original connection test message, which is consistent with the information represented by the DEV _ PORT (101). In this process, the heterogeneous chip 1 only needs to forward the original connection test message, and normal service operation on the heterogeneous chip 1 is not affected. When the original connection test message is sent from the port 1A of the heterogeneous chip 1, the programmable chip generates a trace message S3 according to the received original connection test message, and simultaneously generates response information m3, at this time, the response information m3 corresponds to the connection condition between the port 1A of the heterogeneous chip 1 and the port 101 of the programmable chip, and finally, the trace message S3 carrying the response information m3 is sent to the observation device.

When the original connection test packet returns to the programmable chip from the PORT 101, the programmable chip obtains PORT identification information, i.e. DEV _ PORT (202), in a pop manner again, as shown in the following table 9:

TABLE 9

3

202

As can be seen from table 6 above, the port identification information indicates: the message needs to be forwarded to port 202. Then according to the port identification information, the original connection test packet is sent from the port 101 on pipeline1 to the port 202 on pipeline 2. Meanwhile, the programmable chip generates a trace message S4 carrying response information m4 corresponding to the ports 101 to 202, and sends the trace message S4 to the detection device or the observation device.

Next, when the original connectivity test packet reaches the PORT 202 on pipeline2, the programmable chip obtains a PORT identification information, i.e. DEV _ PORT (203), again in a pop manner, as shown in table 10:

watch 10

4

203

As can be seen from table 6, the port identification information indicates: the message needs to be returned from the port 203, and at this time, the popped message format cannot be directly identified by the heterogeneous chip 2, so that the programmable chip encapsulates the original test message based on the message format that can be identified by the heterogeneous chip 2. Optionally, as shown in table 4, the PORT identification information of the popped DEV _ PORT (203) is correspondingly encapsulated as a DST _ PORT (2A), and the PORT identification information DST _ PORT (2A) is encapsulated to a corresponding field position of a packet format recognizable by the heterogeneous chip 2, and then is sent to the heterogeneous chip 2. Meanwhile, the programmable chip generates a trace message S5 carrying response information m5 from the corresponding port 202 to the port 2B, and sends the trace message S5 to the detection device or the observation device.

When the original connection test message reaches the heterogeneous chip 2 through the port 2B of the heterogeneous chip 2 interconnected with the port 202, the heterogeneous chip 2 recognizes forwarding information corresponding to the heterogeneous chip 2 from the packaged original connection test message. Specifically, the heterogeneous chip 2 identifies a certain key field, that is, forwarding information, carried in the encapsulated original connectivity test packet, where the key field may be PORT identification information used by the heterogeneous chip 2 to represent a PORT, for example, a corresponding DST _ PORT (2A), or may be another field (such as a Hash value). According to the forwarding information, the heterogeneous chip 2 considers that the original connection test packet needs to be sent from the PORT 2A, and the PORT 203 interconnected with the heterogeneous chip can receive the returned original connection test packet, which is consistent with the information represented by the DEV _ PORT (203). In this process, the heterogeneous chip 2 only needs to forward the original connection test message, and normal service operation on the heterogeneous chip 2 is not affected. Meanwhile, the programmable chip generates a trace message S6 carrying response information m6 from the port 2A in the corresponding heterogeneous chip 2 to the port 203 in the programmable chip, and sends the trace message S6 to the detection device or the observation device.

When the original connection test packet returns to the programmable chip from the PORT 203, the programmable chip obtains PORT identification information, i.e. DEV _ PORT (302), in a pop manner again, as shown in the following table 11:

TABLE 11

5

302

As can be seen from table 6 above, the port identification information indicates: the message needs to be forwarded to port 302. The original connectivity test packet is sent from port 302 on pipeline3 according to the port identification information. Meanwhile, the programmable chip generates a trace message S7 carrying response information m7 from the corresponding port 203 to the port 302, and sends the trace message S7 to the detection device or the observation device.

Next, when the original connectivity test packet reaches the PORT 302 on pipeline3, the programmable chip obtains a PORT identification information, i.e. DEV _ PORT (301), again in a pop manner, as shown in table 12:

TABLE 12

6

301

As can be seen from table 6, the port identification information indicates: the message needs to be returned from the port 301, and at this time, the popped message format cannot be directly identified by the heterogeneous chip 3, so that the programmable chip encapsulates the original test message based on the message format that can be identified by the heterogeneous chip 3. Optionally, as shown in table 4, the PORT identification information of the popped DEV _ PORT (301) is correspondingly encapsulated as a DST _ PORT (3A), and the PORT identification information DST _ PORT (3A) is encapsulated to a corresponding field position of a packet format recognizable by the heterogeneous chip 3, and then is sent to the heterogeneous chip 3. Meanwhile, the programmable chip generates a trace message S8 according to the received original connection test message, and generates response information m8, at this time, the response information m8 corresponds to the connection condition between the port 302 and the port 3B, and finally, the trace message S8 carrying the response information m8 is sent to the detection device or the observation device.

When the original connection test message reaches the heterogeneous chip 3 through the port 3B of the heterogeneous chip 3 interconnected with the port 302, the heterogeneous chip 3 recognizes forwarding information corresponding to the heterogeneous chip 3 from the packaged original connection test message. Specifically, the heterogeneous chip 2 identifies a certain key field, that is, forwarding information, carried in the encapsulated original connectivity test packet, where the key field may be PORT identification information used for representing a PORT in the heterogeneous chip 3, for example, a corresponding DST _ PORT (3A), or may be another field (for example, a Hash value). According to the forwarding information, the heterogeneous chip 3 considers that the original connection test packet needs to be sent from the PORT 3A, and the PORT 301 interconnected with the heterogeneous chip can receive the returned original connection test packet, which is consistent with the information represented by the DEV _ PORT (301). In this process, the heterogeneous chip 3 only needs to forward the original connection test message according to the identified forwarding information, and normal service operation on the heterogeneous chip 3 is not affected. Meanwhile, the programmable chip generates a trace message S9 according to the received original connection test message, and simultaneously generates response information m9, at this time, the response information m9 corresponds to the connection condition between the port 3A and the port 301, and finally, the trace message S9 carrying the response information m9 is sent to the detection device or the observation device.

When the original connection test packet returns to the programmable chip from the PORT 301, the programmable chip obtains PORT identification information, i.e. DEV _ PORT (004) PORT identification information, in a pop-up manner again, as shown in table 13 below:

watch 13

7

004

As can be seen from table 6 above, the port identification information indicates: the message needs to be forwarded to port 004. Then, according to the port identification information, the original connection test message is forwarded. Meanwhile, the programmable chip generates a trace message S10 according to the received original connection test message, generates response information m10 corresponding to the ports 301 to 004, and sends the trace message S10 carrying the response information m10 to the detection device or the observation device.

Finally, when the original connection test packet reaches the PORT 004, the programmable chip obtains PORT identification information, i.e. DEV _ PORT (0) PORT identification information, in a pop manner again, as shown in the following table 14:

TABLE 14

8

0

As can be seen from table 6 above, the port identification information indicates: the message is sent without the need for a message return. Then according to the port identification information, the original connection test message is sent back to the detection device or sent to the observation device.

It should be noted that the device receiving the original connection test packet sent by the chipset to be tested should be the same as the above mentioned device receiving each trace packet.

As can be seen from the above description, in the embodiment of the present application, the programmable chip and each heterogeneous chip forming the chipset to be tested respectively execute different operations, so that the original connection test packet is transmitted between each port to be tested. In order to avoid affecting other services of each heterogeneous chip, each heterogeneous chip only provides the functions of forwarding messages and feeding back port communication conditions to the programmable chip, and the programmable chip packages the original communication test messages in a message format recognizable by the heterogeneous chip while forwarding the messages, and generates corresponding tracking messages to be fed back to the inspection device or the observation device. By the method, the on-line detection of the connectivity of the message channel is realized, so that the time and various costs required by detection are effectively reduced.

When the original connection test message reaches the port 0B, the receiving time t2 of the original connection test message at this time is recorded.

Optionally, after the observation device interconnected and intercommunicated with the detection device receives the original connectivity test packet output by the chipset to be tested from the port 004, the reception time t2 of the original connectivity test packet at this time is recorded.

Step 204: and calculating corresponding time difference according to the generation time and the receiving time of the original connected test message, and combining each received tracking message to obtain a corresponding detection result.

Specifically, referring to fig. 8, the following steps are performed:

step 2041: and calculating the corresponding time difference according to the generation time and the receiving time of the original connection test message.

For example, in the embodiment of the present application, a corresponding time difference Δ t is calculated according to the generation time t1 and the receiving time t2 of the original connection test packet, and is represented as Δ t-t 2-t 1.

Step 2042: is the time difference confirmed to be within a preset time difference threshold range? If so, go to step 2043, otherwise, go to step 2044.

Step 2043: determining the detection result as follows: and the message detection paths are communicated.

For example, in the embodiment of the present application, the preset time difference threshold is: 100ms, and if the calculated time difference Δ t is 90ms, determining that the detection result is: and communicating the message paths.

Step 2044: according to the received tracking messages, determining a target fault port, and determining that the detection result is as follows: the message communication path fails, and the failure port is a target failure port.

For example, if the time difference calculated in the embodiment of the present application is 200ms and is outside the preset time difference threshold (100ms), the target failure port is determined according to each received trace packet.

Specifically, the following steps can be executed to judge the target failure interface:

For example, if the trace message S1, the trace message S2, and the trace message S3 are received, and the trace message S4 and the following trace messages are not received, the target failed port is determined to be the port corresponding to the trace message S4, i.e., the port 101 and the port 202.

If the trace messages are received from S1 to S8, the fault port is further judged according to the time difference between the generation time and the receiving time of each trace message.

Referring to fig. 9, the embodiment of the present application provides a second method for detecting connectivity between chips on a chipset to be tested, including:

step 901: the chip set to be tested receives an original communication test message sent by the test equipment, wherein the original communication test message at least carries port identification information of each appointed port to be tested, which is preset aiming at a message detection path.

Step 902: and the chipset to be tested transmits the original communication test message among the ports to be tested according to the arrangement sequence of the ports to be tested in the message detection path, wherein each time the chipset passes through one port to be tested, a tracking message aiming at one port to be tested is fed back to the test equipment.

Step 903: the chip set to be tested outputs an original connection test message to the test equipment, so that the test equipment calculates corresponding time difference based on the generation time and the receiving time of the original connection test message, and obtains corresponding detection results by combining each received tracking message.

The method processes a chipset to be tested, wherein the chipset to be tested comprises: the system comprises a plurality of chips to be tested, a plurality of test modules and a plurality of test modules, wherein the chips to be tested further comprise a programmable chip and a plurality of heterogeneous chips; the port to be tested for message connectivity detection correspondingly comprises: the ports on the programmable chip and the ports corresponding to the heterogeneous chips are consistent with the ports in tables 1 and 2 in the embodiment of the application.

The chipset to be tested transfers the original connectivity test packet among the ports to be tested according to the arrangement sequence of the ports to be tested in the packet detection path shown in fig. 4, where the programmable chip and each heterogeneous chip respectively perform their corresponding operations, which specifically includes:

and the programmable chip correspondingly forwards and encapsulates the original communication test message based on the identification information of each port, which is carried in the original communication test message and is set aiming at the programmable chip, wherein the corresponding tracking message is fed back to the test equipment every time the test equipment passes through one port to be tested.

Specifically, the programmable chip obtains port identification information set for the programmable chip from the received original connection test message in a pop-up manner, and encapsulates the original connection test message based on a preset message format; meanwhile, the programmable chip transmits the packaged original connection test message between every two ports to be tested in the programmable chip based on the port identification information set for the programmable chip, and outputs the original connection test message to at least one heterogeneous chip; after the packaged original connection test message passes through each port to be tested, the programmable chip generates corresponding fault reporting information according to the connection condition of the ports to be tested in the programmable chip, and generates a corresponding tracking message according to the original connection test message; and finally, feeding back a tracking message carrying fault reporting information to the test equipment, optionally the observation equipment.

And the heterogeneous chips are used for generating corresponding tracking messages according to the original communication test messages respectively forwarded by the heterogeneous chips and feeding back the tracking messages to the test equipment based on the obtained forwarding information which can be respectively identified by the heterogeneous chips.

Specifically, each heterogeneous chip respectively executes the following operations:

obtaining forwarding information which can be identified by the heterogeneous chip from the received packaged original connection test message;

As can be seen from the above description, in the embodiment of the present application, the programmable chip and the multiple heterogeneous chips that form the chipset to be tested respectively execute different operations, so that the original connection test packet is transmitted between the ports to be tested in the chipset to be tested. The programmable chip completes the forwarding of the original connection test message and simultaneously provides the functions of packaging the message and feeding back a tracking message based on the execution of the steps, and correspondingly, the heterogeneous chip realizes the forwarding of the original connection test message based on the operation, and other services on the heterogeneous chip are not influenced during the operation, so that the on-line detection of the message channel connectivity can be realized, and the time and various costs required by the detection are effectively reduced.

Referring to fig. 10, a first on-line detection apparatus (e.g., a testing device) for inter-chip connectivity provided in the embodiment of the present application includes an obtaining module 1001, a generating module 1002, a communication module 1003, and a calculating module 1004, where:

the acquisition module 1001: the method is used for obtaining configuration information corresponding to a message detection path preset by a chipset to be tested aiming at the chipset to be tested, wherein the configuration information at least comprises: and port identification information of each appointed port to be tested in the message detection path.

The generation module 1002: and the method is used for generating original connection test messages carrying the identification information of each port and recording the generation time of the original connection test messages.

The communication module 1003: the system comprises a test path, a test chip set and a communication test message sending and receiving module, wherein the test path is used for sending an original communication test message to the test chip set to be tested, the original communication test message is transmitted among the test ports to be tested according to the arrangement sequence of the test ports in the message detection path through the test chip set to be tested until the original communication test message output by the test chip set to be tested is received, and the receiving time of the original communication test message is recorded, wherein each time the original communication test message passes through one test port to be tested, a tracking message which is fed back by the test chip set to be tested and aims at one test port to be tested is received.

The calculation module 1004: and the detection module is used for calculating corresponding time difference according to the generation time and the receiving time of the original connected test message and obtaining corresponding detection results by combining each received tracking message.

In an optional embodiment, when generating an original connectivity test packet carrying identification information of each port, the generating module 1002 is specifically configured to:

In an optional embodiment, when the corresponding time difference is calculated according to the generation time and the receiving time of the original connection test packet, and a corresponding detection result is obtained by combining each received trace packet, the calculating module 1004 is specifically configured to:

In an alternative embodiment, when determining a target failure port according to each received trace packet, the calculating module 1004 is specifically configured to:

if the number of the tracking messages is smaller than that of the ports to be tested, determining the subsequent ports to be tested of the ports to be tested corresponding to the latest received tracking messages as target fault ports according to the arrangement sequence of the ports to be tested in the message detection path;

acquiring time information for receiving the tracking message aiming at the tracking message, and acquiring a time difference corresponding to the tracking message according to response information carried by the tracking message, wherein the response information at least comprises the time information for generating the tracking message;

if the time difference corresponding to the tracking message is greater than a preset time difference threshold value, determining the port to be tested corresponding to the tracking message as a target fault port according to the arrangement sequence of the ports to be tested in the message detection path;

Referring to fig. 11, the second apparatus for detecting connectivity between chips (e.g., a chipset to be tested) provided in this embodiment of the present application includes a receiving module 1101, a transmitting module 1102, and an output module 1103, where:

the receiving module 1101 is configured to receive an original connectivity test message sent by a test device, where the original connectivity test message at least carries port identification information of each specified port to be tested, where the port identification information is preset for a message detection path.

The transmitting module 1102 is configured to transmit the original connectivity test packet among the ports to be tested according to the sequence of the ports to be tested in the packet detection path, where a trace packet for one port to be tested is fed back to the test equipment every time the trace packet passes through one port to be tested.

The output module 1103 is configured to output the original connected test packet to the test device, so that the test device calculates a corresponding time difference based on the generation time and the receiving time of the original connected test packet, and obtains a corresponding detection result by combining each received trace packet.

when the chipset to be tested transmits the original connectivity test packet among the ports to be tested according to the sequence of the ports to be tested in the packet detection path, the transmitting module 1102 is specifically configured to:

And performing corresponding forwarding operation on the original connection test message based on the obtained forwarding information which can be respectively identified by the heterogeneous chips through the heterogeneous chips, so that the programmable chip can generate corresponding tracking messages according to the original connection test messages respectively forwarded by the heterogeneous chips and feed the tracking messages back to the test equipment.

In an optional embodiment, when, by using the one programmable chip, performing corresponding forwarding and encapsulation operations on the original connectivity test packet based on the port identification information, which is carried in the original connectivity test packet and is set for the programmable chip, the transmission module 1102 is specifically configured to:

In an optional embodiment, when, through the plurality of heterogeneous chips, based on obtaining forwarding information that the plurality of heterogeneous chips can respectively recognize, corresponding forwarding operation is performed on the original connectivity test packet, the transmitting module 1102 is specifically configured to:

Based on the same inventive concept as the above application embodiments, the application embodiments provide an electronic device, which is adapted to a test device and a chipset to be tested and can be used for on-line detection of connectivity between chips. In one embodiment, the electronic device may be a server, a terminal device, or other electronic device. In this embodiment, the electronic device may be configured as shown in fig. 12, and include a memory 1201, a communication interface 1203, and one or more processors 1202.

A memory 1201 for storing computer programs executed by the processor 1202. The memory 1201 may mainly include a storage program area and a storage data area, where the storage program area may store an operating system, a program required for running an instant messaging function, and the like; the storage data area can store various instant messaging information, operation instruction sets and the like.

Memory 1201 may be a volatile memory (volatile memory), such as a random-access memory (RAM); the memory 1201 may also be a non-volatile memory (non-volatile memory) such as, but not limited to, a read-only memory (rom), a flash memory (flash memory), a hard disk (HDD) or a solid-state drive (SSD), or any other medium which can be used to carry or store desired program code in the form of instructions or data structures and which can be accessed by a computer. The memory 1201 may be a combination of the above memories.

The processor 1202 may include one or more Central Processing Units (CPUs), a digital Processing Unit, and the like. A processor 1202 for implementing the image search method described above when calling a computer program stored in the memory 1201.

The communication interface 1203 is used for communication with the terminal device and other servers.

In the embodiment of the present application, the specific connection medium between the memory 1201, the communication interface 1203 and the processor 1202 is not limited. In the embodiment of the present application, the memory 1201 and the processor 1202 are connected by the bus 1204 in fig. 12, the bus 1204 is represented by a thick line in fig. 12, and the connection manner between other components is only schematically illustrated and is not limited. The bus 1204 may be divided into an address bus, a data bus, a control bus, and the like. For ease of illustration, only one thick line is shown in FIG. 12, but this is not intended to represent only one bus or type of bus.

Based on the same inventive concept as the embodiments of the above application, according to an aspect of the present application, there is provided a computer program product or a computer program comprising computer instructions stored in a computer readable storage medium. A processor of the computer device reads the computer instructions from the computer-readable storage medium, and executes the computer instructions, so that the computer device executes the steps of the first inter-chip connectivity online detection method in the above embodiments; alternatively, the processor of the computer device reads the computer instructions from the computer-readable storage medium, so that the processor executes the steps of the second inter-chip connectivity online detection method. The program product may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples (a non-exhaustive list) of the readable storage medium include: an electrical connection having one or more wires, a portable disk, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.

Claims

1. An on-line detection method for connectivity between chips is characterized by comprising the following steps:

aiming at a chipset to be tested, obtaining configuration information corresponding to a message detection path preset by the chipset to be tested, wherein the configuration information at least comprises: port identification information of each appointed port to be tested in the message detection path;

generating original connection test messages carrying the port identification information, and recording the generation time of the original connection test messages;

inputting the original communication test message into the chipset to be tested, transmitting the original communication test message among the ports to be tested according to the arrangement sequence of the ports to be tested in the message detection path through the chipset to be tested until the original communication test message output by the chipset to be tested is received, and recording the receiving time of the original communication test message, wherein each time the original communication test message passes through one port to be tested, a tracking message which is fed back by the chipset to be tested and aims at the port to be tested is received;

and calculating corresponding time difference according to the generation time and the receiving time of the original connection test message, and combining each received tracking message to obtain a corresponding detection result.

2. The method of claim 1, wherein generating an original connectivity test packet carrying the port identification information comprises:

and generating the original communication test message, acquiring the identification information of each port, and storing the identification information in an associated area of the original communication test message in a stacking mode according to the arrangement sequence of each port to be tested in the message detection path.

3. The method according to claim 1 or 2, wherein calculating a corresponding time difference according to the generation time and the receiving time of the original connection test packet, and obtaining a corresponding detection result by combining each received trace packet, comprises:

calculating corresponding time difference according to the generation time and the receiving time of the original connection test message;

when the time difference is within a preset time difference threshold value range, determining that the detection result is as follows: the message detection paths are communicated;

when the time difference is not within a preset time difference threshold value range, determining a target fault port according to each received tracking message, and determining that a detection result is as follows: the message communication path is in fault, and the fault port is the target fault port.

4. The method of claim 3, wherein determining a target failed port based on each received trace packet comprises:

5. An on-line detection method for connectivity between chips is characterized by comprising the following steps:

the method comprises the steps that a chip set to be tested receives an original communication test message sent by test equipment, wherein the original communication test message at least carries port identification information of each appointed port to be tested, which is preset aiming at a message detection path;

the chipset to be tested transmits the original communication test message among the ports to be tested according to the arrangement sequence of the ports to be tested in the message detection path, wherein each time the chipset to be tested passes through one port to be tested, a tracking message aiming at the port to be tested is fed back to the test equipment;

6. The method of claim 5, wherein the chipset under test comprises: the system comprises a plurality of chips to be tested, a plurality of test control units and a plurality of test control units, wherein the chips to be tested comprise a programmable chip and a plurality of heterogeneous chips; the port to be tested includes: the to-be-tested inlet net end and the to-be-tested outlet net end correspond to the to-be-tested chips respectively;

the transmitting, by the chipset to be tested, the original connectivity test packet among the ports to be tested according to the sequence of the ports to be tested in the packet detection path includes:

performing, by the programmable chip, corresponding forwarding and encapsulation operations on the original connected test packet based on port identification information, which is set for the programmable chip and carried in the original connected test packet, wherein each time the original connected test packet passes through one port to be tested, a corresponding trace packet is fed back to the test equipment;

7. The method of claim 6, wherein performing, by the one programmable chip, corresponding forwarding and encapsulation operations on the original connectivity test packet based on port identification information, which is set for the programmable chip and is carried in the original connectivity test packet, wherein feeding back a corresponding trace packet to the test device every time a port to be tested passes through includes:

acquiring port identification information set for the programmable chip from the received original connection test message by the programmable chip in a pop-up mode, and packaging the original connection test message based on a preset message format, wherein the packaged original connection message carries forwarding information respectively generated for the heterogeneous chips;

transmitting the packaged original connection test message between every two ports to be tested in the programmable chip based on the port identification information set for the programmable chip through the programmable chip, and outputting the original connection test message to at least one heterogeneous chip;

8. The method of claim 6, wherein performing, by the plurality of heterogeneous chips, corresponding forwarding operations on the original connectivity test packet based on obtaining forwarding information that can be respectively identified by the plurality of heterogeneous chips, comprises:

based on the forwarding information, transmitting the packaged original connection test message between every two ports to be tested in the heterogeneous chip, and outputting the original connection test message to the programmable chip, so that the programmable chip can generate a corresponding trace message according to the packaged original connection test message output by the heterogeneous chip, and feed the trace message back to the test equipment.

9. An on-line detection device for connectivity between chips, comprising:

the acquisition module is used for acquiring configuration information corresponding to a message detection path preset by a chipset to be tested aiming at the chipset to be tested, wherein the configuration information at least comprises: port identification information of each appointed port to be tested in the message detection path;

the generating module is used for generating original connection test messages carrying the identification information of each port and recording the generating time of the original connection test messages;

the communication module is used for inputting an original communication test message into a chip set to be tested, transmitting the original communication test message among the ports to be tested according to the arrangement sequence of the ports to be tested in a message detection path through the chip set to be tested until the original communication test message output by the chip set to be tested is received, and recording the receiving time of the original communication test message, wherein each time the original communication test message passes through one port to be tested, a tracking message which is fed back by the chip set to be tested and aims at one port to be tested is received;

10. An on-line detection device for connectivity between chips, comprising:

the device comprises a receiving module, a sending module and a receiving module, wherein the receiving module is used for receiving an original communication test message sent by test equipment, and the original communication test message at least carries port identification information of each specified port to be tested, which is preset aiming at a message detection path;

the transmission module is used for transmitting the original communication test message among the ports to be tested according to the arrangement sequence of the ports to be tested in the message detection path, wherein each time the original communication test message passes through one port to be tested, a tracking message aiming at one port to be tested is fed back to the test equipment;

11. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the steps of the method according to any of claims 1-4 when executing the computer program or causes the processor to perform the steps of the method according to any of claims 5-8.

12. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 4, or causes the processor to carry out the steps of the method according to any one of claims 5 to 8.