CN114124199B - Anti-interference channel demodulation accelerator suitable for satellite baseband processing chip - Google Patents
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Abstract
The invention discloses an anti-interference channel demodulation accelerator suitable for a satellite baseband processing chip, which consists of a data processing module, an algorithm processing module, a control information register, a data information register and the like. The input baseband sampling data is cached in a data information register by an accelerator integrated controller, each parameter is configured by a control information register, a data processing module completes the functions of parameter processing, channel identification, data formatting and the like, an algorithm processing module completes the functions of frequency word generation, unique word equalization, data word demodulation, timing word calculation and the like and signal operation required in the process, and a final result is written back to the data processing module. The demodulation accelerator algorithm is flexible in configuration, efficient in resource utilization, capable of rapidly completing an anti-interference channel signal demodulation processing algorithm, particularly suitable for designing and using related baseband processing chips, and is particularly optimized for reverse carrier signal demodulation of a discrete multi-subcarrier transmission system satellite communication system.
Description
Technical Field
The invention relates to an anti-interference channel demodulation accelerator suitable for a satellite baseband processing chip, in particular to a satellite communication system baseband processing chip which is suitable for a satellite communication system adopting a discrete multi-subcarrier anti-interference transmission system.
Background
The satellite communication transmission distance is long, the signal strength is poor, the signal to noise ratio is low, reliable transmission is realized, and reliable synchronization, demodulation, decoding and other processing processes are relied on in a physical layer, wherein demodulation performance has a large influence on the error code performance and stability of a communication system. Particularly, in the case of poor channel conditions or the existence of non-cooperative interference signals in the transmission process, a communication transmission system with special design and an effective demodulation device designed for the system are required to realize reliable communication transmission with interference resistance.
The satellite communication baseband processing chip can be divided into an on-board processing chip and a ground user terminal baseband processing chip, and has the main functions of synchronizing, demodulating, decoding and the like of a digital baseband for forward and reverse signals of satellite communication received on the satellite or on the ground. The digital signal processor is mainly used for completing the baseband signal processing work of the physical layer, the general digital signal processor and the general core processor cannot be completely qualified in certain cases because of large satellite communication baseband processing operand and limited operation time, and the FPGA field programmable gate array can be used for developing an accelerator prototype, but is limited to the problems of volume, power consumption, stability consistency and the like.
The hardware accelerator has strong pertinence and a certain special characteristic in the application range. The physical layer differs significantly for different satellite communication protocols, so different accelerators are required to match the various satellite communication waveforms. At present, a plurality of communication accelerators are generally arranged in a multimode chip, and even if the multimode chip is uniformly designed as a baseband accelerator, the multimode chip also comprises special acceleration units corresponding to protocol standards one by one. For the same protocol standard, the hardware accelerator has different implementation schemes, and the design targets and emphasis points of the different implementation schemes are different.
For the land cellular network communication system, a plurality of baseband chips and accelerators have been developed in the industry, and for satellite communication systems, especially for new generation satellite communication systems which are independently designed in China, because of fewer users and newer fields, special system chips and accelerators are rarely developed at present. For the new generation of high-orbit/low-orbit satellite anti-interference communication system in China, a baseband accelerator or a baseband chip capable of processing discrete multi-subcarrier anti-interference channel demodulation tasks in real time with high performance is lacking at present.
Disclosure of Invention
The invention aims to solve the technical problem of providing an anti-interference channel demodulation accelerator applicable to satellite load and terminal baseband aiming at the next generation of anti-interference satellite mobile communication system based on discrete multiple subcarriers, and mainly completes the processes of frequency synchronization, timing synchronization, data demodulation and the like of a satellite communication receiver of the system.
The invention adopts the technical scheme that:
an anti-interference channel demodulation accelerator suitable for a satellite baseband processing chip comprises a data processing module 1, an algorithm processing module 2, a control information register 3 and a data information register 4;
the data processing module 1 is used for analyzing the multi-user control parameters sent by the control information register 3 under the control of the accelerator integrated controller, completing parameter processing, channel identification and data formatting operation, generating local data, performing access operation on the multi-user data information sent by the data information register 4, and outputting the user data extracted according to the need, the local generation data and the formatted control information to the algorithm processing module 2; the data word demodulation result and the timing word result output by the algorithm processing module 2 are buffered and output outwards under the control of the accelerator integrated controller;
the algorithm processing module 2 is used for performing anti-interference demodulation algorithm processing on the user data, the local generated data and the formatted control information sent by the data processing module 1, obtaining a data word demodulation result and a timing word result after processing, and outputting the processing result to the data processing module 1;
The control information register 3 comprises a plurality of register groups, and is used for storing multi-user control parameters input by the accelerator integrated controller or the processor according to a certain format for reading by the data processing module 1;
the data information register 4 is used for buffering the baseband sampling data sent from the outside under the control of the accelerator integrated controller, and dividing the baseband sampling data into multiple paths according to a multi-user data access rule and outputting the multiple paths of the baseband sampling data to the data processing module 1.
The algorithm processing module 2 comprises a frequency word processing unit 2A, a unique word operation unit 2B, a data word demodulation unit 2C and a timing word generation unit 2D;
the frequency word processing unit 2A is configured to receive the extracted user data and the locally generated data output by the data processing module 1, process the extracted user data and the locally generated data to generate de-modulated data and frequency word values, output the de-modulated data to the unique word operation unit 2B, and output the frequency word values to the unique word operation unit 2B and the data demodulation unit 2C respectively; the unique word operation unit 2B receives the de-modulated data and the frequency word value input by the frequency word processing unit 2A and processes the data to generate a frequency-offset-removed unique word and a channel word result, wherein the frequency-offset-removed unique word result is output to the timing word generation unit 2D, and the channel word result is output to the data word demodulation unit 2C; the data word demodulation unit 2C is configured to process the frequency word value, the channel word result, and the extracted user data output by the data processing module 1, obtain a data word demodulation result, and output the data word demodulation result back to the corresponding access unit of the data processing module 1; the timing word generating unit 2D is configured to process the unique word result after frequency offset removal and the control information output by the data processing module 1, obtain a timing word result, and output the timing word result back to the corresponding access unit of the data processing module 1.
The frequency word processing unit 2A includes a first complex multiplication unit 200, a first temporary register 201, a first FFT operation unit 202, a first strobe unit 203, a first square operation unit 204, a second square operation unit 205, a first accumulator unit 206, a first data register 207, a first comparator unit 208, a second strobe unit 209, a second accumulator unit 210, and a frequency word register 211;
the first complex multiplication unit 200 performs complex multiplication operation on the extracted user data output by the data processing module 1 and locally generated data, and the product results are output to the first temporary register 201 and the FFT operation unit 202, respectively; a first temporary register 201; outputting the result of the product to the unique word operation unit 2B; the FFT operation unit 202 performs a fast fourier transform operation on the data output from the first complex multiplication unit 200, and outputs the result to the first gating unit 203; in the frequency word processing, the first gating unit 203 gates the output result of the FFT operation unit 202, and correspondingly outputs the real part and the imaginary part of the complex signal to the first square operation unit 204 and the second square operation unit 205, respectively; the first accumulator unit 206 performs a data accumulation operation on the square results output from the first square operation unit 204 and the second square operation unit 205, and the accumulated sums are output to the first comparator unit 208 and the first data register 207, respectively; the first comparator unit 208 compares the output result of the first accumulator unit 206 with the registered data in the first data register 207, and the larger and larger index marks are stored back in the first data register 207; when all the sample processing output by the FFT operation unit 202 is completed, the second gating unit gates 209 to gate the result in the first data register 207 to the second accumulator unit 210; the second accumulator unit 210 performs a data accumulation operation on the processing results of each subcarrier and each frame of the current channel of the second gating unit 209, and outputs the accumulation result to the frequency word register 211; the frequency word register 211 outputs the frequency word numerical value to the unique word operation unit 2B and the data word demodulation unit 2C, respectively.
Wherein the unique word operation unit 2B includes a first counter unit 212, a first multiplication unit 213, a first lookup table unit 214, a second complex multiplication unit 215, a second data register 216, a first delay unit 217, an eighth accumulator unit 218, a second counter unit 219, a third strobe unit 220, a first shifter unit 221, and a third data register 222;
the first counter unit 212 sequentially increments the count from zero according to the unique word timing index; the first multiplication unit 213 multiplies the output value of the first counter unit 212 and the frequency word value output from the frequency word processing unit 2A, and the product result is used as an input of the first lookup table unit 214; the first lookup table unit 214 stores the natural logarithmic discrete index result of one trigonometric function period in advance in a fixed-point manner, takes the product output by the first multiplication unit 213 as an input index, obtains a complex result corresponding to the lookup table, and outputs the complex result to the second complex multiplication unit 215; the second complex multiplication unit 215 performs complex multiplication operation on the product result output from the first lookup table unit 214 and the frequency word processing unit 2A, and the complex multiplication result is stored in the second data register 216; one path of the output result of the second data register 216 is directly output to the eighth accumulator unit 218, and the other path is delayed by the first delay unit 217 and then output to the eighth accumulator unit 218, and the register value is sequentially output to the timing word generating unit 2D from zero according to the unique word timing index; the eighth accumulator unit 218 performs an accumulation operation on the direct output result of the second data register 216 and the structure delayed by the first delay unit 217, and outputs the accumulation result to the third gating unit 220; the second counter unit 219 counts the unique word position index value, and the output value is used as the strobe judgment threshold value of the third strobe unit 220; the third gating unit 220 gates the output value of the eighth accumulator unit 218 into a head section, a middle section and a tail section according to the gating judgment threshold, and outputs the result to the first shifter unit 221; the first shifter unit 221 performs a rightward shift process on the output result of the third gate unit 220, and the shift result is stored in the third data register 222 at the corresponding positions of the head section, the middle section, and the tail section; the third data register 222 sequentially outputs the registered values to the data word demodulation unit 2C from zero according to the data word timing index.
Wherein the data word demodulation unit 2C includes a coefficient register unit 223, a first subtractor unit 224, a second multiplication unit 225, a second delay unit 226, a third multiplication unit 227, a third accumulator unit 228, a third counter unit 229, a second shifter unit 230, a fourth accumulator unit 231, a fourth multiplication unit 232, a second lookup table unit 233, a third complex multiplication unit 234, and a fourth complex multiplication unit 235;
the coefficient values registered by the coefficient register 223 are output to the second multiplication unit 225, the first subtractor unit 224, and the fourth accumulator unit 231, respectively; the second multiplication unit 225 receives the registered value outputted from the zero by the unique word operation unit 2B according to the data word timing index, multiplies the registered value by the coefficient value registered by the coefficient register 223, and outputs the multiplied result to the third accumulator unit 228; the first subtractor 224 performs subtraction between the constant 1 and the coefficient value registered in the coefficient register 223, and outputs the result to the third multiplier 227; the second delayer unit 226 receives the register value outputted from the unique word operation unit 2B from zero according to the data word timing index, delays by one time unit, and outputs to the third multiplying unit 227; the third multiplication unit 227 multiplies the two input values, and outputs the product result to the third accumulator unit 228; the third accumulator unit 228 adds the output values of the second multiplication unit 225 and the third multiplication unit 227, and outputs the result to the fourth complex multiplication unit 235; the third counter unit 229 sequentially counts up from zero according to the data word timing index, and the count value is output to the second shifter unit 230; the second shifter unit 230 performs a shift-left process on the received data, and outputs the shift result to the fourth accumulator unit 231; the fourth accumulator unit 231 adds the input of the coefficient register 223 and the input value of the second shifter unit 230, and the result is output to the fourth multiplication unit 232; the fourth multiplication unit 232 multiplies the output value of the fourth accumulator unit 231 and the output frequency word value of the frequency word processing unit 2A, and outputs the result to the second lookup table unit 233 as a lookup table index value; the second lookup table unit 233 outputs a natural log discrete index lookup table result of one trigonometric function period stored in advance to the third complex multiplication unit 234 according to the index value; the third complex multiplication unit 234 performs complex multiplication on the output of the second lookup table unit 233 and the complex value of the received data word obtained from the data processing module 1, and the obtained complex result is output to the fourth complex multiplication unit 235; the fourth complex multiplication unit 235 performs complex multiplication on the two complex values input by the third accumulator unit 228 and the third complex multiplication unit 234 to obtain data word demodulation result data, and writes the data word demodulation result data into the corresponding access unit of the data processing module 1 through the interface.
The timing word generating unit 2D includes a fifth accumulator unit 237, a fourth counter unit 238, a fifth multiplier unit 239, a first truncator unit 240, a third lookup table unit 241, a fifth complex multiplier unit 242, a sixth accumulator unit 243, a fourth strobe unit 244, a third square operation unit 245, a fourth square operation unit 246, a seventh accumulator unit 247, a fourth data register 248, a second comparator unit 249, a fifth strobe unit 250, and a timing word register 251;
the fifth accumulator unit 237 performs subcarrier-by-subcarrier accumulation on the registered value output from the unique word operation unit 2B, and the accumulated result is output to the fifth complex multiplier unit 242; the fourth counter unit 238 sequentially counts up from zero, and outputs the count value to the fifth multiplier unit 239 as a timing position hypothesis value; while the fifth multiplier unit 239 receives the control information outputted from the control information register 3 through the data processing module 1; the fifth multiplier unit 239 multiplies the two input data, and outputs the result to the first truncator unit 240; the first truncator unit 240 truncates the product value output from the fifth multiplier unit 239, and outputs the result as an index value to the third lookup table unit 241; the third lookup table unit 241 outputs the natural logarithmic dispersion index lookup table result of one trigonometric function period stored in advance as the phase compensation value generated on each subcarrier by the timing position hypothesis value according to the index value, and outputs to the fifth complex multiplier unit 242; the fifth complex multiplier 242 performs complex multiplication on the two input data to obtain a compensation result of each subcarrier accumulated value, and outputs the compensation result to the sixth accumulator 243; the sixth accumulator unit 243 performs an accumulation operation on the compensation result of each subcarrier accumulated value, and the obtained accumulated value is gated by the fourth gating unit 244 and divided into a real part and an imaginary part to be respectively and correspondingly output to the third square operation unit 245 and the fourth square operation unit 246; the seventh accumulator unit 247 performs a data accumulation operation on the square results output from the third square operation unit 245 and the fourth square operation unit 246, and accumulates and outputs to the second comparator unit 249 and the fourth data register 248; the second comparator unit 249 compares the output result of the seventh accumulator unit 247 with the registered data in the fourth data register 248, the larger ones and the index marks of the larger ones are stored back in the fourth data register 248, and when all the timing position samples outputted from the fourth strobe unit 244 are processed, the fifth strobe unit 250 strobes and writes the output result of the fourth data register 248 into the timing word register 251 for the data processing module 1.
Compared with the background technology, the demodulation accelerator of the invention has the following advantages:
1. the demodulation accelerator mainly comprises 4 functional modules, including a data processing module, an algorithm processing module, a control information register and a data information register. The algorithm processing module can flexibly combine and gate the input data with different forms and resources by controlling the parameter control of the information register, the data processing module and the data information register to properly process the input data, adapt to different numbers of subcarriers, and simultaneously support demodulation of various waveform channels with continuous or discontinuous or continuous/discrete subcarrier combination.
2. The demodulation accelerator of the invention performs bottom optimization and cross-unit decomposition combination on the algorithm acceleration processing part, is not limited to each processing step limit of the principle mathematical formula, and can obtain the operation processing target result more quickly and more resource-saving.
3. The demodulation accelerator of the invention separates operation and data access, can be suitable for data with different depths and signal data mixed by different rates and different users, is not only limited to single-user demodulation of a terminal baseband, but also can be suitable for a multi-user data demodulation accelerator taking a station side as a low-orbit constellation satellite load.
4. The demodulation accelerator disclosed by the invention optimizes and balances the performance and resources, meets the low-power consumption requirement of a terminal or an on-board load, and simultaneously meets the requirement of high demodulation performance under the satellite communication anti-interference condition.
Drawings
Fig. 1 is a block diagram of a demodulation accelerator assembly of the present invention.
FIG. 2 is a block diagram of the algorithm processing module of the present invention.
Detailed Description
The invention is explained in more detail below with reference to the drawings.
As shown in fig. 1, an anti-interference channel demodulation accelerator suitable for a satellite baseband processing chip comprises a data processing module 1, an algorithm processing module 2, a control information register 3 and a data information register 4;
the data processing module 1 is used for analyzing the multi-user control parameters sent by the control information register 3 under the control of the accelerator integrated controller, completing parameter processing, channel identification and data formatting operation, generating local data, performing access operation on the multi-user data information sent by the data information register 4, and outputting the user data extracted according to the need, the local generation data and the formatted control information to the algorithm processing module 2; the data word demodulation result and the timing word result output by the algorithm processing module 2 are buffered and output outwards under the control of the accelerator integrated controller;
The algorithm processing module 2 is used for performing anti-interference demodulation algorithm processing on the user data, the local generated data and the formatted control information sent by the data processing module 1, obtaining a data word demodulation result and a timing word result after processing, and outputting the processing result to the data processing module 1;
the control information register 3 comprises a plurality of register groups, and is used for storing multi-user control parameters input by the accelerator integrated controller or the processor according to a certain format for reading by the data processing module 1;
the data information register 4 is used for buffering the baseband sampling data sent from the outside under the control of the accelerator integrated controller, and dividing the baseband sampling data into multiple paths according to a multi-user data access rule and outputting the multiple paths of the baseband sampling data to the data processing module 1.
As shown in fig. 2, the algorithm processing module 2 includes a frequency word processing unit 2A, a unique word operation unit 2B, a data word demodulation unit 2C, and a timing word generation unit 2D;
the frequency word processing unit 2A is configured to receive the extracted user data and the locally generated data output by the data processing module 1, process the extracted user data and the locally generated data to generate de-modulated data and frequency word values, output the de-modulated data to the unique word operation unit 2B, and output the frequency word values to the unique word operation unit 2B and the data demodulation unit 2C respectively; the unique word operation unit 2B receives the de-modulated data and the frequency word value input by the frequency word processing unit 2A and processes the data to generate a frequency-offset-removed unique word and a channel word result, wherein the frequency-offset-removed unique word result is output to the timing word generation unit 2D, and the channel word result is output to the data word demodulation unit 2C; the data word demodulation unit 2C is configured to process the frequency word value, the channel word result, and the extracted user data output by the data processing module 1, obtain a data word demodulation result, and output the data word demodulation result back to the corresponding access unit of the data processing module 1; the timing word generating unit 2D is configured to process the unique word result after frequency offset removal and the control information output by the data processing module 1, obtain a timing word result, and output the timing word result back to the corresponding access unit of the data processing module 1.
The frequency word processing unit 2A includes a first complex multiplication unit 200, a first temporary register 201, a first FFT operation unit 202, a first strobe unit 203, a first square operation unit 204, a second square operation unit 205, a first accumulator unit 206, a first data register 207, a first comparator unit 208, a second strobe unit 209, a second accumulator unit 210, and a frequency word register 211;
the first complex multiplication unit 200 performs complex multiplication operation on the extracted user data output by the data processing module 1 and locally generated data, and the product results are output to the first temporary register 201 and the FFT operation unit 202, respectively; a first temporary register 201; outputting the result of the product to the unique word operation unit 2B; the FFT operation unit 202 performs a fast fourier transform operation on the data output from the first complex multiplication unit 200, and outputs the result to the first gating unit 203; in the frequency word processing, the first gating unit 203 gates the output result of the FFT operation unit 202, and correspondingly outputs the real part and the imaginary part of the complex signal to the first square operation unit 204 and the second square operation unit 205, respectively; the first accumulator unit 206 performs a data accumulation operation on the square results output from the first square operation unit 204 and the second square operation unit 205, and the accumulated sums are output to the first comparator unit 208 and the first data register 207, respectively; the first comparator unit 208 compares the output result of the first accumulator unit 206 with the registered data in the first data register 207, and the larger and larger index marks are stored back in the first data register 207; when all the sample processing output by the FFT operation unit 202 is completed, the second gating unit gates 209 to gate the result in the first data register 207 to the second accumulator unit 210; the second accumulator unit 210 performs a data accumulation operation on the processing results of each subcarrier and each frame of the current channel of the second gating unit 209, and outputs the accumulation result to the frequency word register 211; the frequency word register 211 outputs the frequency word numerical value to the unique word operation unit 2B and the data word demodulation unit 2C, respectively.
Wherein the unique word operation unit 2B includes a first counter unit 212, a first multiplication unit 213, a first lookup table unit 214, a second complex multiplication unit 215, a second data register 216, a first delay unit 217, an eighth accumulator unit 218, a second counter unit 219, a third strobe unit 220, a first shifter unit 221, and a third data register 222;
the first counter unit 212 sequentially increments the count from zero according to the unique word timing index; the first multiplication unit 213 multiplies the output value of the first counter unit 212 and the frequency word value output from the frequency word processing unit 2A, and the product result is used as an input of the first lookup table unit 214; the first lookup table unit 214 stores the natural logarithmic discrete index result of one trigonometric function period in advance in a fixed-point manner, takes the product output by the first multiplication unit 213 as an input index, obtains a complex result corresponding to the lookup table, and outputs the complex result to the second complex multiplication unit 215; the second complex multiplication unit 215 performs complex multiplication operation on the product result output from the first lookup table unit 214 and the frequency word processing unit 2A, and the complex multiplication result is stored in the second data register 216; one path of the output result of the second data register 216 is directly output to the eighth accumulator unit 218, and the other path is delayed by the first delay unit 217 and then output to the eighth accumulator unit 218, and the register value is sequentially output to the timing word generating unit 2D from zero according to the unique word timing index; the eighth accumulator unit 218 performs an accumulation operation on the direct output result of the second data register 216 and the structure delayed by the first delay unit 217, and outputs the accumulation result to the third gating unit 220; the second counter unit 219 counts the unique word position index value, and the output value is used as the strobe judgment threshold value of the third strobe unit 220; the third gating unit 220 gates the output value of the eighth accumulator unit 218 into a head section, a middle section and a tail section according to the gating judgment threshold, and outputs the result to the first shifter unit 221; the first shifter unit 221 performs a rightward shift process on the output result of the third gate unit 220, and the shift result is stored in the third data register 222 at the corresponding positions of the head section, the middle section, and the tail section; the third data register 222 sequentially outputs the registered values to the data word demodulation unit 2C from zero according to the data word timing index.
Wherein the data word demodulation unit 2C includes a coefficient register unit 223, a first subtractor unit 224, a second multiplication unit 225, a second delay unit 226, a third multiplication unit 227, a third accumulator unit 228, a third counter unit 229, a second shifter unit 230, a fourth accumulator unit 231, a fourth multiplication unit 232, a second lookup table unit 233, a third complex multiplication unit 234, and a fourth complex multiplication unit 235;
the coefficient values registered by the coefficient register 223 are output to the second multiplication unit 225, the first subtractor unit 224, and the fourth accumulator unit 231, respectively; the second multiplication unit 225 receives the registered value outputted from the zero by the unique word operation unit 2B according to the data word timing index, multiplies the registered value by the coefficient value registered by the coefficient register 223, and outputs the multiplied result to the third accumulator unit 228; the first subtractor 224 performs subtraction between the constant 1 and the coefficient value registered in the coefficient register 223, and outputs the result to the third multiplier 227; the second delayer unit 226 receives the register value outputted from the unique word operation unit 2B from zero according to the data word timing index, delays by one time unit, and outputs to the third multiplying unit 227; the third multiplication unit 227 multiplies the two input values, and outputs the product result to the third accumulator unit 228; the third accumulator unit 228 adds the output values of the second multiplication unit 225 and the third multiplication unit 227, and outputs the result to the fourth complex multiplication unit 235; the third counter unit 229 sequentially counts up from zero according to the data word timing index, and the count value is output to the second shifter unit 230; the second shifter unit 230 performs a shift-left process on the received data, and outputs the shift result to the fourth accumulator unit 231; the fourth accumulator unit 231 adds the input of the coefficient register 223 and the input value of the second shifter unit 230, and the result is output to the fourth multiplication unit 232; the fourth multiplication unit 232 multiplies the output value of the fourth accumulator unit 231 and the output frequency word value of the frequency word processing unit 2A, and outputs the result to the second lookup table unit 233 as a lookup table index value; the second lookup table unit 233 outputs a natural log discrete index lookup table result of one trigonometric function period stored in advance to the third complex multiplication unit 234 according to the index value; the third complex multiplication unit 234 performs complex multiplication on the output of the second lookup table unit 233 and the complex value of the received data word obtained from the data processing module 1, and the obtained complex result is output to the fourth complex multiplication unit 235; the fourth complex multiplication unit 235 performs complex multiplication on the two complex values input by the third accumulator unit 228 and the third complex multiplication unit 234 to obtain data word demodulation result data, and writes the data word demodulation result data into the corresponding access unit of the data processing module 1 through the interface.
The timing word generating unit 2D includes a fifth accumulator unit 237, a fourth counter unit 238, a fifth multiplier unit 239, a first truncator unit 240, a third lookup table unit 241, a fifth complex multiplier unit 242, a sixth accumulator unit 243, a fourth strobe unit 244, a third square operation unit 245, a fourth square operation unit 246, a seventh accumulator unit 247, a fourth data register 248, a second comparator unit 249, a fifth strobe unit 250, and a timing word register 251;
the fifth accumulator unit 237 performs subcarrier-by-subcarrier accumulation on the registered value output from the unique word operation unit 2B, and the accumulated result is output to the fifth complex multiplier unit 242; the fourth counter unit 238 sequentially counts up from zero, and outputs the count value to the fifth multiplier unit 239 as a timing position hypothesis value; while the fifth multiplier unit 239 receives the control information outputted from the control information register 3 through the data processing module 1; the fifth multiplier unit 239 multiplies the two input data, and outputs the result to the first truncator unit 240; the first truncator unit 240 truncates the product value output from the fifth multiplier unit 239, and outputs the result as an index value to the third lookup table unit 241; the third lookup table unit 241 outputs the natural logarithmic dispersion index lookup table result of one trigonometric function period stored in advance as the phase compensation value generated on each subcarrier by the timing position hypothesis value according to the index value, and outputs to the fifth complex multiplier unit 242; the fifth complex multiplier 242 performs complex multiplication on the two input data to obtain a compensation result of each subcarrier accumulated value, and outputs the compensation result to the sixth accumulator 243; the sixth accumulator unit 243 performs an accumulation operation on the compensation result of each subcarrier accumulated value, and the obtained accumulated value is gated by the fourth gating unit 244 and divided into a real part and an imaginary part to be respectively and correspondingly output to the third square operation unit 245 and the fourth square operation unit 246; the seventh accumulator unit 247 performs a data accumulation operation on the square results output from the third square operation unit 245 and the fourth square operation unit 246, and accumulates and outputs to the second comparator unit 249 and the fourth data register 248; the second comparator unit 249 compares the output result of the seventh accumulator unit 247 with the registered data in the fourth data register 248, the larger ones and the index marks of the larger ones are stored back in the fourth data register 248, and when all the timing position samples outputted from the fourth strobe unit 244 are processed, the fifth strobe unit 250 strobes and writes the output result of the fourth data register 248 into the timing word register 251 for the data processing module 1.
Claims (4)
1. The anti-interference channel demodulation accelerator suitable for the satellite baseband processing chip comprises a data processing module (1), an algorithm processing module (2), a control information register (3) and a data information register (4), and is characterized in that:
the data processing module (1) is used for analyzing the multi-user control parameters sent by the control information register (3) under the control of the accelerator integrated controller, completing parameter processing, channel identification and data formatting operation, generating local data, performing access operation on the multi-user data information sent by the data information register (4), and outputting the user data extracted according to the need, the local generated data and the formatted control information to the algorithm processing module (2); the data word demodulation result and the timing word result output by the algorithm processing module (2) are buffered and output outwards under the control of the accelerator integrated controller;
the algorithm processing module (2) is used for carrying out anti-interference demodulation algorithm processing on the user data, the local generated data and the formatted control information sent by the data processing module (1), obtaining a data word demodulation result and a timing word result after processing, and outputting the processing result to the data processing module (1);
The control information register (3) comprises a plurality of register groups and is used for storing multiuser control parameters input by the accelerator integrated controller or the processor according to a certain format for reading by the data processing module (1);
the data information register (4) is used for caching the baseband sampling data sent from the outside under the control of the accelerator integrated controller, and dividing the baseband sampling data into multiple paths according to a multi-user data access rule and outputting the multiple paths to the data processing module (1);
the algorithm processing module (2) comprises a frequency word processing unit (2A), a unique word operation unit (2B), a data word demodulation unit (2C) and a timing word generation unit (2D);
the frequency word processing unit (2A) is used for receiving the extracted user data and the locally generated data output by the data processing module (1), processing the extracted user data and the locally generated data to generate de-modulated data and frequency word values, outputting the de-modulated data to the unique word operation unit (2B), and outputting the frequency word values to the unique word operation unit (2B) and the data word demodulation unit (2C) respectively; the unique word operation unit (2B) receives the de-modulated data and the frequency word value input by the frequency word processing unit (2A) and processes the data to generate a frequency-offset-removed unique word and a channel word result, wherein the frequency-offset-removed unique word result is output to the timing word generation unit (2D), and the channel word result is output to the data word demodulation unit (2C); the data word demodulation unit (2C) is used for processing the frequency word value, the channel word result and the extracted user data output by the data processing module (1) to obtain a data word demodulation result, and outputting the data word demodulation result back to the corresponding access unit of the data processing module (1); the timing word generating unit (2D) is used for processing the unique word result subjected to frequency deviation removal and the control information output by the data processing module (1) to obtain a timing word result, and outputting the timing word result back to the corresponding access unit of the data processing module (1);
The frequency word processing unit (2A) comprises a first complex multiplication unit (200), a first temporary register (201), an FFT operation unit (202), a first gating unit (203), a first square operation unit (204), a second square operation unit (205), a first accumulator unit (206), a first data register (207), a first comparator unit (208), a second gating unit (209), a second accumulator unit (210) and a frequency word register (211);
the first complex multiplication unit (200) performs complex multiplication operation on the extracted user data output by the data processing module (1) and locally generated data, and the product result is output to the first temporary register (201) and the FFT operation unit (202) respectively; a first temporary register (201); outputting the result of the product to a unique word operation unit (2B); an FFT operation unit (202) performs a fast Fourier transform operation on the data output from the first complex multiplication unit (200) and outputs the result to a first gating unit (203); when frequency word processing is performed, a first gating unit (203) gates the output result of the FFT operation unit (202) and correspondingly outputs the real part and the imaginary part of a complex signal to a first square operation unit (204) and a second square operation unit (205) respectively; the first accumulator unit (206) performs data accumulation operation on the square results output by the first square operation unit (204) and the second square operation unit (205), and the accumulated sums are respectively output to the first comparator unit (208) and the first data register (207); the first comparator unit (208) compares the output result of the first accumulator unit (206) with the registered data in the first data register (207), and the larger and larger index marks are stored back in the first data register (207); when all sample processing output by the FFT operation unit (202) is completed, a second gating unit (209) gates the result in the first data register (207) to a second accumulator unit (210); the second accumulator unit (210) performs data accumulation operation on the processing results of each subcarrier and each frame of the current channel of the second gating unit (209), and the accumulated results are output to the frequency word register (211); the frequency word register (211) outputs the frequency word numerical value to the unique word operation unit (2B) and the data word demodulation unit (2C), respectively.
2. An antijam channel demodulation accelerator for use with a satellite baseband processing chip as claimed in claim 1, wherein: the unique word operation unit (2B) comprises a first counter unit (212), a first multiplication unit (213), a first lookup table unit (214), a second complex multiplication unit (215), a second data register (216), a first delay unit (217), an eighth accumulator unit (218), a second counter unit (219), a third gating unit (220), a first shifter unit (221) and a third data register (222);
a first counter unit (212) sequentially counts up from zero according to the unique word timing index; the first multiplication unit (213) multiplies the output value of the first counter unit (212) and the frequency word value output by the frequency word processing unit (2A), and the product result is used as the input of the first lookup table unit (214); the first lookup table unit (214) stores the natural logarithmic discrete index result of one trigonometric function period in a fixed-point mode in advance, takes the product output by the first multiplication unit (213) as an input index, obtains a complex result corresponding to the lookup table and outputs the complex result to the second complex multiplication unit (215); the second complex multiplication unit (215) performs complex multiplication operation on the product result output by the first lookup table unit (214) and the frequency word processing unit (2A), and the complex multiplication result is stored in the second data register (216); one path of output result of the second data register (216) is directly output to the eighth accumulator unit (218), one path is delayed by the first delay unit (217) and then is output to the eighth accumulator unit (218), and register values are sequentially output to the timing word generating unit (2D) from zero according to the unique word timing index; an eighth accumulator unit (218) performs an accumulation operation on the direct output result of the second data register (216) and the structure delayed by the first delay unit (217), and outputs the accumulation result to a third gating unit (220); the second counter unit (219) counts the unique word position index value, and outputs the value as a gating judgment threshold of the third gating unit (220); the third gating unit (220) gates the output value of the eighth accumulator unit (218) into a head section, a middle section and a tail section according to a gating judgment threshold value, and outputs the data to the first shifter unit (221); the first shifter unit (221) performs rightward shift processing on the output result of the third gating unit (220), and the shift result is stored in a third data register (222) according to the corresponding positions of the head section, the middle section and the tail section; the third data register (222) sequentially outputs the registered values to the data word demodulation unit (2C) from zero according to the data word timing index.
3. An antijam channel demodulation accelerator for use with a satellite baseband processing chip as claimed in claim 1, wherein: the data word demodulation unit (2C) comprises a coefficient register unit (223), a first subtractor unit (224), a second multiplication unit (225), a second delay unit (226), a third multiplication unit (227), a third accumulator unit (228), a third counter unit (229), a second shifter unit (230), a fourth accumulator unit (231), a fourth multiplication unit (232), a second lookup table unit (233), a third complex multiplication unit (234) and a fourth complex multiplication unit (235);
the coefficient values registered by the coefficient register unit (223) are output to the second multiplication unit (225), the first subtractor unit (224) and the fourth accumulator unit (231), respectively; the second multiplication unit (225) receives the register value output by the unique word operation unit (2B) from zero according to the time sequence index of the data word, performs multiplication operation with the coefficient value registered by the coefficient register unit (223), and outputs the product result to the third accumulator unit (228); the first subtracter unit (224) performs subtraction operation on the constant 1 and the coefficient value registered by the coefficient register unit (223), and then outputs the result to the third multiplying unit (227); the second delayer unit (226) receives the register value outputted by the unique word operation unit (2B) from zero according to the time sequence index of the data word, delays the register value by one time unit and outputs the delayed register value to the third multiplication unit (227); a third multiplication unit (227) multiplies the two input values, and outputs the product result to a third accumulator unit (228); a third accumulator unit (228) adds the output values of the second multiplication unit (225) and the third multiplication unit (227), and the obtained result is output to a fourth complex multiplication unit (235); a third counter unit (229) sequentially counts up from zero according to the data word timing index, and the count value is output to the second shifter unit (230); the second shifter unit (230) shifts the received data to the left, and outputs the shift result to the fourth accumulator unit (231); a fourth accumulator unit (231) adds the input of the coefficient register unit (223) and the input value of the second shifter unit (230), and the result is output to a fourth multiplication unit (232); a fourth multiplication unit (232) multiplies the output value of the fourth accumulator unit (231) and the output frequency word value of the frequency word processing unit (2A), and outputs the result to the second lookup table unit (233) as a lookup table index value; the second lookup table unit (233) outputs a natural log discrete index lookup table result of one trigonometric function period stored in advance to the third complex multiplication unit (234) according to the index value; a third complex multiplication unit (234) performs complex multiplication on the output of the second lookup table unit (233) and the complex value of the received data word obtained from the data processing module (1), and the obtained complex result is output to a fourth complex multiplication unit (235); the fourth complex multiplication unit (235) performs complex multiplication operation on the two complex values input by the third accumulator unit (228) and the third complex multiplication unit (234) to obtain data word demodulation result data, and the data word demodulation result data is written into a corresponding access unit of the data processing module (1) through an interface.
4. An antijam channel demodulation accelerator for use with a satellite baseband processing chip as claimed in claim 1, wherein: the timing word generating unit (2D) comprises a fifth accumulator unit (237), a fourth counter unit (238), a fifth multiplier unit (239), a first truncator unit (240), a third lookup table unit (241), a fifth complex multiplier unit (242), a sixth accumulator unit (243), a fourth gating unit (244), a third square operation unit (245), a fourth square operation unit (246), a seventh accumulator unit (247), a fourth data register (248), a second comparator unit (249), a fifth gating unit (250) and a timing word register (251);
a fifth accumulator unit (237) performs subcarrier-by-subcarrier accumulation operation on the register value output from the unique word operation unit (2B), and the accumulated result is output to a fifth complex multiplier unit (242); a fourth counter unit (238) sequentially counts up from zero and outputs the count value to a fifth multiplier unit (239) as a timing position hypothesis value; meanwhile, a fifth multiplier unit (239) receives control information output by the control information register (3) through the data processing module (1); a fifth multiplier unit (239) multiplies the two input data, and outputs the result to a first truncator unit (240); the first truncator unit (240) truncates the product value output by the fifth multiplier unit (239), and the result is used as an index value and is output to the third lookup table unit (241); a third lookup table section (241) outputs a natural logarithmic dispersion index lookup table result of one trigonometric function period stored in advance as a phase compensation value generated on each subcarrier by the timing position hypothesis value, based on the index value, and outputs the result to a fifth complex multiplier section (242); a fifth complex multiplier unit (242) performs complex multiplication on the two input data to obtain a compensation result of each subcarrier accumulated value, and outputs the compensation result to a sixth accumulator unit (243); the sixth accumulator unit (243) performs accumulation operation on the compensation result of each subcarrier accumulated value, the obtained accumulated value is gated by the fourth gating unit (244), and the accumulated value is divided into a real part and an imaginary part which are respectively and correspondingly output to the third square operation unit (245) and the fourth square operation unit (246); the seventh accumulator unit (247) performs data accumulation operation on the square results output by the third square operation unit (245) and the fourth square operation unit (246), and accumulates and outputs the accumulated results to the second comparator unit (249) and the fourth data register (248); the second comparator unit (249) compares the output result of the seventh accumulator unit (247) with the registered data in the fourth data register (248), the larger index marks and the larger index marks are stored back into the fourth data register (248), and when all timing position sampling points output by the fourth gating unit (244) are processed, the fifth gating unit (250) gates, and the output result of the fourth data register (248) is written into the timing word register (251) for being used by the data processing module (1).
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