CN114124146B - External port expansion device for network analyzer and radio frequency switch control method - Google Patents
External port expansion device for network analyzer and radio frequency switch control method Download PDFInfo
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- CN114124146B CN114124146B CN202210103722.4A CN202210103722A CN114124146B CN 114124146 B CN114124146 B CN 114124146B CN 202210103722 A CN202210103722 A CN 202210103722A CN 114124146 B CN114124146 B CN 114124146B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
Abstract
An external port expansion device for a network analyzer and a radio frequency switch control method comprise a first I/O connection interface, a second I/O connection interface, a first switch circuit, a second switch circuit, a switch configuration circuit, a cascade configuration circuit, a first serial-to-parallel interface and a second serial-to-parallel interface. Firstly, the first switch circuit respectively sends the IO control signal received by the first I/O connection interface to the second switch circuit, the switch configuration circuit and the cascade configuration circuit, and the second switch circuit responds to the switch control signal sent by the switch configuration circuit and sends the IO control signal to the second I/O connection interface, the first serial-parallel interface or the second serial-parallel interface. Because the radio frequency switch control of the network analyzer is realized through the I/O interface circuit of the external port expansion device, the switch switching of the network analyzer is faster, and the response speed of the network analyzer is further improved.
Description
Technical Field
The application relates to the technical field of network analyzers, in particular to an external port expansion device and a radio frequency switch control method for a network analyzer.
Background
The network analyzer is a comprehensive microwave measuring instrument capable of scanning and measuring in a wide frequency band to determine network parameters. The network analyzer is a microwave network analyzer, is a novel instrument for measuring network parameters, can directly measure complex scattering parameters of active or passive, reversible or irreversible double-port and single-port networks, and gives the amplitude and phase frequency characteristics of each scattering parameter in a frequency scanning mode. The network analyzer can correct errors of the measurement results point by point and convert dozens of other network parameters such as reflection power, return loss, reflection coefficient, standing-wave ratio and the like. Many devices now integrate many functions into a single device, resulting in multiple rf ports per device. In the field of wireless communication, for example, cellular phones, etc., need to support multiple frequency bands and signals of more systems, such as WLAN, bluetooth, GPS, etc., which further increases the complexity of the device. And, for example, a multiple antenna technique of Multiple Input Multiple Output (MIMO) is employed in wireless services in order to achieve faster data transmission rates. In response to the requirement of multi-port measurement, when a network analyzer (generally, the network analyzer has only two external ports) measures radio frequency parameters of a multi-port device, in order to improve the measurement efficiency, a matrix switch is generally used in cooperation with the network analyzer, and the network analyzer is connected to the matrix switch through a network interface and/or a USB interface.
Disclosure of Invention
The application provides an external port expanding unit to when solving network analysis appearance multiport setting among the prior art, port response inefficiency's technical problem.
In a first aspect, an embodiment provides an external port expansion device for a network analyzer, including a first I/O connection interface, a second I/O connection interface, a first switch circuit, a second switch circuit, a switch configuration circuit, a cascade configuration circuit, a first serial-to-parallel interface, and a second serial-to-parallel interface;
the first I/O connection interface is connected with the first switch circuit; the first I/O connection interface is used for being connected with a control signal output end of the network analyzer, receiving an IO control signal sent by the network analyzer and sending the IO control signal to the first switch circuit;
the first switch circuit is respectively connected with the second switch circuit, the switch configuration circuit and the cascade configuration circuit; the first switch circuit is configured to send the IO control signal received by the first I/O connection interface to the second switch circuit, the switch configuration circuit, and the cascade configuration circuit, respectively;
the switch configuration circuit is connected with the second switch circuit and used for responding to the IO control signal to send a switch control signal to the second switch circuit;
the second switch circuit is respectively connected with the second I/O connection interface, the first serial-to-parallel interface and the second serial-to-parallel interface; the second switch circuit is configured to send the IO control signal sent by the first switch circuit to the second I/O connection interface, the first serial-to-parallel interface, or the second serial-to-parallel interface in response to the switch control signal;
the second I/O connection interface is used for being connected with the external port expansion device at the next stage of cascade connection; the second I/O connection interface is configured to send the IO control signal sent by the second switch circuit to the external port expansion device of the next stage in cascade connection;
the first serial-parallel interface is used for performing serial-parallel conversion on the IO control signal and outputting the IO control signal when the IO control signal sent by the second switch circuit is received so as to control a radio frequency switch of the network analyzer;
the second serial-parallel interface is used for performing serial-parallel conversion on the IO control signal and outputting the IO control signal when the IO control signal sent by the second switch circuit is received so as to control the radio frequency switch of the network analyzer;
when receiving an IO control signal sent by the second switch circuit, the cascade configuration circuit is configured to respond to the IO control signal and feed back a connection state of the second I/O connection interface; and feeding back a cascade connection signal when the second I/O connection interface is connected with the external port expansion device at the next cascade stage, and feeding back a cascade disconnection signal when the second I/O connection interface is not connected with the external port expansion device at the next cascade stage.
In one embodiment, the external port expansion device further comprises a communication interface and a control processor;
the communication interface is connected with the control processor; the communication interface is used for establishing communication connection with the network analyzer, receiving a radio frequency switching command sent by the network analyzer and sending the radio frequency switching command to the control processor;
the control processor is connected with the first switch circuit; and the control processor is used for converting the radio frequency switching command into the IO control signal and sending the IO control signal to the first switching circuit when receiving the radio frequency switching command.
In one embodiment, the communication interface includes a wired network interface, a wireless network interface and/or a USB interface.
In one embodiment, the first I/O connection interface includes a first connection end, a second connection end, and a third connection end;
the first switch circuit comprises a first switch, a second switch and a third switch;
the first switch is respectively connected with the first connection end of the first I/O connection interface and the switch configuration circuit, and is configured to send the IO control signal acquired by the first I/O connection interface to the switch configuration circuit;
the second switch is respectively connected with the second connection end of the first I/O connection interface and the second switch circuit, and is configured to send the IO control signal obtained by the first I/O connection interface to the second switch circuit;
the third switch is respectively connected with a third connection end of the first I/O connection interface and the cascade configuration circuit, and is configured to send the IO control signal acquired by the first I/O connection interface to the cascade configuration circuit.
In one embodiment, the IO control signal includes a chip select configuration signal, a cascade configuration signal, and a serial-to-parallel conversion and output enable signal;
the first connection end of the first I/O connection interface is used for receiving the chip selection configuration signal;
the second connection end of the first I/O connection interface is used for receiving the serial-parallel conversion and outputting an enabling signal;
and the third connection end of the first I/O connection interface is used for receiving the cascade configuration signal.
In one embodiment, the switch configuration circuit includes a CS register, and the CS register is configured to configure on or off of the second switch circuit in response to the chip select configuration signal to establish connection between the first switch circuit and the first I/O connection interface, the first serial-to-parallel interface, or the second serial-to-parallel interface.
In one embodiment, the cascade configuration circuit includes a status register, and the status register is configured to feed back a connection status of the second I/O connection interface in response to the cascade configuration signal.
In an embodiment, the first serial-to-parallel interface and/or the second serial-to-parallel interface is configured to, when receiving the serial-to-parallel conversion and output enable signal sent by the second switch circuit, perform serial-to-parallel conversion on the serial-to-parallel conversion and output enable signal, and then output the serial-to-parallel conversion and output enable signal, so as to control a radio frequency switch of the network analyzer.
In a second aspect, an embodiment provides a radio frequency switch control method for a network analyzer, including:
receiving an IO control signal sent by the network analyzer, and sending the IO control signal to a first switch circuit;
when the first switch circuit acquires the IO control signal, the IO control signal is respectively sent to a second switch circuit, a switch configuration circuit and a cascade configuration circuit;
when the switch configuration circuit acquires the IO control signal, responding to the IO control signal to send a switch control signal to the second switch circuit;
when the second switch circuit obtains the switch control signal, the IO control signal is sent to a second I/O connection interface, a first serial-to-parallel interface or a second serial-to-parallel interface;
when the second I/O connection interface acquires the IO control signal, the IO control signal is sent to the next-stage external port expansion device in cascade connection;
when the first serial-parallel interface or the second serial-parallel interface acquires the IO control signal, the IO control signal is output after serial-parallel conversion, so that the control of a radio frequency switch of the network analyzer is realized;
and when the cascade configuration circuit acquires the IO control signal, the cascade configuration circuit responds to the IO control signal and feeds back the connection state of the second I/O connection interface.
In one embodiment, the radio frequency switch control method further includes:
and when receiving a radio frequency switching command sent by the network analyzer, converting the radio frequency switching command into the IO control signal, and sending the IO control signal to the first switching circuit.
According to the above embodiment, an external port expansion device for a network analyzer includes a first I/O connection interface, a second I/O connection interface, a first switch circuit, a second switch circuit, a switch configuration circuit, a cascade configuration circuit, a first serial-to-parallel interface, and a second serial-to-parallel interface. Firstly, the first switch circuit respectively sends the IO control signal received by the first I/O connection interface to the second switch circuit, the switch configuration circuit and the cascade configuration circuit, and the second switch circuit responds to the switch control signal sent by the switch configuration circuit and sends the IO control signal to the second I/O connection interface, the first serial-parallel interface or the second serial-parallel interface. Because the radio frequency switch control of the network analyzer is realized through the I/O interface circuit of the external port expansion device, the switch switching of the network analyzer is faster, and the response speed of the network analyzer is further improved.
Drawings
FIG. 1 is a schematic diagram illustrating an expansion of an external interface of a network analyzer in the prior art;
FIG. 2 is a schematic structural diagram of an external interface extension apparatus for a network analyzer according to an embodiment;
FIG. 3 is a circuit diagram of an external port expansion device according to an embodiment;
FIG. 4 is a circuit diagram illustrating a cascade connection of two external port expansion devices according to an embodiment;
FIG. 5 is a block diagram illustrating a cascade connection of two external port expansion devices according to an embodiment;
FIG. 6 is a SPI data flow for configuration of RF _ SWCH1_4 in one embodiment;
FIG. 7 is a SPI data flow for configuration RF _ SWCH2_4 in one embodiment;
FIG. 8 is a diagram illustrating an exemplary configuration of an external port extender device to initialize SPI data flow.
Detailed Description
The present invention will be described in further detail with reference to the following detailed description and accompanying drawings. Wherein like elements in different embodiments are numbered with like associated elements. In the following description, numerous details are set forth in order to provide a better understanding of the present application. However, those skilled in the art will readily recognize that some of the features may be omitted or replaced with other elements, materials, methods in different instances. In some instances, certain operations related to the present application have not been shown or described in detail in order to avoid obscuring the core of the present application from excessive description, and it is not necessary for those skilled in the art to describe these operations in detail, so that they may be fully understood from the description in the specification and the general knowledge in the art.
Furthermore, the features, operations, or characteristics described in the specification may be combined in any suitable manner to form various embodiments. Also, the various steps or actions in the method descriptions may be transposed or transposed in order, as will be apparent to one of ordinary skill in the art. Thus, the various sequences in the specification and drawings are for the purpose of describing certain embodiments only and are not intended to imply a required sequence unless otherwise indicated where such sequence must be followed.
The numbering of the components as such, e.g., "first", "second", etc., is used herein only to distinguish the objects as described, and does not have any sequential or technical meaning. The term "connected" and "coupled" when used in this application, unless otherwise indicated, includes both direct and indirect connections (couplings).
Referring to fig. 1, a schematic diagram of an expansion of an external interface of a network analyzer in the prior art is shown, the network analyzer generally has only two ports, and can be expanded into 12 ports through a matrix switch, and the network analyzer controls the matrix switch through a control interface to realize switching of the 12 ports. As shown in fig. 1, one network analyzer can only control one matrix switch, and cannot further expand the ports.
Referring to fig. 2, a schematic structural diagram of an external interface expansion device for a network analyzer in an embodiment is shown, where the external interface expansion device includes a communication interface, a control circuit, and a plurality of radio frequency switches, and the communication interface in the prior art generally adopts a network interface or a USB interface, and since the network interface or the USB interface needs to perform communication protocol conversion, the response time of the radio frequency switches is prolonged, and the working efficiency of the network analyzer is further reduced.
In the embodiment of the application, the radio frequency switch control of the network analyzer is realized through the I/O interface circuit of the external port expansion device, so that the switch switching of the network analyzer is faster, the working efficiency of the network analyzer is further improved, and the response speed of the matrix switch can be improved by more than 10 times.
Example one
Referring to fig. 3, a schematic circuit diagram of an external port expansion device in an embodiment is shown, where the external port expansion device includes a first I/O connection interface 10, a second I/O connection interface 11, a first switch circuit 12, a second switch circuit 15, a switch configuration circuit 14, a cascade configuration circuit 13, a first serial-to-parallel interface 16, and a second serial-to-parallel interface 17. The first I/O connection interface 10 is connected to the first switch circuit 12, and the first I/O connection interface 10 is configured to be connected to a control signal output end of the network analyzer, and is configured to receive an IO control signal sent by the network analyzer, and send the IO control signal to the first switch circuit 12. The first switch circuit 12 is connected to the second switch circuit 15, the switch configuration circuit 14, and the cascade configuration circuit 13, respectively. The first switch circuit 12 is configured to send the IO control signal received by the first I/O connection interface 10 to the second switch circuit 15, the switch configuration circuit 14, and the cascade configuration circuit 13, respectively. The switch configuration circuit 14 is connected to the second switch circuit 15, and is configured to respond to the IO control signal to send a switch control signal to the second switch circuit 15. The second switching circuit 15 is connected to the second I/O connection interface 11, the first serial-to-parallel interface 16, and the second serial-to-parallel interface 17, respectively. The second switch circuit 15 is configured to respond to the and switch control signal and send the IO control signal sent by the first switch circuit 12 to the second I/O connection interface 11, the first serial-parallel interface 16, or the second serial-parallel interface 17. The second I/O connection interface 11 is used to connect with the cascaded next-stage external port expansion device, and the second I/O connection interface 11 is used to send the IO control signal sent by the second switch circuit 15 to the cascaded next-stage external port expansion device. The first serial-parallel interface 16 is configured to, when receiving an IO control signal sent by the second switch circuit, perform serial-parallel conversion on the IO control signal and output the converted IO control signal, so as to control the radio frequency switch of the network analyzer. The second serial-parallel interface 17 is configured to, when receiving an IO control signal sent by the second switch circuit, perform serial-parallel conversion on the IO control signal and then output the IO control signal, so as to control the radio frequency switch of the network analyzer. The cascade configuration circuit 13 is configured to feed back a connection state of the second I/O connection interface in response to the IO control signal. And feeding back a cascade connection signal when the second I/O connection interface 11 is connected with the cascade connection next-stage external port expansion device, and feeding back a cascade non-connection signal when the second I/O connection interface 11 is not connected with the cascade connection next-stage external port expansion device.
In an embodiment, the first switch circuit 12, the second switch circuit 15, the switch configuration circuit 14, and the cascade configuration circuit 13 are programmable logic devices.
In one embodiment, the external port expansion device further comprises a communication interface 18 and a control processor 19. The communication interface 18 is connected with the control processor 19, and the communication interface 18 is used for establishing communication connection with the network analyzer, receiving a radio frequency switching command sent by the network analyzer, and sending the radio frequency switching command to the control processor 19. The control processor 19 is connected to the first switch circuit 12, and the control processor 19 is configured to convert the radio frequency switching command into an IO control signal when receiving the radio frequency switching command, and send the IO control signal to the first switch circuit. In one embodiment, the communication interface 18 includes a wired network interface, a wireless network interface, and/or a USB interface.
In one embodiment, the first I/O connection interface 10 includes a first connection end, a second connection end, and a third connection end. The first switch circuit 12 includes a first switch, a second switch, and a third switch. The first switch is connected to the first connection end of the first I/O connection interface 10 and the switch configuration circuit 14, respectively, and is configured to send the IO control signal acquired by the first I/O connection interface 10 to the switch configuration circuit 14. The second switch is connected to the second connection end of the first I/O connection interface 10 and the second switch circuit 15, respectively, and is configured to send the IO control signal obtained by the first I/O connection interface 10 to the second switch circuit 15. The third switch is connected to the third connection end of the first I/O connection interface 10 and the cascade configuration circuit 13, respectively, and is configured to send the IO control signal obtained by the first I/O connection interface 10 to the cascade configuration circuit 13.
In one embodiment, the IO control signals include a chip select configuration signal, a cascade configuration signal, and a serial-to-parallel conversion and output enable signal. The first connection end of the first I/O connection interface 10 is configured to receive a chip select configuration signal, the second connection end of the first I/O connection interface 10 is configured to receive a serial-to-parallel conversion and output enable signal, and the third connection end of the first I/O connection interface 10 is configured to receive a cascade configuration signal.
In one embodiment, the switch configuration circuit 14 includes a CS register for configuring the on or off of the second switch circuit in response to a chip select configuration signal to establish the connection of the first switch circuit 12 with the first I/O connection interface 11, the first cascode interface 16, or the second cascode interface 17.
In one embodiment, the cascade configuration circuit 13 comprises a status register for feeding back the connection status of the second I/O connection interface 11 in response to the cascade configuration signal.
In an embodiment, the first serial-to-parallel interface 16 or the second serial-to-parallel interface 17 is configured to, when receiving the serial-to-parallel conversion and output enable signal sent by the second switch circuit 15, perform serial-to-parallel conversion on the serial-to-parallel conversion and output enable signal, and then output the serial-to-parallel conversion and output enable signal, so as to control the radio frequency switch of the network analyzer.
Based on the external port expansion device, in an embodiment of the present application, a radio frequency switch control method for a network analyzer is further disclosed, where the method includes:
firstly, an IO control signal sent by a network analyzer is received, and the IO control signal is sent to a first switch circuit. When the first switch circuit acquires the IO control signal, the IO control signal is respectively sent to the second switch circuit, the switch configuration circuit and the cascade configuration circuit;
then, when the switch configuration circuit acquires the IO control signal, the switch configuration circuit responds to the IO control signal to send a switch control signal to the second switch circuit; when the second switch circuit obtains the switch control signal, the IO control signal is sent to the second I/O connection interface, the first serial-to-parallel interface or the second serial-to-parallel interface;
finally, when the second I/O connection interface acquires the IO control signal, the IO control signal is sent to the next-stage external port expansion device in cascade connection; when the first serial-parallel interface or the second serial-parallel interface acquires an IO control signal, the IO control signal is output after serial-parallel conversion, so that the control of a radio frequency switch of the network analyzer is realized; and when the cascade configuration circuit acquires the IO control signal, the connection state of the second I/O connection interface is fed back in response to the IO control signal.
In one embodiment, the rf switch control method further includes:
when receiving a radio frequency switching command sent by the network analyzer, the radio frequency switching command is converted into an IO control signal, and the IO control signal is sent to the first switching circuit.
The embodiment of the application discloses an external port expansion device for a network analyzer, which comprises a first I/O connection interface, a second I/O connection interface, a first switch circuit, a second switch circuit, a switch configuration circuit, a cascade configuration circuit, a first serial-to-parallel interface and a second serial-to-parallel interface. Firstly, the first switch circuit respectively sends the IO control signal received by the first I/O connection interface to the second switch circuit, the switch configuration circuit and the cascade configuration circuit, and the second switch circuit responds to the switch control signal sent by the switch configuration circuit and sends the IO control signal to the second I/O connection interface, the first serial-parallel interface or the second serial-parallel interface. Because the radio frequency switch control of the network analyzer is realized through the I/O interface circuit of the external port expansion device, the switch switching of the network analyzer is faster, and the response speed of the network analyzer is further improved.
In the following, the external port expansion device disclosed in the present application is described with an embodiment, as shown in fig. 4, the communication interface 18 communicates with the network analyzer and receives the rf switch command, and the communication interface 18 may be a USB, a network port, or the like. After acquiring the rf switch command, the control processor 19 converts the rf switch command into a corresponding IO control signal. In one embodiment, the control processor 19 performs information interaction with the programmable logic device through the SPI, and all SPI buses share clock and data lines, which are distinguished by the chip select CS. And (4) building an internal logic circuit of the external port expansion device by using the programmable logic device. The first switch circuit 12 functions to select internal control (control processor issued CSx _ MCU) or external control (CSx _ IN input to the first I/O connection interface), i.e. the first switch circuit comprises three two-way single pole double throw switches, e.g. CS0_ MCU, CS0_ IN, one of which is output to CS0, and so on.
The IO control signals include signal CS0, signal CS1, and signal CS 2. The signal CS0 is a configuration chip select CS register (i.e. a switch configuration circuit) to control the second switch circuit, and the signal CS1 is an enable serial-parallel and output signal enable interface, and is gated by the second switch circuit (a multiple-select-1 switch). The signal CS2 is a read status register (i.e., a cascade configuration circuit), such as whether a lower external port extension device has access to the second I/O connection interface. The CS register holds the gating state of the second switching circuit. When the signal CS0 is gated, the upstream CS register is configured to control the gating state of the second switching circuit. The status register is used for informing the upstream whether a downstream device exists in the initialization process. Referring to fig. 5, a schematic diagram of cascade connection of external port expansion devices in an embodiment is shown, in which a network analyzer is connected through control interfaces of two external port expansion devices. In the initialization process, the network analyzer can read the status register of the first external port expansion device, because the first external port expansion device is connected with the second external port expansion device, and the status register of the first external port expansion device displays that the next device is connected. And the network analyzer reads the status register of the second external port expansion device and displays that no lower-level equipment exists. Thus, the network analyzer knows that two external port expansion devices are connected. Since the IO control signal is serial data of SPI, it needs to be converted into parallel data to control the rf switch, and in an embodiment, the first serial to parallel interface and the second serial to parallel interface may select chips such as 74HC 595.
The following examples illustrate the manner in which the external port expansion device implements the rf switch control. As shown in fig. 4 and 5, since the control IO inputs of the two external port expansion devices are both connected to the upper-level device, the first switch circuits of the two external port expansion devices are both switched to the control IO inputs. Namely CS0= CS0_ IN, CS1= CS1_ IN, CS2= CS2_ IN.
The CS registers have at least 5 configurations, which are REG _ CS0, REG _ CS1, REG _ CS2, REG _ CS3, REG _ CS4, REG _ CSx =0 is gated CON _ CSx, REG _ CSx =1 is non-gated CON _ CSx. The status register has REG _ STATE, REG _ STATE =1 indicates that the lower level has a device connection, and REG _ STATE =0 indicates that the lower level has no device connection.
Assuming that RF _ SWCH1_4 needs to be controlled to be turned on, the CS register of the first external port expansion device is configured first, CS0_ IN is gated, that is, CS0 is also gated, SPI transfers data, REG _ CS4 is configured to be 0, and CON _ CS4 is gated. CS0 is no longer gated, SPI transmits data, and the second serial-to-interface controls RF _ SWICH1_4 to turn on. The SPI transmits data. Assume that RF _ SWCH2_4 needs to be controlled to be on. The CS register of the first external port extension device is configured first, CS0_ IN is gated, namely CS0 is also gated, SPI transmits data, REG _ CS0 is configured to be 0, and CON _ CS0 is gated. At this time, since the control IO output of the first external port expansion device is connected to the control IO input of the second external port expansion device, when CON _ CS0 is gated, CS0 of the second external port expansion device is also gated. At this time, CS0 of the first external port expansion device is no longer gated, and the CS register of the second external port expansion device is reconfigured to configure REG _ CS4 as 0, and CON _ CS4 is gated. And gating the CS0 of the second external port expansion device, configuring the REG _ CS1 as 0, gating CON _ CS1, and not gating the CS of the first external port expansion device. SPI transmits data and the second deserializer interface controls RF _ SWICH2_4 to be on. The SPI data flow is shown in fig. 6 and 7, wherein fig. 6 is the SPI data flow with RF _ SWCH1_4 configured in one embodiment, and fig. 7 is the SPI data flow with RF _ SWCH2_4 configured in one embodiment. Certainly, initialization is required when the external port expansion device is powered on, increased or decreased in number, and the SPI data stream during initialization is as shown in fig. 8, which is an initialization SPI data stream for configuring the external port expansion device in one embodiment.
The present invention has been described in terms of specific examples, which are provided to aid in understanding the invention and are not intended to be limiting. Numerous simple deductions, modifications or substitutions may also be made by those skilled in the art in light of the present teachings.
Claims (10)
1. An external port expansion device for a network analyzer is characterized by comprising a first I/O connection interface, a second I/O connection interface, a first switch circuit, a second switch circuit, a switch configuration circuit, a cascade configuration circuit, a first serial-to-parallel interface and a second serial-to-parallel interface;
the first I/O connection interface is connected with the first switch circuit; the first I/O connection interface is used for being connected with a control signal output end of the network analyzer, receiving an IO control signal sent by the network analyzer and sending the IO control signal to the first switch circuit;
the first switch circuit is respectively connected with the second switch circuit, the switch configuration circuit and the cascade configuration circuit; the first switch circuit is configured to send the IO control signal received by the first I/O connection interface to the second switch circuit, the switch configuration circuit, and the cascade configuration circuit, respectively;
the switch configuration circuit is connected with the second switch circuit and used for responding to the IO control signal to send a switch control signal to the second switch circuit;
the second switch circuit is respectively connected with the second I/O connection interface, the first serial-to-parallel interface and the second serial-to-parallel interface; the second switch circuit is configured to send the IO control signal sent by the first switch circuit to the second I/O connection interface, the first serial-to-parallel interface, or the second serial-to-parallel interface in response to the switch control signal;
the second I/O connection interface is used for being connected with the external port expansion device at the next stage of cascade connection; the second I/O connection interface is configured to send the IO control signal sent by the second switch circuit to the external port expansion device of the next stage in cascade connection;
the first serial-parallel interface is used for performing serial-parallel conversion on the IO control signal and outputting the IO control signal when the IO control signal sent by the second switch circuit is received so as to control a radio frequency switch of the network analyzer;
the second serial-parallel interface is used for performing serial-parallel conversion on the IO control signal and outputting the IO control signal when the IO control signal sent by the second switch circuit is received so as to control the radio frequency switch of the network analyzer;
when receiving an IO control signal sent by the first switch circuit, the cascade configuration circuit is configured to respond to the IO control signal and feed back a connection state of the second I/O connection interface; and feeding back a cascade connection signal when the second I/O connection interface is connected with the external port expansion device at the next cascade stage, and feeding back a cascade disconnection signal when the second I/O connection interface is not connected with the external port expansion device at the next cascade stage.
2. The external port expansion device of claim 1, further comprising a communication interface and a control processor;
the communication interface is connected with the control processor; the communication interface is used for establishing communication connection with the network analyzer, receiving a radio frequency switching command sent by the network analyzer and sending the radio frequency switching command to the control processor;
the control processor is connected with the first switch circuit; and the control processor is used for converting the radio frequency switching command into the IO control signal and sending the IO control signal to the first switching circuit when receiving the radio frequency switching command.
3. The external port expansion device of claim 2, wherein the communication interface comprises a wired network interface, a wireless network interface, and/or a USB interface.
4. The add-on port expansion device of claim 2, wherein the first I/O connection interface comprises a first connection end, a second connection end, and a third connection end;
the first switch circuit comprises a first switch, a second switch and a third switch;
the first switch is respectively connected with the first connection end of the first I/O connection interface and the switch configuration circuit, and is configured to send the IO control signal acquired by the first I/O connection interface to the switch configuration circuit;
the second switch is respectively connected with the second connection end of the first I/O connection interface and the second switch circuit, and is configured to send the IO control signal obtained by the first I/O connection interface to the second switch circuit;
the third switch is respectively connected with a third connection end of the first I/O connection interface and the cascade configuration circuit, and is configured to send the IO control signal acquired by the first I/O connection interface to the cascade configuration circuit.
5. The external port expansion device according to claim 4, wherein the IO control signal comprises a chip select configuration signal, a cascade configuration signal, and a serial-to-parallel conversion and output enable signal;
the first connection end of the first I/O connection interface is used for receiving the chip selection configuration signal;
the second connection end of the first I/O connection interface is used for receiving the serial-parallel conversion and outputting an enabling signal;
and the third connection end of the first I/O connection interface is used for receiving the cascade configuration signal.
6. The external port expansion device of claim 5, wherein the switch configuration circuit comprises a CS register to configure the second switch circuit to be turned on or off in response to the chip select configuration signal to establish the connection of the first switch circuit with the first I/O connection interface, the first serial-to-parallel interface, or the second serial-to-parallel interface.
7. The external port expansion device of claim 5, wherein said cascade configuration circuit comprises a status register for feeding back a connection status of said second I/O connection interface in response to said cascade configuration signal.
8. The external port expansion device according to claim 5, wherein the first deserializer interface and/or the second deserializer interface are/is configured to deserialize and output an enable signal when receiving the deserializer and output enable signal sent by the second switch circuit, so as to control a radio frequency switch of the network analyzer.
9. A radio frequency switch control method for a network analyzer, comprising:
receiving an IO control signal sent by the network analyzer, and sending the IO control signal to a first switch circuit;
when the first switch circuit acquires the IO control signal, the IO control signal is respectively sent to a second switch circuit, a switch configuration circuit and a cascade configuration circuit;
when the switch configuration circuit acquires the IO control signal, responding to the IO control signal to send a switch control signal to the second switch circuit;
when the second switch circuit obtains the switch control signal, the IO control signal is sent to a second I/O connection interface, a first serial-to-parallel interface or a second serial-to-parallel interface;
when the second I/O connection interface acquires the IO control signal, the IO control signal is sent to the next-stage external port expansion device in cascade connection;
when the first serial-parallel interface or the second serial-parallel interface acquires the IO control signal, the IO control signal is output after serial-parallel conversion, so that the control of a radio frequency switch of the network analyzer is realized;
and when the cascade configuration circuit acquires the IO control signal, the cascade configuration circuit responds to the IO control signal and feeds back the connection state of the second I/O connection interface.
10. The radio frequency switch control method of claim 9, further comprising:
and when receiving a radio frequency switching command sent by the network analyzer, converting the radio frequency switching command into the IO control signal, and sending the IO control signal to the first switching circuit.
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| US6912202B1 (en) * | 2001-01-25 | 2005-06-28 | Advanced Micro Device, Inc. | Arrangement for testing network switch expansion port using external logic to emulate connected expansion port |
| US6590417B1 (en) * | 2001-04-03 | 2003-07-08 | Cypress Semiconductor Corporation | Cascadable bus based crossbar switch in a programmable logic device |
| CN103049357B (en) * | 2011-10-12 | 2017-05-31 | 中盈创信(北京)商贸有限公司 | Electronic circuit product chip-scale maintenance intelligent detection card |
| CN105553498B (en) * | 2014-10-27 | 2018-04-03 | 天工方案公司 | With the interface related apparatus and method for radio-frequency module |
| CN205786868U (en) * | 2016-05-16 | 2016-12-07 | 深圳市广凯信科技有限公司 | Detect the detecting system of multiaspect multiport antenna for base station simultaneously |
| CN205786886U (en) * | 2016-05-16 | 2016-12-07 | 深圳市广凯信科技有限公司 | Detect the detecting system of multiple combiner simultaneously |
| US10698498B2 (en) * | 2017-11-30 | 2020-06-30 | Komodo OpenLab Inc. | Configurable device switching mechanism that enables seamless interactions with multiple devices |
| CN113726360B (en) * | 2020-05-26 | 2022-11-04 | Oppo广东移动通信有限公司 | Radio frequency PA Mid device, radio frequency transceiver and communication equipment |
| CN111766426A (en) * | 2020-06-24 | 2020-10-13 | 深圳市极致汇仪科技有限公司 | Method and system for flexibly realizing testing function of multi-port vector network analyzer |
| CN112952933A (en) * | 2021-02-03 | 2021-06-11 | 广州视源电子科技股份有限公司 | Interface expansion device, electronic device and interface expansion method |
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