CN114123139A - Failure protection method and device suitable for high-resistance fault - Google Patents
Failure protection method and device suitable for high-resistance fault Download PDFInfo
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
- H02H7/26—Sectionalised protection of cable or line systems, e.g. for disconnecting a section on which a short-circuit, earth fault, or arc discharge has occured
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Abstract
The invention relates to a failure protection method and a device suitable for high-resistance faults, wherein the judgment is as follows: condition 1, receiving a start-up failure open-in signal; condition 2, the phase current exceeds the upper limit value of the zero sequence current and the zero sequence current or the negative sequence current exceeds the upper limit value of the zero sequence current; condition 3, the phase voltage is lower than the threshold value or the zero sequence voltage is higher than the upper limit value or the negative sequence voltage is higher than the upper limit value, or the open failure voltage locking logic is established; the fail voltage lockout logic holds including: receiving a starting failure starting signal, wherein the zero sequence voltage change difference value is greater than the difference threshold, and the zero sequence current is greater than the zero sequence current when the tail end of the line fails; when the condition 1, the condition 2 and the condition 3 are all satisfied, after the delay time T, the failure protection action is executed. The invention improves the logic control of the failure protection, improves the sensitivity of the judgment logic of the failure protection voltage on the premise of not sacrificing the reliability of the protection, ensures that the failure protection can reliably act under various faults, and meets the requirement of a relay protection device on ensuring the safe and stable operation of a power grid.
Description
Technical Field
The invention relates to the technical field of power systems, in particular to a failure protection method and device suitable for high-resistance faults.
Background
The relay protection is used as a first line of defense line of the power system to ensure the safe and stable operation of the power system. When a power system has faults and the main protection tripping circuit breaker fails, the failure protection is used as a near backup protection, an adjacent circuit breaker can be tripped quickly, the power failure range is reduced as far as possible, and the stable operation of a power grid is guaranteed.
The failure protection comprises two aspects, namely, judging the failure of the circuit breaker by failure protection, namely, issuing a trip command to the circuit breaker by the protection, namely, receiving the failure starting and entering; the second is that the system is in fault, that is, the breaker has current in a period of time and the system voltage changes. The circuit breaker failure protection discrimination logic therefore comprises 3 parts: there is a start-up failure, open, there is a current (phase current, zero sequence current, or negative sequence current), bus voltage variation (low voltage, zero sequence voltage out-of-limit, negative sequence voltage out-of-limit). As shown in figure 1.
In the process of grounding and slowly climbing faults through the transition resistor, the grounding resistor is large, the influence on the system voltage is small, and the low voltage, the zero sequence voltage and the negative sequence voltage in the figure 1 do not meet action fixed values. If the breaker fails, the failure protection can not act quickly to isolate the fault, and the override trip of the upper-level power grid can be caused, so that the power supply reliability is influenced. How to guarantee to pass through transition resistance ground connection, slowly climb the trouble in-process, the circuit breaker is malfunctioning to fail the protection action reliability, is the technological problem that this field awaits urgent solution.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides a failure protection method and a failure protection device suitable for high-resistance faults.
In order to achieve the above object, the present invention provides a failure protection method for high resistance fault, comprising:
judging whether the conditions 1, 2 and 3 are satisfied; the condition 1 is satisfied and comprises receiving a start-failure open-in signal; the condition 2 is met, wherein the phase current exceeds the upper limit value of the phase current, and the zero sequence current or the negative sequence current exceeds the upper limit value of the zero sequence current; a condition 3 is established, including determining whether or not the condition 11 and the condition 12 are established, and when either of the condition 11 and the condition 12 is established, the condition 3 is established;
the satisfaction of the condition judgment condition 11 includes: the phase voltage is lower than a threshold value or the zero sequence voltage is higher than an upper limit value or the negative sequence voltage is higher than an upper limit value, or the open failure voltage locking logic is established;
determining that condition 12 holds includes: receiving a starting failure starting signal, wherein the zero sequence voltage change difference value is greater than the difference threshold, and the detected zero sequence current is greater than the zero sequence current when the tail end of the line fails;
when the condition 1, the condition 2 and the condition 3 are all satisfied, after the delay time T, the failure protection action is executed.
Further, if the difference between the current cycle current and the current before two cycles is higher than the first current deviation threshold, the zero sequence voltage of 3 cycles is calculated as the memorized zero sequence voltage, and the difference between the current zero sequence voltage and the memorized zero sequence voltage is calculated as the zero sequence voltage change difference. Further, the memorized zero sequence voltage is updated only once every 10 s.
Further, zero sequence voltage is calculated in real time, and N zero sequence voltage values are cached; after a starting failure starting signal of a certain phase is received, if the phase current of the phase is greater than the phase current starting lower limit, finding out the minimum value of the current cache N zero sequence voltage values as the memorized zero sequence voltage, and taking the difference value between the current zero sequence voltage and the memorized zero sequence voltage as the zero sequence voltage change difference value. Further, the memorized zero sequence voltage is updated only once every 10 s.
Further, T is 0.2-0.5 s; the difference threshold of the zero sequence voltage change difference value is 0.5V-1.5V, the zero sequence current of the line end In fault is 0.05 In-0.15 In, and In is the secondary rated current; the first current deviation threshold is 0.1In, and the lower limit of the phase current start-up is 0.05 In.
Furthermore, the broadening with the zero sequence voltage change difference value larger than the difference threshold is 0.5 s-1.2 s, and if a start failure open signal is received within 0.5 s-1.2 s and the zero sequence current is larger than the zero sequence current when the tail end of the line fails, the open failure voltage locking logic is established.
Another aspect provides a failsafe device suitable for high resistance faults, comprising:
the acquisition module acquires the current and the bus voltage of each phase of each line;
the first judgment module receives a failure starting-in signal and outputs a first signal;
the second judgment module outputs a second signal when the phase current exceeds the upper limit value of the second judgment module and the zero sequence current or the negative sequence current exceeds the upper limit value of the second judgment module;
the third judgment module outputs a third signal when the phase voltage is lower than a threshold value or the zero sequence voltage is higher than the upper limit value or the negative sequence voltage is higher than the upper limit value or the open failure voltage locking logic is established; the establishment of the open failure voltage blocking logic comprises the following steps: receiving a starting failure starting signal, wherein the zero sequence voltage change difference value is greater than the difference threshold, and the detected zero sequence current is greater than the zero sequence current when the tail end of the line fails;
and the action control module executes the failure protection action after delaying the time T when the first signal, the second signal and the third signal exist.
Further, the third determining module calculates that a difference between the current cycle current and the current before two cycles is higher than a first current deviation threshold, and then calculates a zero sequence voltage of 3 cycles as a memorized zero sequence voltage, and a difference between the current zero sequence voltage and the memorized zero sequence voltage as a zero sequence voltage change difference. Further, the memorized zero sequence voltage is updated only once every 10 s.
Further, the third judging module calculates zero sequence voltage in real time and caches N zero sequence voltage values; after a starting failure starting signal of a certain phase is received, if the phase current of the phase is greater than the phase current starting lower limit, finding out the minimum value of the current cache N zero sequence voltage values as the memorized zero sequence voltage, and taking the difference value between the current zero sequence voltage and the memorized zero sequence voltage as the zero sequence voltage change difference value. Further, the memorized zero sequence voltage is updated only once every 10 s.
Furthermore, the difference threshold of the zero sequence voltage change difference value is 1.5V, the zero sequence current of the line end In fault is 0.15In, and In is the rated current; the first current deviation threshold is 0.1In, and the lower limit of the phase current start-up is 0.05 In.
Further, the third judging module sets the broadening with the zero sequence voltage variation difference value larger than the difference threshold to be 1s, and if a start-up failure start-in signal is received in 1s and the zero sequence current is larger than the zero sequence current when the tail end of the line fails, the open failure voltage blocking logic is established.
A third aspect of the invention provides a computer readable storage medium having stored thereon program instructions which, when executed by a processor, implement the failsafe method for high impedance faults.
A fourth aspect of the invention provides a processing apparatus comprising a processor and a memory, the memory being for storing program instructions, the processor being for invoking the program instructions to perform the failsafe method applicable to high impedance faults.
The technical scheme of the invention has the following beneficial technical effects:
the invention improves the control of the failure protection logic by adding the failure voltage locking logic in the judgment logic. On the premise of not sacrificing the protection reliability, the judgment logic sensitivity of the failure protection voltage is improved, and the reliable action of the failure protection under the high-resistance fault is ensured, so that the requirement of a relay protection device for ensuring the safe and stable operation of a power grid is met.
Drawings
FIG. 1 is a schematic diagram of exemplary fail-safe logic;
FIG. 2 is a schematic diagram of the improved fail logic proposed by the present invention;
FIG. 3 is a schematic diagram of open failure voltage blocking logic according to the present invention;
FIG. 4 is a flow chart of 3U0 before a memory fault based on current change;
FIG. 5 is a flow chart of 3U0 before fault memory based on other protection behavior.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings in conjunction with the following detailed description. It should be understood that the description is intended to be exemplary only, and is not intended to limit the scope of the present invention. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present invention.
The invention judges the system voltage disturbance based on the voltage fault component change characteristics, determines the system fault and opens the failure voltage locking logic. On the basis of the existing protection logic, the failure voltage locking logic is added.
The invention provides a failure protection method suitable for high-resistance faults, which is combined with a figure 2, starts failure protection actions and simultaneously meets three conditions:
Condition 2, the phase current exceeds its upper limit value and the zero sequence current or negative sequence current exceeds its upper limit value.
A condition 3 including determining whether or not the condition 11 and the condition 12 are satisfied, wherein the condition 3 is satisfied when either the condition 11 or the condition 12 is satisfied; the satisfaction of the condition judgment condition 11 includes: the phase voltage is lower than a threshold value or the zero sequence voltage is higher than an upper limit value or the negative sequence voltage is higher than an upper limit value, or the open failure voltage blocking logic is established. Determining that condition 12 holds includes that the fail voltage lockout logic holds.
And when the condition 1, the condition 2 and the condition 3 are all satisfied, after the delay time is 0.2-0.5 s, executing the failure protection action. And if the three conditions are not met within 0.2-0.5 s, stopping executing the failure protection action.
With reference to fig. 3, the fail voltage blocking logic holds: and receiving a starting failure starting signal, wherein the zero sequence voltage change difference value is greater than the difference threshold, and the detected zero sequence current is greater than the zero sequence current when the tail end of the line fails. The zero sequence current of the line end In fault is 0.05-0.15 In, and the primary current is not more than 300A.
And (3) judging the variation of the zero-sequence voltage 3U0, namely the difference between the current 3U0 and the memorized 3U0, recording the variation as delta 3U0, judging the zero-sequence current of the failure breaker, and judging a failure starting signal (other protection of the failure breaker sends an over-trip command).
And (3) judging the change of the zero sequence voltage 3U0, namely judging the change sizes of the fault time 3U0 and the fault pre-3U 0, determining the 'fault pre' -time, and locking the 3U0 value at the moment. Determining the moment before the fault can be identified in two ways.
(1) And 3U0 before the fault is searched through the current change characteristic.
With reference to fig. 4, when a power system fails, the current changes more or less, and the system is determined to have failed through the current sudden change characteristics, and the system is advanced for a certain time to find the 3U0 before the failure by taking the current sudden change characteristics as a reference time point.
The implementation method comprises the following steps:
judging the current and the variation before 2 cycles (40ms) in real time.
Secondly, when the current change is larger than 0.1In, the system is considered to have a fault, and at the moment, the zero sequence voltage 3U0 value before 3 cycles (60ms) is calculated from the cached data to serve as the memorized zero sequence voltage.
3U0 of 3 cycles is calculated and then memorized, and is not recalculated within 10s, so that the calculation is taken as 3U0 before the fault to participate in logic operation.
(2) The pre-fault 3U0 is found by other protection action behaviors.
Referring to fig. 5, one of the conditions for judging the failure of the circuit breaker by the failure protection is that the protection sends an over-trip command to the circuit breaker, the protection device provides a starting failure contact for the failure protection while sending the over-trip command to the circuit breaker, and the failure protection searches for the zero sequence voltage 3U0 before the failure according to the signal of the starting failure contact.
The implementation method comprises the following steps:
firstly, zero sequence voltage 3U0 values are calculated in the protection operation, one zero sequence voltage 3U0 data is cached every 20ms, 200 data are cached continuously, and the total time is 4 s. The 200 data adopt a rolling storage mode, and the cache data are ensured to be 200 data in 4s before the current moment.
Secondly, after the failure protection receives the confirmation of a certain time (10ms) after the failure starting, other protection devices are considered to issue a tripping command to the circuit breaker.
And thirdly, judging that the current of the breaker is more than 0.05In at the moment so as to confirm that the breaker does not trip.
After receiving the fault starting and confirming the current, selecting the minimum value of 200 cached 3U0 data as the memorized zero sequence voltage, and not recalculating within 10s to be used as the 3U0 before the fault to participate in logic operation.
In implementation, the 3U0 before the fault is searched according to the current change and other protection action behaviors. And assigning the 3U0 data before the fault found by the two methods to the same intermediate data for open voltage locking logic judgment. The method aims to avoid the problem that the change quantity delta 3U0 of the zero sequence voltage is smaller than 1.5V in a short time due to the fact that the zero sequence voltage in the fault process becomes smaller, and then the action behavior of the failure protection is influenced. Therefore, the difference between the current 3U0 and the memory 3U0 is larger than 1.5V in the fault judgment, and the time is widened by 1 s.
On the other hand, the failure protection device suitable for the high-resistance fault comprises an acquisition module, a first judgment module, a second judgment module, a third judgment module and an action control module.
And the acquisition module acquires the current and the bus voltage of each phase of each line.
The first judgment module receives the failure starting-in signal and outputs a first signal.
And the second judgment module outputs a second signal when the phase current exceeds the upper limit value and the zero sequence current or the negative sequence current exceeds the upper limit value.
The third judgment module outputs a third signal when the phase voltage is lower than a threshold value or the zero sequence voltage is higher than the upper limit value or the negative sequence voltage is higher than the upper limit value or the open failure voltage locking logic is established; the establishment of the open failure voltage blocking logic comprises the following steps: and receiving a starting failure starting signal, wherein the zero sequence voltage change difference value is greater than the difference threshold, and the zero sequence current is greater than the zero sequence current when the tail end of the line fails.
And the action control module executes the failure protection action after delaying the time T when the first signal, the second signal and the third signal exist.
Further, the third determining module calculates that the difference between the current and the two cycle-front currents is higher than the first current deviation threshold, and then calculates the zero-sequence voltages of the 3 cycle-front currents as the memorized zero-sequence voltages, and calculates the difference between the current and the memorized zero-sequence voltages as the zero-sequence voltage variation difference. Further, the memorized zero sequence voltage is updated only once every 10 s.
Further, the third judging module calculates zero sequence voltage in real time and caches N zero sequence voltage values; after a starting failure starting signal of a certain phase is received, if the phase current of the phase is greater than the phase current starting lower limit, finding out the minimum value of the current cache N zero sequence voltage values as the memorized zero sequence voltage, and taking the difference value between the current zero sequence voltage and the memorized zero sequence voltage as the zero sequence voltage change difference value. Further, the memorized zero sequence voltage is updated only once every 10 s.
Further, the difference threshold of the zero sequence voltage change difference value is 1.5V, the zero sequence current of the line end In fault is 0.15In, and In is the secondary rated current; the first current deviation threshold is 0.1In, and the lower limit of the phase current start-up is 0.05 In.
Further, the third judging module sets the broadening with the zero sequence voltage variation difference value larger than the difference threshold to be 1s, and if a start failure opening signal is received in 1s and the zero sequence current is larger than the zero sequence current when the tail end of the line fails, the failure voltage blocking logic is established.
In summary, the present invention relates to a failure protection method and device for high resistance fault, which judges: condition 1, receiving a start-up failure open-in signal; condition 2, the phase current exceeds the upper limit value of the zero sequence current and the zero sequence current or the negative sequence current exceeds the upper limit value of the zero sequence current; condition 3, the phase voltage is lower than the threshold value or the zero sequence voltage is higher than the upper limit value or the negative sequence voltage is higher than the upper limit value, or the open failure voltage locking logic is established; the establishment of the open failure voltage blocking logic comprises the following steps: receiving a starting failure starting signal, wherein the zero sequence voltage change difference value is greater than the difference threshold, and the zero sequence current is greater than the zero sequence current when the tail end of the line fails; when the condition 1, the condition 2 and the condition 3 are all satisfied, after the delay time T, the failure protection action is executed. The invention improves the logic control of the failure protection, improves the sensitivity of the judgment logic of the failure protection voltage on the premise of not sacrificing the reliability of the protection, ensures the reliable action of the failure protection and meets the requirement of a relay protection device for ensuring the safe and stable operation of a power grid.
A third aspect of the invention provides a computer readable storage medium having stored thereon program instructions which, when executed by a processor, implement the failsafe method for high resistance faults.
A fourth aspect of the invention provides a processing apparatus comprising a processor and a memory, the memory being for storing program instructions, the processor being for invoking the program instructions to perform the failsafe method applicable to high impedance faults.
The memory may be a Read Only Memory (ROM), a static memory device, a dynamic memory device, or a Random Access Memory (RAM). The memory may store a program which, when executed by the processor, performs the steps of the method of image processing of an embodiment of the present invention, e.g. the steps of the embodiment shown in fig. 1 may be performed.
The processor may be a general-purpose Central Processing Unit (CPU), a microprocessor, an Application Specific Integrated Circuit (ASIC), or one or more integrated circuits, and is configured to execute related programs to implement the method for processing an image according to the embodiment of the present invention.
The processor may also be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the method of image processing according to the embodiment of the present invention may be implemented by integrated logic circuits of hardware in a processor or instructions in the form of software.
The processor may also be a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components. The various methods, steps and logic blocks disclosed in the embodiments of the present invention may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The steps of the method disclosed in connection with the embodiments of the present invention may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software module may be located in ram, flash memory, rom, prom, or eprom, registers, etc. storage media as is well known in the art. The storage medium is located in a memory, and a processor reads information in the memory and performs, in combination with hardware thereof, functions required to be performed by units included in the apparatus for image processing in the embodiment of the present invention.
The computer-readable storage medium may include, for example, a memory card of a smart phone, a storage component of a tablet computer, a hard disk of a personal computer, a Read Only Memory (ROM), an Erasable Programmable Read Only Memory (EPROM), a portable compact disc read only memory (CD-ROM), a USB memory, or any combination of the above storage media. The computer-readable storage medium may be any combination of one or more computer-readable storage media.
It is to be understood that the above-described embodiments of the present invention are merely illustrative of or explaining the principles of the invention and are not to be construed as limiting the invention. Therefore, any modification, equivalent replacement, improvement and the like made without departing from the spirit and scope of the present invention should be included in the protection scope of the present invention. Further, it is intended that the appended claims cover all such variations and modifications as fall within the scope and boundaries of the appended claims or the equivalents of such scope and boundaries.
Claims (10)
1. A method of failsafe for high resistance faults, comprising:
judging whether the conditions 1, 2 and 3 are satisfied; the condition 1 is satisfied and comprises receiving a start-failure open-in signal; the condition 2 is met, wherein the phase current exceeds the upper limit value of the phase current, and the zero sequence current or the negative sequence current exceeds the upper limit value of the zero sequence current; a condition 3 is established, including determining whether or not the condition 11 and the condition 12 are established, and when either of the condition 11 and the condition 12 is established, the condition 3 is established;
the satisfaction of the condition judgment condition 11 includes: the phase voltage is lower than a threshold value or the zero sequence voltage is higher than an upper limit value or the negative sequence voltage is higher than an upper limit value, or the open failure voltage locking logic is established;
determining that condition 12 holds includes: receiving a starting failure starting signal, wherein the zero sequence voltage change difference value is greater than the difference threshold, and the detected zero sequence current is greater than the zero sequence current when the tail end of the line fails;
when the condition 1, the condition 2 and the condition 3 are all satisfied, after the delay time T, the failure protection action is executed.
2. The fault protection method for high resistance faults according to claim 1, wherein if the difference between the current cycle current and the current before two cycles is calculated to be higher than the first current deviation threshold, then 3 cycles of zero sequence voltage are calculated as the memorized zero sequence voltage, and the difference between the current zero sequence voltage and the memorized zero sequence voltage is calculated as the zero sequence voltage variation difference. Further, the memorized zero sequence voltage is updated only once every 10 s.
3. The fault protection method for high resistance faults according to claim 1, characterized in that zero sequence voltages are calculated in real time and N zero sequence voltage values are buffered; after a starting failure starting signal of a certain phase is received, if the phase current of the phase is greater than the phase current starting lower limit, finding out the minimum value of the current cache N zero sequence voltage values as the memorized zero sequence voltage, and taking the difference value between the current zero sequence voltage and the memorized zero sequence voltage as the zero sequence voltage change difference value. Further, the memorized zero sequence voltage is updated only once every 10 s.
4. The fault protection method for high resistance fault according to claim 1 or 2, wherein T is 0.2-0.5 s; the difference threshold of the zero sequence voltage change difference value is 0.5V-1.5V, the zero sequence current of the line end In fault is 0.05 In-0.15 In, and In is the secondary rated current; the first current deviation threshold is 0.1In, and the lower starting limit of the phase current is 0.05 In;
the broadening with the zero sequence voltage change difference value larger than the difference threshold is 0.5 s-1.2 s, and if a starting failure starting signal is received within 0.5 s-1.2 s and the zero sequence current is larger than the zero sequence current when the tail end of the line fails, the open failure voltage locking logic is established.
5. A failsafe device suitable for high resistance faults, comprising:
the acquisition module acquires the current and the bus voltage of each phase of each line;
the first judgment module receives a failure starting-in signal and outputs a first signal;
the second judgment module outputs a second signal when the phase current exceeds the upper limit value of the second judgment module and the zero sequence current or the negative sequence current exceeds the upper limit value of the second judgment module;
the third judgment module is used for judging whether the phase voltage is lower than a threshold value or the zero sequence voltage is higher than the upper limit value or the negative sequence voltage is higher than the upper limit value and judging whether the open failure voltage locking logic is established or not; when the phase voltage is lower than the threshold value or the zero sequence voltage is higher than the upper limit value or the negative sequence voltage is higher than the upper limit value, or the open failure voltage locking logic is established, outputting a third signal; the establishment of the open failure voltage blocking logic comprises the following steps: receiving a starting failure starting signal, wherein the zero sequence voltage change difference value is greater than the difference threshold, and the detected zero sequence current is greater than the zero sequence current when the tail end of the line fails;
and the action control module executes the failure protection action after delaying the time T when the first signal, the second signal and the third signal exist.
6. The fault protection device for high resistance faults according to claim 5, wherein the third determining module calculates a difference value between the current cycle current and the two cycle-ahead currents to be higher than a first current deviation threshold value, and calculates a zero-sequence voltage of 3 cycle-ahead currents as a memorized zero-sequence voltage, and calculates a difference value between the current zero-sequence voltage and the memorized zero-sequence voltage as a zero-sequence voltage variation difference value. Further, the memorized zero sequence voltage is updated only once every 10 s.
7. The fault protection device for high resistance fault according to claim 6, wherein the third determining module calculates zero sequence voltage in real time and buffers N zero sequence voltage values; after a starting failure starting signal of a certain phase is received, if the phase current of the phase is greater than the phase current starting lower limit, finding out the minimum value of the current cache N zero sequence voltage values as the memorized zero sequence voltage, and taking the difference value between the current zero sequence voltage and the memorized zero sequence voltage as the zero sequence voltage change difference value. Further, the memorized zero sequence voltage is updated only once every 10 s.
8. The fault protection device for high-resistance faults according to claim 5 or 6, wherein the difference threshold of the zero sequence voltage variation difference value is 1.5V, the zero sequence current at the fault of the line end is 0.15In, and In is the secondary rated current; the first current deviation threshold is 0.1In, and the lower starting limit of the phase current is 0.05 In;
and the third judgment module sets the broadening with the zero sequence voltage change difference value larger than the difference threshold to be 1s, and if a starting failure starting signal is received within 1s and the zero sequence current is larger than the zero sequence current when the tail end of the line fails, the open failure voltage locking logic is established.
9. A computer-readable storage medium, characterized in that program instructions are stored in the computer-readable storage medium, which program instructions, when executed by a processor, implement the failsafe method for high impedance faults as claimed in one of claims 1 to 4.
10. A processing device comprising a processor and a memory, the memory storing program instructions, the processor being configured to invoke the program instructions to perform the failsafe method for high impedance faults of one of claims 1 to 4.
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