CN114121817B - Memory device and method of forming the same - Google Patents
Memory device and method of forming the same Download PDFInfo
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- CN114121817B CN114121817B CN202111208150.8A CN202111208150A CN114121817B CN 114121817 B CN114121817 B CN 114121817B CN 202111208150 A CN202111208150 A CN 202111208150A CN 114121817 B CN114121817 B CN 114121817B
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- 238000000034 method Methods 0.000 title claims abstract description 51
- 230000008093 supporting effect Effects 0.000 claims abstract description 81
- 239000000758 substrate Substances 0.000 claims abstract description 76
- 239000003990 capacitor Substances 0.000 claims description 64
- 238000005530 etching Methods 0.000 claims description 59
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- 239000004065 semiconductor Substances 0.000 description 9
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 7
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- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 5
- 229910052698 phosphorus Inorganic materials 0.000 description 5
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- 230000000717 retained effect Effects 0.000 description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
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- 238000000231 atomic layer deposition Methods 0.000 description 4
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- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
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- 229910015801 BaSrTiO Inorganic materials 0.000 description 1
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- 229910002370 SrTiO3 Inorganic materials 0.000 description 1
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- 229910001439 antimony ion Inorganic materials 0.000 description 1
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- 229910001449 indium ion Inorganic materials 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
Abstract
A memory device and method of forming the same, the method of forming, after forming a first sacrificial layer on a substrate, a stacked support layer on the first sacrificial layer, the stacked support layer including a first support layer and a second support layer on the first support layer, the first support layer having a plurality of first bump structures, the second support layer having a plurality of second bump structures, a corresponding one of the first bump structures and a corresponding one of the second bump structures above the first bump structures above each of the lower electrode contact structures, and the first bump structures and the second bump structures each including a bump top layer parallel to a surface of the substrate and a bump extension wall extending in a direction perpendicular to the surface of the substrate and connected to an edge of the bump top layer; and forming a second sacrificial layer on the laminated supporting layer. The support strength of the lower electrode layer is improved by forming the above-described specific structure laminated support structure.
Description
Technical Field
The present disclosure relates to the field of memory fabrication, and more particularly, to a memory device and a method for forming the same.
Background
Dynamic random access memory (Dynamic Random Access Memory, DRAM) is a semiconductor memory device commonly used in computers and consists of many repeated memory cells. Each memory cell typically includes a capacitor and a transistor having a gate connected to a word line, a drain connected to a bit line, and a source connected to the capacitor, a voltage signal on the word line being capable of controlling the transistor to turn on or off, thereby reading data information stored in the capacitor through the bit line, or writing data information to the capacitor through the bit line for storage.
The prior art provides a method for forming a DRAM, comprising: providing a substrate; forming a first sacrificial layer on the substrate; forming a support layer on the first sacrificial layer; forming a second sacrificial layer on the support layer; etching to remove part of the first sacrificial layer, the supporting layer and the first sacrificial layer to form a plurality of capacitance holes; forming a lower electrode on the sidewall and bottom surface of the capacitor hole; after forming the lower electrode, removing the residual first sacrificial layer, the second sacrificial layer and part of the supporting layer to form a cavity; forming a dielectric layer on the surface of the lower electrode and the surface of the side wall of the cavity; an upper electrode is formed on the surface of the dielectric layer.
However, in the DRAM process formed by the above method, the supporting strength of the supporting layer on the capacitor needs to be improved, which affects the structural stability of the capacitor.
Disclosure of Invention
In view of this, some embodiments of the present application provide a method for forming a memory device, including:
Providing a substrate, wherein a plurality of lower electrode contact structures are formed in the substrate;
Forming a first sacrificial layer on the substrate;
Forming a laminated support layer on the first sacrificial layer, wherein the laminated support layer comprises a first support layer and a second support layer positioned on the first support layer, the first support layer is provided with a plurality of first protruding structures, the second support layer is provided with a plurality of second protruding structures, one first protruding structure and a second protruding structure positioned above the first protruding structure are respectively arranged above each lower electrode contact structure, and each of the first protruding structure and the second protruding structure comprises a protruding top layer parallel to the surface of the substrate and a protruding extension wall extending along the direction vertical to the surface of the substrate and connected with the edge of the protruding top layer;
Forming a second sacrificial layer on the laminated support layer;
Etching to remove part of the second sacrificial layer, the laminated supporting layer and the first sacrificial layer above the lower electrode contact structure, forming a plurality of capacitance holes exposing the surfaces of the corresponding lower electrode contact structure in the first sacrificial layer, the laminated supporting layer and the second sacrificial layer, and reserving the protruding extension walls of the first protruding structure and the second protruding structure on the side walls of the capacitance holes during etching;
Forming a lower electrode on the side wall and the bottom surface of the capacitor hole;
After forming the lower electrode, removing the remaining first sacrificial layer and second sacrificial layer to form a cavity;
forming a dielectric layer on the surface of the lower electrode and the surface of the cavity in the capacitor hole;
An upper electrode is formed on the dielectric layer.
In some embodiments, a respective one of the first raised structures and one of the second raised structures above each of the lower electrode contact structures are raised in a direction toward the substrate.
In some embodiments, the forming of the stacked support layer includes: etching to remove part of the first sacrificial layer, forming a plurality of first sacrificial layer bulges and first grooves positioned between the first sacrificial layer bulges on the top of the first sacrificial layer, wherein the first grooves are positioned above the corresponding lower electrode contact structures; forming a first support layer on the side wall and the top surface of the first sacrificial layer bulge and on the bottom surface of the first groove between the first sacrificial layer bulges; forming a third sacrificial layer bump on the first support layer surface on the top surface of the first sacrificial layer bump; and forming a second support layer on the side wall and the top surface of the third sacrificial layer protrusion and the first support layer between the third sacrificial layer protrusions.
In some embodiments, the third sacrificial layer protrusion is formed by: forming a third sacrificial layer on the surface of the first supporting layer; and etching to remove part of the third sacrificial layer, and forming a third sacrificial layer protrusion on the surface of the first supporting layer on the top surface of the first sacrificial layer protrusion.
In some embodiments, the third sacrificial layer in the first recess between adjacent first sacrificial layer protrusions is retained or removed while etching away a portion of the third sacrificial layer; when forming the second supporting layer, the part of the second supporting layer is positioned on the surface of the third sacrificial layer which is reserved in the first grooves between the adjacent first sacrificial layer bulges or is directly positioned on the surface of the first supporting layer in the first grooves.
In some embodiments, the third sacrificial layer is removed simultaneously with the removal of the remaining first and second sacrificial layers to form a cavity.
In some embodiments, etching to remove portions of the second sacrificial layer and the stacked support layer above the lower electrode contact structure and the first sacrificial layer, forming a plurality of capacitor holes in the first sacrificial layer, the stacked support layer and the second sacrificial layer exposing surfaces of the respective lower electrode contact structures, and leaving the protruding extension walls of the first protruding structures and the second protruding structures on the sidewalls of the capacitor holes comprises: etching a part of the second sacrificial layer and the first sacrificial layer above the corresponding lower electrode contact structure and the protruding top layer of the first protruding structure and the second protruding structure or etching a part of the second sacrificial layer and the first sacrificial layer above the corresponding lower electrode contact structure and the protruding top layer and the third sacrificial layer of the first protruding structure and the second protruding structure, forming a plurality of capacitance holes exposing the corresponding lower electrode contact structure in the first sacrificial layer, the second sacrificial layer and the laminated supporting layer, and reserving the protruding extension walls of the first protruding structure and the second protruding structure on the side walls of the capacitance holes during etching.
In some embodiments, a respective one of the first raised structures and one of the second raised structures above each of the lower electrode contact structures are raised away from the substrate.
In some embodiments, the forming of the stacked support layer includes: etching to remove part of the first sacrificial layer, forming a plurality of second sacrificial layer bulges and second grooves positioned between the second sacrificial layer bulges at the top of the first sacrificial layer, wherein the second sacrificial layer bulges are positioned above corresponding lower electrode contact structures; forming a first support layer on the side wall and the top surface of the second sacrificial layer bulge and on the bottom surface of the second groove between the second sacrificial layer bulges; forming a third sacrificial layer bump on the first support layer surface on the top surface of the second sacrificial layer bump; and forming a second support layer on the side wall and the top surface of the third sacrificial layer protrusion and the first support layer between the third sacrificial layer protrusions.
In some embodiments, the third sacrificial layer protrusion is formed by: forming a third sacrificial layer on the surface of the first supporting layer; and etching to remove part of the third sacrificial layer, and forming a third sacrificial layer protrusion on the surface of the first supporting layer on the top surface of the first sacrificial layer protrusion.
In some embodiments, the third sacrificial layer in the second recess between adjacent second sacrificial layer protrusions is retained or removed while etching away a portion of the third sacrificial layer; when forming the second supporting layer, the part of the second supporting layer is positioned on the surface of the reserved third sacrificial layer in the second grooves between the adjacent second sacrificial layer bulges or is directly positioned on the surface of the first supporting layer in the second grooves.
In some embodiments, the third sacrificial layer is removed simultaneously with the removing of the remaining first and second sacrificial layers to form a cavity.
In some embodiments, etching to remove portions of the second sacrificial layer and the stacked support layer above the lower electrode contact structure and the first sacrificial layer, forming a plurality of capacitor holes in the first sacrificial layer, the stacked support layer and the second sacrificial layer exposing surfaces of the respective lower electrode contact structures, and leaving the protruding extension walls of the first protruding structures and the second protruding structures on the sidewalls of the capacitor holes comprises: etching part of the second sacrificial layer, the first sacrificial layer and the third sacrificial layer protruding above the corresponding lower electrode contact structure and the protruding top layer of the first protruding structure and the second protruding structure or etching part of the second sacrificial layer and the first sacrificial layer above the corresponding lower electrode contact structure and the protruding top layer of the first protruding structure and the protruding top layer of the third sacrificial layer and the second sacrificial layer protruding, forming a plurality of capacitor holes exposing the corresponding lower electrode contact structure in the first sacrificial layer, the second sacrificial layer and the laminated supporting layer, and reserving the protruding extension walls of the first protruding structure and the second protruding structure on the side walls of the capacitor holes during etching.
In some embodiments, further comprising: and forming a top supporting layer on the second sacrificial layer.
In some embodiments, when forming the plurality of capacitor holes, etching is performed to remove a portion of the top supporting layer above the lower electrode contact structure, so as to expose a surface of a portion of the second sacrificial layer above the corresponding lower electrode contact structure.
In some embodiments, before removing the remaining first sacrificial layer and second sacrificial layer, removing a portion of the remaining top support layer between adjacent capacitive holes exposes a surface of the remaining second sacrificial layer between adjacent capacitive holes.
Some embodiments of the present invention also provide a memory device including:
a substrate in which a plurality of lower electrode contact structures are formed;
A plurality of U-shaped lower electrodes connected with the corresponding lower electrode contact structures;
the laminated support layers are positioned on the outer side walls of the plurality of lower electrodes, each laminated support layer comprises a first support layer and a second support layer positioned on the first support layer, the contact parts of the first support layer and the second support layer with the outer side walls of the lower electrodes comprise convex extension walls extending along the direction vertical to the surface of the substrate, and the convex extension walls of the first support layer are connected with the convex extension walls of the second support layer;
dielectric layers on the inner wall side and outer side wall surfaces of the lower electrode;
an upper electrode on the surface of the dielectric layer.
In some embodiments, the first support layer between portions of the lower electrode has a first raised structure, the second support layer has a second raised structure, the second raised structure and located above the first raised structure, and the first raised structure and the second raised structure each include a raised top layer parallel to the substrate surface and raised extension walls connected to edges of the raised top layer and located on sidewall surfaces of respective capacitive holes and extending in a direction perpendicular to the substrate surface.
In some embodiments, the first and second raised structures are raised away from the substrate surface, a third cavity is between the raised top layer of the first raised structure and the raised top layer of the second raised structure, the dielectric layer is also located on a sidewall surface of the third cavity, and a surface of the dielectric layer in the third cavity is also provided with an upper electrode layer.
In some embodiments, the first bump structure and the second bump structure are bump in a direction close to the substrate surface, the bump top layer of the first bump structure is in contact with the bump top layer of the second bump structure or a third cavity is provided between the bump top layer of the first bump structure and the bump top layer of the second bump structure, the dielectric layer is further located on a side wall surface of the third cavity, and a surface of the dielectric layer in the third cavity is further provided with an upper electrode layer.
In the method for forming a memory device according to the foregoing embodiments of the present application, after forming a first sacrificial layer on a substrate, a stacked support layer is formed on the first sacrificial layer, the stacked support layer includes a first support layer and a second support layer located on the first support layer, the first support layer has a plurality of first bump structures, the second support layer has a plurality of second bump structures, a corresponding one of the first bump structures and a corresponding one of the second bump structures located above the first bump structures is located above each of the lower electrode contact structures, and each of the first bump structure and the second bump structure includes a bump top layer parallel to a surface of the substrate and a bump extension wall extending in a direction perpendicular to the surface of the substrate and connected to an edge of the bump top layer; and forming a second sacrificial layer on the laminated supporting layer. By forming the laminated supporting structure with the specific structure, when the capacitor hole is formed later, the protruding extension arms of the first protruding structure and the second protruding structure can remain on the side wall of the capacitor hole, and when the lower electrode layer is formed on the side wall and the bottom surface of the capacitor hole, the contact area between the laminated supporting structure and the lower electrode layer can be increased, so that the supporting strength of the lower electrode layer is improved.
Further, in some embodiments, a third sacrificial layer protrusion may be further disposed between the first support layer and the second support layer, when the thicknesses of the first support layer and the second support layer are thinner, the whole stacked support structure still has strong mechanical stability, so that the stacked support structure can maintain a strong supporting effect on the lower electrode layer, and the third sacrificial layer protrusion may be removed to form a third cavity, in which a part of the dielectric layer and the upper electrode layer may be formed, so that in the case of a support layer with the same thickness, the stacked support structure has the third cavity to form a part of the dielectric layer and the upper electrode layer, thereby improving the capacitance value of the capacitor.
Drawings
FIGS. 1-14 are schematic diagrams illustrating a memory structure formation process according to some embodiments of the application;
fig. 15-25 are schematic diagrams illustrating a process of forming a memory structure according to further embodiments of the present application.
Detailed Description
As to the background art, in the existing DRAM formation process, the supporting strength of the supporting layer on the capacitor needs to be improved, which affects the structural stability of the capacitor.
It is found that, although increasing the thickness of the support layer can increase the support strength of the support layer, the support layer occupies a larger space, the capacitance value of the capacitor is reduced, and a thicker support layer requires a longer etching time, which causes larger etching damage to the top of the lower electrode layer.
In this regard, the application provides a memory device and a method for forming the same, which can make the thinner support layer have stronger support strength to the capacitor, improve the structural stability of the capacitor, ensure the capacitance value of the capacitor and reduce the damage to the top of the lower electrode layer.
In order that the above objects, features and advantages of the application will be readily understood, a more particular description of the application will be rendered by reference to the appended drawings. In describing embodiments of the present application in detail, the schematic drawings are not necessarily to scale and are merely illustrative and should not be taken as limiting the scope of the application. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
Referring to fig. 1, a substrate 200 is provided, and a plurality of lower electrode contact structures are formed in the substrate 200.
The substrate 200 serves as a platform for subsequent processing.
In some embodiments, the base 200 may include a semiconductor substrate 201 and an underlying dielectric layer 202 on the semiconductor substrate 201, where the material of the semiconductor substrate 201 may be silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); silicon On Insulator (SOI), germanium On Insulator (GOI); or may be other materials such as III-V compounds such as gallium arsenide. The semiconductor substrate is doped with certain impurity ions according to the need, the impurity ions can be N-type impurity ions or P-type impurity ions, the N-type impurity ions are one or more of phosphorus ions, arsenic ions or antimony ions, and the P-type impurity ions are one or more of boron ions, gallium ions or indium ions. In this embodiment, the material of the semiconductor substrate 201 is silicon. A number of trench transistors may be formed in the semiconductor substrate as part of a DRAM memory device. Specifically, the trench transistor includes an active region in the semiconductor substrate 201, at least one buried gate in the active region, a middle drain region and at least one source region of the active region on both sides of the buried gate.
The bottom dielectric layer 202 may be a single layer or a multi-layer stack structure. A plurality of lower electrode contact structures 220 are formed in the bottom dielectric layer 202, and the lower electrode contact structures 220 may be used to connect a lower electrode layer of a capacitor formed later and a source electrode of a trench transistor formed in the semiconductor substrate 201.
In some embodiments, the bottom dielectric layer 202 may be a single layer structure formed by one of silicon oxide, silicon nitride, silicon oxynitride, FSG (fluorine doped silicon dioxide), BSG (boron doped silicon dioxide), PSG (phosphorus doped silicon dioxide) or BPSG (boron doped phosphorus silicon dioxide), a low dielectric constant material, or a stacked layer structure formed by two or more materials in the group formed by the above materials. In this embodiment, the bottom dielectric layer 202 is a single layer structure of silicon nitride, or at least the top layer is a stacked layer structure of silicon nitride.
In some embodiments, the lower electrode contact structure 220 may include one or both of a metal plug and a metal pad. The material of the lower electrode contact structure 220 is metal. In some embodiments, the bottom electrode contact structure 220 may be a single layer structure formed by one material of W, al, cu, ag, au, co, pt, ni, ti, ta, tiN, taN or a stacked structure formed by two or more materials of the group (such as a dual layer stacked structure formed by a TiN layer and a W layer on the TiN layer).
In some embodiments, the formed lower electrode contact structure 220 is located entirely within the underlying dielectric layer 202, i.e., the top surface of the lower electrode contact structure 220 is lower than the top surface of the underlying dielectric layer 202.
Referring to fig. 2, a first sacrificial layer 205 is formed on the substrate 200.
The first sacrificial layer 205 is subsequently used to form a capacitor hole and a capacitor. The first sacrificial layer may be a single-layer or multi-layer stacked structure. The material of the first sacrificial layer 205 is different from the material of the bottom dielectric layer and the subsequently formed first support layer and second support layer, and the etching amount of the first support layer 206 and the bottom dielectric layer 202 is small or negligible when the first sacrificial layer 205 is etched later. In some embodiments, the first sacrificial layer 205 may be a single layer structure formed by one material of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, carbon, boron doped silicon oxide, phosphorus doped silicon oxide, boron nitride, silicon germanium, polysilicon, amorphous silicon, amorphous carbon, or a stacked layer structure formed by two or more materials in the group consisting of the above materials. In this embodiment, the first sacrificial layer 205 is a single layer structure of silicon oxide, and the first sacrificial layer 205 is formed by a chemical vapor deposition process.
Referring to fig. 7, a stacked support layer is formed on the first sacrificial layer 205, the stacked support layer including a first support layer 207 and a second support layer 210 on the first support layer 207, the first support layer 207 having a plurality of first bump structures 227, the second support layer 210 having a plurality of second bump structures 230, a corresponding one of the first bump structures 227 and the second bump structures 230 above the first bump structures 227 above each of the lower electrode contact structures 220, and the first bump structures 227 and the second bump structures 230 each including a bump top layer (26, 29) parallel to the surface of the substrate and bump extension walls (27, 30) extending in a direction perpendicular to the surface of the substrate 200 and connected to edges of the bump top layer (26, 29).
In this embodiment, the first protruding structures 227 in the first support layer 207 and the second protruding structures 230 in the second support layer 210 are protruding in a direction approaching the substrate 200. The first bump structure 227 includes a (first) bump top layer 26 parallel to the surface of the substrate 200 and a (first) bump extension wall 27 extending in a direction perpendicular to the surface of the substrate 200 and connected to an edge of the (first) bump top layer 26. The second bump structure 230 includes a (second) bump top layer 29 parallel to the substrate surface and a (second) bump extension wall 30 extending in a direction perpendicular to the substrate 200 surface and connected to an edge of the (second) bump top layer 29.
In this embodiment, the second bump structure 230 is partially located in the first bump structure 227, the bump top layer 29 of the second bump structure 230 is in contact with the bump top layer 30 of the first bump structure 227, and the portion of the bump extension wall 30 of the second bump structure 230 is in contact with the bump extension wall 27 of the first bump structure 227.
The process of forming the aforementioned laminate support layer is described in detail below in connection with fig. 3-7 in some embodiments.
Referring to fig. 3, a portion of the first sacrificial layer 205 is etched away, a plurality of first sacrificial layer protrusions 226 and first grooves 206 located between the first sacrificial layer protrusions 226 are formed on top of the first sacrificial layer 205, and the first grooves 206 are located above the corresponding lower electrode contact structures 220.
The first sacrificial layer 205 is etched using an anisotropic dry etching process, including an anisotropic plasma etching process.
Referring to fig. 4, a first support layer 207 is formed on the sidewalls and top surfaces of the first sacrificial layer protrusions 226 and the surface of the first groove bottom 206 between the first sacrificial layer protrusions 226.
The first support layer 207 is formed as a part of the stacked support layers, and the first support layer 207 is formed to have a plurality of first protrusion structures 227 protruding in a direction approaching the substrate 200. Each of the first bump structures 227 includes a (first) bump top layer 26 parallel to the substrate surface and a (first) bump extension wall 27 extending in a direction perpendicular to the substrate 200 surface and connected to an edge of the (first) bump top layer 26.
The thickness of the first support layer 207 may be relatively thin, and in some embodiments, the thickness of the first support layer 207 may be 5-100 nanometers. In some embodiments, the first support layer 207 material may be silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride. The material of the second support layer 206 in this embodiment is silicon nitride, and the forming process is an Atomic Layer Deposition (ALD) process.
Referring to fig. 5 and 6, a third sacrificial layer 208 (refer to fig. 5) is formed on the surface of the first support layer 207; and etching to remove part of the third sacrificial layer 208, and forming a third sacrificial layer protrusion 209 on the surface of the first support layer 207 on the top surface of the first sacrificial layer protrusion.
The material of the third sacrificial layer 208 is different from the material of the first support layer 207 and the subsequently formed second support layer. In some embodiments, the third sacrificial layer 208 may be a single layer structure formed by one material of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, carbon, boron doped silicon oxide, phosphorus doped silicon oxide, boron nitride, silicon germanium, polysilicon, amorphous silicon, amorphous carbon, or a stacked layer structure formed by two or more materials in the group consisting of the above materials. In this embodiment, the third sacrificial layer 208 has a single-layer structure of silicon oxide.
In this embodiment, when a portion of the third sacrificial layer 208 is etched and removed, the third sacrificial layer in the first recess between adjacent first sacrificial layer protrusions is removed, and then when a second supporting layer is formed, the portion of the second supporting layer is directly located on the surface of the first supporting layer in the first recess.
In other embodiments, the third sacrificial layer in the first recess between adjacent first sacrificial layer protrusions is preserved while etching away a portion of the third sacrificial layer 208, the preserved third sacrificial layer in the first recess having a surface lower than or flush with a surface of the first supporting layer on the top surface of the first sacrificial layer protrusions, and the portion of the second supporting layer is located on the preserved third sacrificial layer in the first recess between the adjacent first sacrificial layer protrusions when the second supporting layer is subsequently formed.
Referring to fig. 7, a second support layer 210 is formed on the sidewalls and top surfaces of the third sacrificial layer protrusions 209 and the first support layer between the third sacrificial layer protrusions 209.
The second support layer 210 is formed as a part of the stacked support layers, and the second support layer 210 is formed to have a plurality of second protrusion structures 230 protruding in a direction approaching the substrate 200. Each of the second bump structures 230 includes a (second) bump top layer 29 parallel to the substrate surface and a (second) bump extension wall 30 extending in a direction perpendicular to the substrate 200 surface and connected to an edge of the (second) bump top layer 29.
The thickness of the second support layer 210 may be relatively thin, and in some embodiments, the thickness of the second support layer 210 may be 5-100nm. In some embodiments, the second support layer 210 material may be silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, or silicon carbonitride. The material of the second support layer 210 in this embodiment is silicon nitride, and the forming process is an Atomic Layer Deposition (ALD) process.
In this embodiment, a portion of the second support layer 210 is formed directly on the surface of the first support layer 207 in the first recess. In other embodiments, when the second support layer is formed with a portion of the third sacrificial layer remaining in the first recess between adjacent first sacrificial layer protrusions, a portion of the second support layer is located on the surface of the remaining third sacrificial layer in the first recess between the adjacent first sacrificial layer protrusions.
In the application, the laminated supporting structure with the specific structure is formed by the method, and when the capacitor hole is formed later, the first protruding structure 227 and the protruding extension arms (27, 30) of the second protruding structure 230 are reserved on the side wall of the capacitor hole, and when the lower electrode layer is formed on the side wall and the bottom surface of the capacitor hole, the contact area between the laminated supporting structure and the lower electrode layer is increased, so that the supporting strength of the lower electrode layer is improved. Further, the third sacrificial layer bulge is arranged between the first supporting layer and the second supporting layer, when the thicknesses of the first supporting layer and the second supporting layer are thinner, the whole stacked supporting structure still has strong mechanical stability, so that the stacked supporting structure can keep strong supporting effect on the lower electrode layer, the third sacrificial layer bulge can be removed to form a third cavity, and part of dielectric layers and upper electrode layers can be formed in the third cavity, therefore, under the condition of supporting layers with the same thickness, the capacitance value of the capacitor can be improved due to the fact that the third cavity is formed in the stacked supporting structure to form part of dielectric layers and upper electrode layers.
Referring to fig. 8, a second sacrificial layer 211 is formed on the stack supporting layer.
The second sacrificial layer 211 is subsequently used to form a capacitor hole and a capacitor. The second sacrificial layer may be a single-layer or multi-layer stacked structure. The material of the second sacrificial layer 211 is different from the material of the second supporting layer 210 and the subsequently formed top supporting layer, and the etching amount of the second supporting layer 210 and the subsequently formed top supporting layer is small or negligible when the second sacrificial layer 211 is etched later. In some embodiments, the second sacrificial layer 211 may be a single layer structure formed by one material of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, carbon, boron doped silicon oxide, phosphorus doped silicon oxide, boron nitride, silicon germanium, polysilicon, amorphous silicon, amorphous carbon, or a stacked structure formed by two or more materials in the group consisting of the above materials. In this embodiment, the second sacrificial layer 211 is a single layer structure of silicon oxide, and the second sacrificial layer 211 is formed by a chemical vapor deposition process.
In some embodiments, after forming the second sacrificial layer 211, a top support layer 212 is formed on the second sacrificial layer 211.
The top support layer 212 also serves to support the capacitor structure. In some embodiments, the top supporting layer 212 may be a single layer structure formed by one material of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride, or a stacked structure formed by two or more materials of the group. The top support layer 212 in this embodiment is a single layer of silicon nitride.
Referring to fig. 9, a portion of the top support layer 212, a portion of the second sacrificial layer 211 and the stacked support layer, and the first sacrificial layer 205 above the lower electrode contact structure 220 are etched away, a plurality of capacitor holes 213 exposing the surfaces of the corresponding lower electrode contact structure 220 are formed in the first sacrificial layer 205, the stacked support layer, and the second sacrificial layer 211, and the protruding extension walls (27, 30) of the first and second protruding structures remain on the sidewalls of the capacitor holes 213 when etched.
In some embodiments, the etching is an anisotropic dry etching process, including an anisotropic plasma etching process.
In some embodiments, the specific process of etching includes: etching a portion of the second sacrificial layer and the first sacrificial layer above the corresponding lower electrode contact structure 220 and a portion of the bump top layer of the first bump structure and the second bump structure or etching a portion of the second sacrificial layer and the first sacrificial layer above the corresponding lower electrode contact structure 220 and a portion of the bump top layer and the third sacrificial layer of the first bump structure and the second bump structure, forming a plurality of capacitor holes 213 in the first sacrificial layer, the second sacrificial layer and the stacked support layer exposing the corresponding lower electrode contact structure 220, and retaining the bump extension walls of the first bump structure and the second bump structure at sidewalls of the capacitor holes when etching.
In some embodiments, when forming the plurality of capacitor holes 213, a portion of the top supporting layer 212 above the bottom electrode contact structure 220 is etched first to expose a surface of a portion of the second sacrificial layer 211 above the corresponding bottom electrode contact structure 220.
Referring to fig. 10, a lower electrode 214 is formed on the sidewall and bottom surface of the capacitor hole 213.
In some embodiments, the bottom electrode 214 may be a single layer formed of one material of W, al, cu, ag, au, co, pt, ni, ti, ta, tiN, taN, taC, taSiN, niSi, coSi, tiAl, WSi or a stacked layer formed of two or more materials of the group. The resistivity of the lower electrode 214 may be between 2×10 -8 (Ω m) and 1×10 2 (Ω m). In this embodiment, the bottom electrode 214 is a TiN layer.
The lower electrode 214 is formed in a "U" shape.
Referring to fig. 11-14, after the lower electrode 214 is formed, the remaining first and second sacrificial layers are removed to form cavities (216, 218, 219).
The following describes a specific process for forming the cavity, which includes: referring to fig. 11, before removing the remaining first sacrificial layer and second sacrificial layer, a portion of the remaining top support layer 212 between adjacent capacitor holes 213 is removed, forming surface etching holes exposing the remaining second sacrificial layer 211 between adjacent capacitor holes 213. Before removing the portion of the top support layer 212, a patterned mask layer is formed over the top support layer 212 and the capacitor holes, the patterned mask layer having openings therein exposing a portion of the top support layer between adjacent capacitor holes 213 that needs to be removed.
Referring to fig. 12, the second sacrificial layer is removed along the etched holes to form a second cavity 216. And removing the second sacrificial layer by wet etching.
Referring to fig. 13, the second support layer 210, the third sacrificial layer bump 209 and the first support layer 207 are partially removed along the etching hole and the corresponding first cavity 216 by using an anisotropic dry etching process, and during etching, the bump extension wall 30 in the second support layer 210 and the bump extension wall 27 in the first support layer 207 remain on the outer sidewall of the "U" shaped lower electrode 214.
Referring to fig. 3, a wet etching process is used to remove the remaining third sacrificial layer protrusion 209, a third cavity 218 is formed at a corresponding position, the remaining first sacrificial layer is removed, a first cavity 219 is formed at a corresponding position, and the first cavity 219, the second cavity 216, and the third cavity 218 form a cavity.
In some embodiments, after forming the cavity, further comprising: forming a dielectric layer on the surface of the lower electrode 214 and the surfaces of the cavities (the first cavity 219, the second cavity 216 and the third cavity 218) in the capacitor hole 213; an upper electrode is formed on the dielectric layer.
In some embodiments, the material of the dielectric layer is a high K (K greater than 2.8) dielectric material to increase the capacitance value of the capacitor per unit area. In a specific embodiment, the dielectric layer may be a single layer structure formed by one material of HfO2、TiO2、HfZrO、HfSiNO、Ta2O5、ZrO2、ZrSiO2、Al2O3、SrTiO3 or BaSrTiO or a stacked layer structure formed by two or more materials of the above group. In this embodiment, the dielectric layer is a HfO 2 layer.
In some embodiments, the upper electrode W, al, cu, ag, au, co, pt, ni, ti, ta, tiN, taN, taC, taSiN, niSi, coSi, tiAl, WSi has a single layer structure formed of one material or a stacked layer structure formed of two or more materials selected from the group consisting of the above materials. The upper electrode layer may have a resistivity of between 2×10 -8 (Ω m) and 1×10 2 (Ω m). In this embodiment, the upper electrode layer is a TiN layer.
In other embodiments of the present invention, referring to fig. 15-25, there is further provided a method for forming a storage structure, where the main difference between the embodiment and the previous embodiment is that the protruding directions of the first protruding structures and the second protruding structures are different, and a corresponding one of the first protruding structures and the second protruding structures above each of the lower electrode contact structures protrudes in a direction away from the substrate. It should be noted that, when the following description is given in this embodiment, detailed description and limitation of the same or similar structures as those in the foregoing embodiment will not be repeated, and specific reference is made to the foregoing embodiment.
Referring to fig. 15, a substrate 300 is provided, and a plurality of lower electrode contact structures 330 are formed in the substrate 300; forming a first sacrificial layer 305 on the substrate 300; and etching to remove part of the first sacrificial layer 305, forming a plurality of second sacrificial layer protrusions 326 and second grooves 306 between the second sacrificial layer protrusions 326 on the top of the first sacrificial layer 305, wherein the second sacrificial layer protrusions 326 are positioned above the corresponding lower electrode contact structures.
Referring to fig. 16, a first support layer 307 is formed on the sidewalls and top surfaces of the second sacrificial layer protrusions and the bottom surfaces of the second grooves between the second sacrificial layer protrusions, the first support layer 307 being formed with a plurality of first protrusion structures 327 protruding in a direction away from the substrate 300. Each of the first bump structures 327 (refer to fig. 19) includes a (first) bump top layer 26 parallel to the substrate surface and a (first) bump extension wall 27 extending in a direction perpendicular to the substrate 200 surface and connected to an edge of the (first) bump top layer 26.
Referring to fig. 17 and 18, a third sacrificial layer 308 (refer to fig. 17) is formed on the surface of the first support layer 307; and etching to remove part of the third sacrificial layer 308, and forming a third sacrificial layer protrusion 309 on the surface of the first support layer 307 on the top surface of the second sacrificial layer protrusion.
In this embodiment, when a portion of the third sacrificial layer 308 is etched and removed, the third sacrificial layer in the second recess between the adjacent second sacrificial layer protrusions is retained, and the surface of the retained third sacrificial layer 328 in the second recess is lower than or flush with the surface of the first supporting layer on the top surface of the second sacrificial layer protrusions, and when the second supporting layer is subsequently formed, the portion of the second supporting layer is located on the surface of the retained third sacrificial layer in the first recess between the adjacent second sacrificial layer protrusions.
In other embodiments, when a portion of the third sacrificial layer 308 is etched away, the third sacrificial layer in the second recess between adjacent second sacrificial layer protrusions is removed, and then when a second support layer is formed, the portion of the second support layer is directly located on the surface of the first support layer in the second recess.
Referring to fig. 19, a second support layer 310 is formed on the sidewalls and top surfaces of the third sacrificial layer protrusions and the first support layer 307 between the third sacrificial layer protrusions, the formed second support layer 310 having a plurality of second protrusion structures 330 protruding in a direction away from the substrate 300. Each of the second bump structures 330 includes a (second) bump top layer 29 parallel to the substrate surface and a (second) bump extension wall 30 extending in a direction perpendicular to the substrate 300 surface and connected to an edge of the (second) bump top layer 29.
Referring to fig. 20, a second sacrificial layer 311 is formed on the stack supporting layer; after the second sacrificial layer 311 is formed, a top support layer 312 is formed on the second sacrificial layer 311.
Referring to fig. 21, a portion of the top support layer 312, a portion of the second sacrificial layer 311 and the stacked support layer, and the first sacrificial layer 305 above the lower electrode contact structure 320 are etched away, a plurality of capacitance holes 313 exposing the surfaces of the corresponding lower electrode contact structure 320 are formed in the first sacrificial layer 305, the stacked support layer, and the second sacrificial layer 311, and the protruding extension walls (27, 30) of the first and second protruding structures remain on the sidewalls of the capacitance holes 313 when etched.
In some embodiments, the specific etching process includes: etching part of the second sacrificial layer, the first sacrificial layer and the third sacrificial layer protruding above the corresponding lower electrode contact structure and the protruding top layer of the first protruding structure and the second protruding structure or etching part of the second sacrificial layer and the first sacrificial layer above the corresponding lower electrode contact structure and the protruding top layer of the first protruding structure and the protruding top layer of the third sacrificial layer and the second sacrificial layer protruding, forming a plurality of capacitor holes exposing the corresponding lower electrode contact structure in the first sacrificial layer, the second sacrificial layer and the laminated supporting layer, and reserving the protruding extension walls of the first protruding structure and the second protruding structure on the side walls of the capacitor holes during etching.
With continued reference to fig. 21, a lower electrode 314 is formed on the sidewall and bottom surface of the capacitor hole 313.
Referring to fig. 22, before removing the remaining first sacrificial layer and second sacrificial layer, a portion of the remaining top support layer 312 between adjacent capacitor holes 313 is removed, forming etching holes exposing the surface of the remaining second sacrificial layer 311 between adjacent capacitor holes 313.
Referring to fig. 23, the second sacrificial layer is removed along the etched holes to form a second cavity 316. And removing the second sacrificial layer by wet etching.
Referring to fig. 24, the second support layer 310, the reserved third sacrificial layer 328 and the first support layer 307 are partially removed along the etching holes and the corresponding first cavities 316 by using an anisotropic dry etching process, and during etching, the protruding extension walls 30 in the second support layer 310 and the protruding extension walls 27 in the first support layer 207 remain on the outer sidewalls of the "U" shaped lower electrode 314.
Referring to fig. 25, the remaining third sacrificial layer 328 is removed using a wet etching process, a third cavity 318 is formed at a corresponding position, the remaining first sacrificial layer is removed, a first cavity 319 is formed at a corresponding position, and the first cavity 319, the second cavity 316, and the third cavity 318 constitute a cavity.
In some embodiments, after forming the cavity, further comprising: forming a dielectric layer on the surface of the lower electrode 314 and the surfaces of the cavities (the first cavity 319, the second cavity 316 and the third cavity 318) in the capacitor hole 313; an upper electrode is formed on the dielectric layer.
Some embodiments of the present invention also provide a memory device, referring to fig. 14 or 25, including:
A substrate 200 (300), wherein a plurality of lower electrode contact structures 220 (330) are formed in the substrate 200 (300);
A plurality of "U" -shaped bottom electrodes 214 (314) connected to the respective bottom electrode contact structures 220 (330);
A stacked support layer on the outer side walls of the plurality of lower electrodes 214 (314), the stacked support layer including a first support layer 207 (307) and a second support layer 210 (310) on the first support layer 207 (307), portions of the first support layer 207 (307) and the second support layer 310 (310) contacting the outer side walls of the lower electrodes 220 (330) including convex extension walls (27, 30) extending in a direction perpendicular to the substrate surface, the convex extension walls 27 of the first support layer 207 (307) being connected with the convex extension walls 30 of the second support layer 210 (310);
Dielectric layers on the inner wall side and outer sidewall surface of the lower electrode 214 (314);
an upper electrode on the surface of the dielectric layer.
In some embodiments, referring to fig. 7 (or fig. 19), the first support layer 207 (307) between portions of the lower electrode 214 (314) has a first raised structure 227 (327), the second support layer 210 (310) has a second raised structure 230 (330), the second raised structure and being located above the first raised structure, and the first raised structure and the second raised structure each comprise a raised top layer parallel to the substrate surface and a raised extension wall connected to the raised top layer edge and located on a sidewall surface of a corresponding capacitive aperture and extending in a direction perpendicular to the substrate surface.
In some embodiments, referring to fig. 19, the first bump structure 327 and the second bump structure 330 are bump in a direction away from the surface of the substrate 300, and a third cavity (where the third sacrificial layer bump 309 is removed) is formed between the bump top layer 26 of the first bump structure 327 and the bump top layer 29 of the second bump structure 230, and the dielectric layer is further located on a sidewall surface of the third cavity, and a surface of the dielectric layer in the third cavity is further provided with an upper electrode layer.
In other embodiments, referring to fig. 7, the first protrusion structures 227 and the second protrusion structures 230 protrude in a direction approaching the surface of the substrate 200.
Although the present application has been described in terms of the preferred embodiments, it is not intended to be limited to the embodiments, and any person skilled in the art can make any possible variations and modifications to the technical solution of the present application by using the methods and technical matters disclosed above without departing from the spirit and scope of the present application, so any simple modifications, equivalent variations and modifications to the embodiments described above according to the technical matters of the present application are within the scope of the technical matters of the present application.
Claims (20)
1. A method of forming a memory device, comprising:
Providing a substrate, wherein a plurality of lower electrode contact structures are formed in the substrate;
Forming a first sacrificial layer on the substrate;
Forming a laminated support layer on the first sacrificial layer, wherein the laminated support layer comprises a first support layer and a second support layer positioned on the first support layer, the first support layer is provided with a plurality of first protruding structures, the second support layer is provided with a plurality of second protruding structures, one first protruding structure and a second protruding structure positioned above the first protruding structure are respectively arranged above each lower electrode contact structure, and each of the first protruding structure and the second protruding structure comprises a protruding top layer parallel to the surface of the substrate and a protruding extension wall extending along the direction vertical to the surface of the substrate and connected with the edge of the protruding top layer;
Forming a second sacrificial layer on the laminated support layer;
Etching to remove part of the second sacrificial layer, the laminated supporting layer and the first sacrificial layer above the lower electrode contact structure, forming a plurality of capacitance holes exposing the surfaces of the corresponding lower electrode contact structure in the first sacrificial layer, the laminated supporting layer and the second sacrificial layer, and reserving the protruding extension walls of the first protruding structure and the second protruding structure on the side walls of the capacitance holes during etching;
Forming a lower electrode on the side wall and the bottom surface of the capacitor hole;
After forming the lower electrode, removing the remaining first sacrificial layer and second sacrificial layer to form a cavity;
forming a dielectric layer on the surface of the lower electrode and the surface of the cavity in the capacitor hole;
forming an upper electrode on the dielectric layer;
wherein, have the third cavity between first supporting layer and the second supporting layer, and first supporting layer with the second supporting layer is only through protruding extension wall direct contact.
2. The method of forming a memory device of claim 1, wherein a corresponding one of the first bump structures and the second bump structures above each of the lower electrode contact structures are each bump in a direction toward the substrate.
3. The method of forming a memory device of claim 2, wherein the forming of the stacked support layer comprises: etching to remove part of the first sacrificial layer, forming a plurality of first sacrificial layer bulges and first grooves positioned between the first sacrificial layer bulges on the top of the first sacrificial layer, wherein the first grooves are positioned above the corresponding lower electrode contact structures; forming a first support layer on the side wall and the top surface of the first sacrificial layer bulge and on the bottom surface of the first groove between the first sacrificial layer bulges; forming a third sacrificial layer bump on the first support layer surface on the top surface of the first sacrificial layer bump; and forming a second support layer on the side wall and the top surface of the third sacrificial layer protrusion and the first support layer between the third sacrificial layer protrusions.
4. The method of forming a memory device of claim 3, wherein the third sacrificial layer bump is formed by: forming a third sacrificial layer on the surface of the first supporting layer; and etching to remove part of the third sacrificial layer, and forming a third sacrificial layer protrusion on the surface of the first supporting layer on the top surface of the first sacrificial layer protrusion.
5. The method of forming a memory device according to claim 4, wherein a portion of the third sacrificial layer is etched away, and the third sacrificial layer in the first recess between adjacent first sacrificial layer projections is left or removed; when forming the second supporting layer, the part of the second supporting layer is positioned on the surface of the third sacrificial layer which is reserved in the first grooves between the adjacent first sacrificial layer bulges or is directly positioned on the surface of the first supporting layer in the first grooves.
6. The method of forming a memory device of claim 5, wherein the third sacrificial layer is removed simultaneously with the removing of the remaining first sacrificial layer and second sacrificial layer to form a cavity.
7. The method of forming a memory device of claim 5, wherein etching away portions of the second sacrificial layer and the stacked support layer and the first sacrificial layer over the lower electrode contact structure forms a plurality of capacitor holes in the first sacrificial layer, the stacked support layer and the second sacrificial layer exposing surfaces of the respective lower electrode contact structures, and wherein retaining the raised extension walls of the first raised structures and the second raised structures during etching at sidewalls of the capacitor holes comprises: etching a part of the second sacrificial layer and the first sacrificial layer above the corresponding lower electrode contact structure and the protruding top layer of the first protruding structure and the second protruding structure or etching a part of the second sacrificial layer and the first sacrificial layer above the corresponding lower electrode contact structure and the protruding top layer and the third sacrificial layer of the first protruding structure and the second protruding structure, forming a plurality of capacitance holes exposing the corresponding lower electrode contact structure in the first sacrificial layer, the second sacrificial layer and the laminated supporting layer, and reserving the protruding extension walls of the first protruding structure and the second protruding structure on the side walls of the capacitance holes during etching.
8. The method of forming a memory device of claim 1, wherein a corresponding one of the first bump structures and the second bump structures above each of the lower electrode contact structures are each bump in a direction away from the substrate.
9. The method of forming a memory device of claim 8, wherein the forming of the stacked support layer comprises: etching to remove part of the first sacrificial layer, forming a plurality of second sacrificial layer bulges and second grooves positioned between the second sacrificial layer bulges at the top of the first sacrificial layer, wherein the second sacrificial layer bulges are positioned above corresponding lower electrode contact structures; forming a first support layer on the side wall and the top surface of the second sacrificial layer bulge and on the bottom surface of the second groove between the second sacrificial layer bulges; forming a third sacrificial layer bump on the first support layer surface on the top surface of the second sacrificial layer bump; and forming a second support layer on the side wall and the top surface of the third sacrificial layer protrusion and the first support layer between the third sacrificial layer protrusions.
10. The method of forming a memory device of claim 9, wherein the forming of the third sacrificial layer bump is: forming a third sacrificial layer on the surface of the first supporting layer; and etching to remove part of the third sacrificial layer, and forming a third sacrificial layer protrusion on the surface of the first supporting layer on the top surface of the first sacrificial layer protrusion.
11. The method of forming a memory device according to claim 10, wherein a third sacrificial layer in the second recess between adjacent second sacrificial layer projections is left or removed while etching away a part of the third sacrificial layer; when forming the second supporting layer, the part of the second supporting layer is positioned on the surface of the reserved third sacrificial layer in the second grooves between the adjacent second sacrificial layer bulges or is directly positioned on the surface of the first supporting layer in the second grooves.
12. The method of forming a memory device of claim 11, wherein the third sacrificial layer is removed simultaneously with the removing of the remaining first sacrificial layer and second sacrificial layer to form a cavity.
13. The method of forming a memory device of claim 12, wherein etching away portions of the second sacrificial layer and the stacked support layer and the first sacrificial layer over the lower electrode contact structure forms a plurality of capacitor holes in the first sacrificial layer, the stacked support layer and the second sacrificial layer exposing surfaces of the respective lower electrode contact structures, and wherein etching away sidewalls of the protruding extension walls of the first protruding structures and the second protruding structures comprises: etching part of the second sacrificial layer, the first sacrificial layer and the third sacrificial layer protruding above the corresponding lower electrode contact structure and the protruding top layer of the first protruding structure and the second protruding structure or etching part of the second sacrificial layer and the first sacrificial layer above the corresponding lower electrode contact structure and the protruding top layer of the first protruding structure and the protruding top layer of the third sacrificial layer and the second sacrificial layer protruding, forming a plurality of capacitor holes exposing the corresponding lower electrode contact structure in the first sacrificial layer, the second sacrificial layer and the laminated supporting layer, and reserving the protruding extension walls of the first protruding structure and the second protruding structure on the side walls of the capacitor holes during etching.
14. The method of forming a memory device of claim 1, further comprising: and forming a top supporting layer on the second sacrificial layer.
15. The method of claim 14, wherein when forming the plurality of capacitor holes, etching to remove a portion of the top support layer above the lower electrode contact structure exposes a surface of a portion of the second sacrificial layer above the corresponding lower electrode contact structure.
16. The method of forming a memory device of claim 15, wherein removing a portion of the remaining top support layer between adjacent capacitor holes exposes a surface of the remaining second sacrificial layer between adjacent capacitor holes before removing the remaining first sacrificial layer and second sacrificial layer.
17. A memory device, comprising:
a substrate in which a plurality of lower electrode contact structures are formed;
A plurality of U-shaped lower electrodes connected with the corresponding lower electrode contact structures;
the laminated support layers are positioned on the outer side walls of the plurality of lower electrodes, each laminated support layer comprises a first support layer and a second support layer positioned on the first support layer, the contact parts of the first support layer and the second support layer with the outer side walls of the lower electrodes comprise convex extension walls extending along the direction vertical to the surface of the substrate, and the convex extension walls of the first support layer are connected with the convex extension walls of the second support layer;
dielectric layers on the inner wall side and outer side wall surfaces of the lower electrode;
an upper electrode on the surface of the dielectric layer;
wherein, have the third cavity between first supporting layer and the second supporting layer, and first supporting layer with the second supporting layer is only through protruding extension wall direct contact.
18. The memory device of claim 17, wherein the first support layer between portions of the lower electrode has a first raised structure, the second support layer has a second raised structure, the second raised structure and being located above the first raised structure, and wherein the first raised structure and the second raised structure each include a raised top layer parallel to the substrate surface and a raised extension wall connected to an edge of the raised top layer and located on a sidewall surface of the corresponding capacitive aperture and extending in a direction perpendicular to the substrate surface.
19. The memory device of claim 18, wherein the first and second raised structures are raised away from the substrate surface, the third cavity is further located between a raised top layer of the first raised structure and a raised top layer of the second raised structure, the dielectric layer is further located on a sidewall surface of the third cavity, and a surface of the dielectric layer in the third cavity is further provided with an upper electrode layer.
20. The memory device of claim 18, wherein the first and second raised structures are raised in a direction proximate to a substrate surface, wherein a raised top layer of the first raised structure is in contact with a raised top layer of the second raised structure or wherein the third cavity is further located between the raised top layer of the first raised structure and the raised top layer of the second raised structure, wherein the dielectric layer is further located at a sidewall surface of the third cavity, wherein a surface of the dielectric layer in the third cavity is further provided with an upper electrode layer.
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| KR101589912B1 (en) * | 2009-03-20 | 2016-02-01 | 삼성전자주식회사 | Capacitor and Method of forming the same |
| KR101728320B1 (en) * | 2011-06-30 | 2017-04-20 | 삼성전자 주식회사 | Method of fabricating semiconductor device |
| TWI571915B (en) * | 2014-01-29 | 2017-02-21 | 華亞科技股份有限公司 | Method for manufacturing lower electrode of capacitor and semiconducor device |
| CN108550568B (en) * | 2018-04-26 | 2020-04-10 | 长鑫存储技术有限公司 | Capacitor array, forming method thereof and semiconductor device |
| CN112908968B (en) * | 2019-12-03 | 2022-06-10 | 长鑫存储技术有限公司 | Capacitor in semiconductor memory and method for fabricating the same |
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- 2021-10-18 CN CN202111208150.8A patent/CN114121817B/en active Active
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| CN101132003A (en) * | 2006-08-25 | 2008-02-27 | 茂德科技股份有限公司 | Capacitor structure of semiconductor memory and method for preparing the same |
| CN109148426A (en) * | 2018-09-29 | 2019-01-04 | 长鑫存储技术有限公司 | Capacitance structure and forming method thereof |
| CN112185886A (en) * | 2019-07-05 | 2021-01-05 | 长鑫存储技术有限公司 | Capacitor array, preparation method thereof and storage device |
| KR20210052094A (en) * | 2019-10-31 | 2021-05-10 | 삼성전자주식회사 | Integrated circuit semiconductor device |
| CN111834529A (en) * | 2020-08-07 | 2020-10-27 | 福建省晋华集成电路有限公司 | Capacitor structure, semiconductor device and capacitor structure preparation method |
| CN113053898A (en) * | 2021-03-12 | 2021-06-29 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method thereof |
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| WO2023065543A1 (en) | 2023-04-27 |
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