CN114121783A - Wiring material for semiconductor device, wiring for semiconductor device, and semiconductor device including wiring - Google Patents

Wiring material for semiconductor device, wiring for semiconductor device, and semiconductor device including wiring Download PDF

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Publication number
CN114121783A
CN114121783A CN202110829288.3A CN202110829288A CN114121783A CN 114121783 A CN114121783 A CN 114121783A CN 202110829288 A CN202110829288 A CN 202110829288A CN 114121783 A CN114121783 A CN 114121783A
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China
Prior art keywords
wiring
boride
semiconductor device
wiring material
based compound
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CN202110829288.3A
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Inventor
俞贞恩
康永宰
尹斗燮
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication of CN114121783A publication Critical patent/CN114121783A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22C—ALLOYS
    • C22C29/00—Alloys based on carbides, oxides, nitrides, borides, or silicides, e.g. cermets, or other metal compounds, e.g. oxynitrides, sulfides
    • C22C29/14—Alloys based on carbides, oxides, nitrides, borides, or silicides, e.g. cermets, or other metal compounds, e.g. oxynitrides, sulfides based on borides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H01L23/53219—Aluminium alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
    • H01L23/53261—Refractory-metal alloys
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B22—CASTING; POWDER METALLURGY
    • B22F—WORKING METALLIC POWDER; MANUFACTURE OF ARTICLES FROM METALLIC POWDER; MAKING METALLIC POWDER; APPARATUS OR DEVICES SPECIALLY ADAPTED FOR METALLIC POWDER
    • B22F2302/00—Metal Compound, non-Metallic compound or non-metal composition of the powder or its coating
    • B22F2302/35—Complex boride, carbide, carbonitride, nitride, oxide or oxynitride

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Abstract

Providing a wiring material for a semiconductor device, a wiring for a semiconductor type device, and a semiconductor type device including the wiring, the wiring material comprising: a boride-based compound comprising boron and at least one metal selected from elements of groups 2 to 14.

Description

Wiring material for semiconductor device, wiring for semiconductor device, and semiconductor device including wiring
Cross reference to related applications
This application is based on and claims priority from korean patent application No.10-2020-0110591, filed by the korean intellectual property office on 31/8/2020, the disclosure of which is incorporated herein by reference in its entirety.
Technical Field
The present disclosure relates to a wiring (wiring) material for a semiconductor device, a wiring for a semiconductor device including the same, and/or a semiconductor device including the wiring.
Background
In recent years, the size of semiconductor devices has been gradually reduced to provide high integration of semiconductor devices, and for this reason, the line width of wirings in an interconnect structure must be reduced.
Meanwhile, when the line width of the wiring is reduced, the current density in the wiring increases, resulting in an increase in the resistance of the wiring.
Copper wiring is generally used as the wiring. Such an increase in the resistance of the wiring may cause electromigration (electron drift) of copper atoms constituting the wiring, resulting in defects in the copper wiring. In addition, potential reliability problems may arise, including wiring stress migration due to stress generated in the metal wiring during processing, Cu diffusion from Cu atoms penetrating into the barrier layer between the wiring and the dielectric material, which are gradually miniaturized (reduced in size), and the like. Therefore, there is an increasing need to develop new wiring materials to replace copper.
Disclosure of Invention
One aspect provides a new wiring material for a semiconductor device.
Another aspect provides a wiring for a semiconductor device including the wiring material.
Still another aspect provides a semiconductor device including a wiring including the wiring material.
Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented embodiments of the disclosure.
According to an embodiment, a wiring material for a semiconductor device may include a boride-based compound including boron and at least one metal selected from elements of groups 2 to 14.
In some embodiments, the at least one metal may be a group 5 element, a group 6 element, or a combination thereof.
In some embodiments, the metal may be tungsten (W), molybdenum (Mo), tantalum (Ta), niobium (Nb), chromium (Cr), vanadium (V), iron (Fe), nickel (Ni), cobalt (Co), titanium (Ti), zirconium (Zr), hafnium (Hf), uranium (U), magnesium (Mg), manganese (Mn), aluminum (Al), dysprosium (Dy), erbium (Er), lanthanum (La), cerium (Ce), indium (In), gallium (Ga), or a combination thereof.
In some embodiments, the metal may be tungsten (W), tantalum (Ta), chromium (Cr), molybdenum (Mo), vanadium (V), or a combination thereof.
In some embodiments, the amount of boron in the boride-based compound may range from 25 atomic% to 88 atomic%.
In some embodiments, the amount of boron in the boride-based compound may range from 50 atomic% to 70 atomic%.
In some embodiments, the boride-based compound may be a compound represented by formula 1:
[ formula 1]
MaBb
In the formula 1, the first and second groups,
m may be W, Mo, Ta, Nb, Cr, V, or combinations thereof,
a can be a number from 1 to 5, and
b may be a number from 1 to 10.
In some embodiments, the boride-based compound may be a compound represented by formula 2:
[ formula 2]
M1aM2cBb
In the formula 2, the first and second groups,
m1 may be W, Mo, Ta, Nb, Cr, Mn, V, Fe, Zr, Ti, Hf, or combinations thereof,
m2 may be Al, Ga, In, or combinations thereof,
a may be a number from 1 to 5,
b can be a number from 1 to 5, and
c may be a number from 1 to 10.
In some embodiments, the boride-based compound can be WB2、MoB2、TaB2、NbB2、CrB2、CrB、MoB、VB2、FeB、NiB、Fe2B、Co2B、Ni2B、TiB2、ZrB2、HfB2、UB2、MgB2、MnB2、AlB2、DyB2、ErB2、Mn3B4、DyB4、ErB4、UB4、Mo2B5、W2B5、LaB6、CeB6、DyB6、ErB6、MoAlB、WAlB、Hf2AlB、Hf2GaB、Hf2InB、Ti2AlB、Ti2GaB、Ti2InB、Zr2AlB、Zr2GaB、Zr2InB、Cr2AlB2、Mn2AlB2、Fe2AlB2、Cr4AlB6Or a combination thereof.
In some embodiments, the boride-based compound can have a 1D quality factor (figure of merit) of 6.7 or less.
In some embodiments, the boride-based compound can have a 1D quality factor of 3 to 6.2.
In some embodiments, the boride-based compound can have a 3D figure of merit of 7.5 or less.
In some embodiments, the boride-based compound can have a 3D figure of merit of 4.5 to 7.5.
In some embodiments, the boride-based compound may have a melting point of 1300 ℃ or greater.
In some embodiments, the boride-based compound may have a melting point of 2000 ℃ or greater.
In some embodiments, the wiring may include the wiring material.
In some embodiments, a semiconductor-type device can include a wiring including the wiring material.
In some embodiments, the semiconductor device can further include a semiconductor substrate and an interconnect structure on the semiconductor substrate. The interconnect structure may include a dielectric layer on the semiconductor substrate. The dielectric layer may have at least one trench formed therein. The interconnect structure may include the wiring, and the wiring is in the trench.
In some embodiments, the interconnect structure may further include a barrier layer covering the wire in the trench.
In some embodiments, the trench of the interconnect structure may extend through a thickness of the interconnect structure.
In some embodiments, the depth of the trench may be less than the thickness of the interconnect structure.
In some embodiments, the interconnect structure may further include a liner layer covering the wire within the trench.
In some embodiments, the pad layer may expose a top surface of the wiring.
In some embodiments, the liner layer may include titanium nitride (TiN), titanium Tungsten (TiW), tungsten nitride (WN), tantalum nitride (TaN), Ti, Ta, or combinations thereof.
In some embodiments, the interconnect structure may further include a barrier layer covering the wire within the trench.
In some embodiments, the barrier layer may have a single layer structure or a multi-layer structure, and the barrier layer may expose a top surface of the wire.
In some embodiments, the semiconductor-type device may further include a logic device on the semiconductor substrate.
In an embodiment, a wiring material for a semiconductor device may include:
a boride-based compound represented by formula 3:
[ formula 3]
M1wM2xZyBz
In the formula 3, the first and second groups,
m1 may be W, Mo, Ta, Nb, Cr, Mn, V, Fe, Zr, Ti, Hf, or combinations thereof,
m2 may be Al, Ga, In, or combinations thereof,
w may be a number from 1 to 5,
x may be a number from 1 to 10,
y may be a number from 1 to 5,
z may be a number from 1 to 6,
when y is greater than or equal to 1, w and x may be 0,
when w is greater than or equal to 1, y can be 0, and
when x is greater than or equal to 1, y may be 0.
In some embodiments, in formula 3, w may be 1 to 4, x may be 1, y may be 1 to 2, z may be 1 to 6, w and x may be 0 when y is 1 to 2, y may be 0 when w is 1 to 4, and y may be 0 when x is 1.
In some embodiments, a semiconductor-type device can include: a substrate and a wiring including the wiring material. The wiring may be on the substrate.
In some embodiments, the boride-based compound can be WB2、MoB2、TaB2、NbB2、CrB2、CrB、MoB、VB2、FeB、NiB、Fe2B、Co2B、Ni2B、TiB2、ZrB2、HfB2、UB2、MgB2、MnB2、AlB2、DyB2、ErB2、Mn3B4、DyB4、ErB4、UB4、Mo2B5、W2B5、LaB6、CeB6、DyB6、ErB6、MoAlB、WAlB、Hf2AlB、Hf2GaB、Hf2InB、Ti2AlB、Ti2GaB、Ti2InB、Zr2AlB、Zr2GaB、Zr2InB、Cr2AlB2、Mn2AlB2、Fe2AlB2、Cr4AlB6Or a combination thereof.
Drawings
The above and other aspects, features and advantages of some embodiments of the present disclosure will become more apparent from the following description considered in conjunction with the accompanying drawings, in which
FIG. 1 shows an example semiconductor device illustrating a stacked structure of semiconductor devices including an interconnect structure, according to one embodiment;
FIG. 2 shows an example semiconductor device illustrating a stacked structure of semiconductor devices including an interconnect structure, according to another embodiment;
fig. 3A and 3B are diagrams of an example of a method of manufacturing the semiconductor device shown in fig. 1;
fig. 3A and 3C are diagrams of an example of a method of manufacturing the semiconductor device shown in fig. 2; and
fig. 4 shows an example semiconductor device according to an embodiment further including a logic device.
Detailed Description
Reference will now be made in detail to the embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. In this regard, the present embodiments may have different forms and should not be construed as limited to the descriptions set forth herein. Accordingly, the embodiments are described below to illustrate aspects only by referring to the drawings. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
The expression "at least one of" when preceding or following a list of elements modifies the entire list of elements and does not modify individual elements of the list. For example, "A, B, and at least one of C", "A, B, or at least one of C", "A, B, C, or one of their combinations" and "A, B, C, and one of their combinations", respectively, can be construed to encompass any of the following: a; b; a and B; a and C; b and C; and A, B, and C.
When the term "about" or "substantially" is used in this specification in connection with a numerical value, it is intended that the relevant numerical value include manufacturing or operating tolerances (e.g., ± 10%) around that numerical value. Moreover, when the words "substantially" and "substantially" are used in connection with a geometric shape, it is intended that the precision of the geometric shape not be required, but that the latitude (limits) of the shape be within the scope of the disclosure. Further, whether a value or shape is modified to be "about" or "substantially," it is to be understood that such values and shapes are to be interpreted as including manufacturing or operating tolerances (e.g., ± 10%) around the value or shape.
A wiring material for a semiconductor device, a wiring for a semiconductor device including the same, and a semiconductor device including the wiring (may also be referred to as a semiconductor type device) according to embodiments will be described in more detail.
Advantages and features of the inventive concepts and methods for their implementation will be apparent with reference to the embodiments of the present disclosure described below in connection with the accompanying drawings. However, the inventive concept is not limited to the disclosed embodiments of the present disclosure, but may be implemented in various ways, and the embodiments of the present disclosure are provided to complete the disclosure of the technical spirit and allow those of ordinary skill in the art to understand the scope of the inventive concept. The technical spirit of the inventive concept may be defined by the claims. In some embodiments, well-known techniques will not be described in detail to avoid obscuring the description of the embodiments of the inventive concepts in the present application. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concepts belong. In addition, terms, such as those defined in commonly used dictionaries, should not be interpreted in an idealized or overly formal sense unless expressly so defined herein. In addition, it will be understood that the term "comprising" indicates the possibility of adding and/or presenting one or more additional components, but does not exclude the possibility of merely including features of the recited components, unless the context clearly indicates otherwise.
In addition, a statement that is used in the singular includes plural referents unless it has a significantly different meaning in the context.
In the drawings, the diameter, length, and thickness of layers and regions are exaggerated or reduced for clarity. Like reference numerals refer to like elements throughout the specification.
Throughout the specification, it will be understood that when an element such as a layer, film, region, or panel is referred to as being "on" another element, the one element may be directly on the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present.
A wiring material for a semiconductor device is provided, which includes a boride-based compound containing boron and at least one metal selected from elements of groups 2 to 14.
The inventive concept relates to wiring materials that can reduce and/or minimize the occurrence of the following phenomena: as device dimensions decrease, resistivity increases. In order to reduce and/or minimize the reliability deterioration caused by the use of the existing wiring material, and in order to reduce and/or minimize the increase in resistivity that occurs when the wiring pattern size is reduced, a new wiring material that can replace the existing wiring material is required.
Copper is known as a wiring material. However, in a semiconductor device using a wiring made of copper, as the device size is reduced, the resistivity is greatly increased because copper has a relatively long mean free path although copper has a low bulk resistivity. As a result, current may not flow well in the semiconductor device, and thus may seriously affect the performance of the semiconductor device. Therefore, it may be necessary to develop a new wiring material capable of replacing the Cu wiring used as the interconnect.
While development of wiring materials with low bulk resistivity and processes thereof have traditionally been a major concern, how low the product of bulk resistivity (ρ 0) and mean free path (λ) has recently become an important measure in determining dimensional effects. The product of the bulk resistivity (ρ 0) and the mean free path (λ) is expressed as a figure of merit. The lower the product of the bulk resistivity (ρ 0) and the mean free path (λ) of the material, i.e., the lower the bulk resistivity (ρ 0) of the material and the shorter the mean free path (λ), the more advantageous in terms of maintaining the resistivity, even if the device size is reduced.
Cu has a relatively large mean free path of about 39nm and reacts sensitively to size effects as device dimensions decrease. Therefore, using a material having a short mean free path as a new wiring material instead of the conventional copper wiring can make the wiring material insensitive to the dimensional effect that occurs when reducing the device size.
When the quality factors of various materials are examined based on the results of the ab initio calculation, Rh, Pt, Ir, Nb, and the like have low quality factors, and thus may be less affected by the size effect according to the scaling of the device size. However, since such materials have low process maturity and may require high process costs, the use of the materials in semiconductor processes may be impractical.
In order to provide a dimensional effect with respect to electrical conductivity and excellent reliability of the wiring material, the wiring material should have a high melting point.
In view of the foregoing, the present inventors have studied on a new wiring material having a short mean free path and being insensitive to a dimensional effect for replacing a conventional copper wiring material, and have finally completed a wiring material, a wiring including the wiring material, and a semiconductor device including the wiring according to the inventive concept.
According to the inventive concept, the new wiring material provides a boride-based compound comprising boron and at least one metal selected from elements of groups 2 to 14. The boride-based compound, which is a compound of boron and a metal element, generally has the properties of an intermetallic compound, an appearance similar to that of a metal, a relatively high rigidity, and a high melting point of 1300 ℃ or more, for example, 2000 ℃ or more, and is chemically inert and superior in thermal and electrical conductivity.
In the boride-based compound according to the embodiment, for example, ZrB2And TiB2Have a rather high thermal and electrical conductivity, i.e. about 10 times the thermal and electrical conductivity of metals. In order to investigate the dimensional effect of the material with respect to electrical conductivity, a quality factor was obtained by a first-principle calculation, and the result confirmed that the material had a very good quality factor compared to Cu which is currently widely used as a wiring material.
In the wiring material for a semiconductor device including a boride-based compound according to an aspect, the metal may be, for example, a group 5 element, a group 6 element, or a combination thereof.
Group 2 to 14 metals include tungsten (W), molybdenum (Mo), tantalum (Ta), niobium (Nb), chromium (Cr), vanadium (V), iron (Fe), nickel (Ni), cobalt (Co), titanium (Ti), zirconium (Zr), hafnium (Hf), uranium (U), magnesium (Mg), manganese (Mn), aluminum (Al), dysprosium (Dy), erbium (Er), lanthanum (La), cerium (Ce), indium (In), gallium (Ga), or combinations thereof.
In embodiments, the metal is, for example, a group 5 element, a group 6 element, or a combination thereof. Additionally, the metal is W, Ta, Cr, Mo, V, or a combination thereof.
In the boride-based compound according to an aspect, the boron content is in the range of 25 to 88 atomic percent (at.%).
According to another aspect, the boron content is, for example, 50 atomic% or greater, or 50 to 70 atomic%. When the boron content is within the above range, potential reliability problems, such as stress migration of the wiring due to stress generated by the metal wiring during the process, or diffusion of Cu atoms that have penetrated into the barrier layer between the wiring and the dielectric material, which have been gradually miniaturized, may be limited and/or prevented.
For example, in an embodiment, the boride-based compound is a compound represented by formula 1:
[ formula 1]
MaBb
In formula 1, M is W, Mo, Ta, Nb, Cr, V, or a combination thereof; and a is a number from 1 to 5, and b is a number from 1 to 10.
In formula 1, a may be a number from 1 to 3 or a number from 1 or 2, and b may be a number from 1 to 6 or a number from 1 to 5.
The boride-based compound may be a compound represented by formula 2:
[ formula 2]
M1aM2cBb
In formula 2, M1 is W, Mo, Ta, Nb, Cr, Mn, V, Fe, Zr, Ti, Hf, or a combination thereof; m2 is Al, Ga, In, or a combination thereof; and a is a number from 1 to 5, b is a number from 1 to 5, and c is a number from 0 to 10 and/or c is a number from 1 to 10.
In formula 2, in an embodiment, a is a number from 1 to 4 or a number from 1 or 2, c is a number from 1 to 3 or a number from 1 or 2, and b is a number from 1 to 5, a number from 1 to 5 or a number from 1 or 2.
In an embodiment, the boride-based compound may be a compound represented by formula 3:
[ formula 3]
M1wM2xZyBz
In the formula 3, the first and second groups,
m1 may be W, Mo, Ta, Nb, Cr, Mn, V, Fe, Zr, Ti, Hf, or combinations thereof,
m2 may be Al, Ga, In, or combinations thereof,
w may be a number from 1 to 5,
x may be a number from 1 to 10,
y may be a number from 1 to 5,
z may be a number from 1 to 6,
when y is greater than or equal to 1, w and x may be 0,
when w is greater than or equal to 1, y can be 0, and
when x is greater than or equal to 1, y may be 0.
In some embodiments, in formula 3, w may be 1 to 4, x may be 1, y may be 1 to 2, z may be 1 to 6, w and x may be 0 when y is 1 to 2, y may be 0 when w is 1 to 4, and y may be 0 when x is 1.
The compound of formula 1, the compound of formula 2, and the compound of formula 3 may include a single crystal or a polycrystal (e.g., polycrystal).
In the compound of formula 1, M and B may be mixed in an atomic ratio of 1:0.3 to 1:6, for example, 1:0.33 to 1: 2.5. When the mixing ratio of M and B in the compound of formula 1 is within the above range, a wiring material for a semiconductor device formed therefrom has a reduced increase in resistivity due to a decrease in line width of a wiring, and a high melting point, as compared with a copper wiring.
In the compound of formula 2, the sum of M1 and M2 and B may be mixed in an atomic ratio of 1:0.3 to 1:6, for example 1:0.33 to 1:2. In the compound of formula 2, when the mixing ratio of the sum of M1 and M2 to B is in the above range, a wiring material for a semiconductor device formed therefrom has a reduced increase in resistivity due to a decrease in line width of a wiring, and has a high melting point, as compared with a copper wiring.
According to an embodiment, when an atomic ratio of M and B mixed in the compound of formula 1 is 1:2 and when an atomic ratio of the sum of M1 and M2 mixed in the compound of formula 2 to B is 1:2, the compound may have an atomic arrangement in which metal layers and boron layers are alternately stacked and may have a layered crystal structure.
In the layered crystal structure, unit structure layers are connected to each other by van der waals force, and thus enable interlayer sliding and can be manufactured by mechanical peeling or liquid peeling to provide nanosheets, thereby providing a thin film having excellent flexibility and high electrical conductivity. Therefore, the wiring material according to the embodiment is useful for a wiring for a semiconductor device.
The boride-based compound as a wiring material for a semiconductor device may include, for example, WB2、MoB2、TaB2、NbB2、CrB2、CrB、MoB、VB2、FeB、NiB、Fe2B、Co2B、Ni2B、TiB2、ZrB2、HfB2、UB2、MgB2、MnB2、AlB2、DyB2、ErB2、Mn3B4、DyB4、ErB4、UB4、Mo2B5、W2B5、LaB6、CeB6、DyB6、ErB6、MoAlB、WAlB、Hf2AlB、Hf2GaB、Hf2InB、Ti2AlB、Ti2GaB、Ti2InB、Zr2AlB、Zr2GaB、Zr2InB、Cr2AlB2、Mn2AlB2、Fe2AlB2、Cr4AlB6Or a combination thereof.
Boride-based compounds according to embodiments may include, for example, WB2、MoB2、TaB2、NbB2、CrB2、CrB、MoB、VB2Or a combination thereof. Among the boride-based compounds, WB2And MoB2Has a hexagonal system.
The boride-based compound has a 1D quality factor of 6.7 or less. The 1D quality factor of the boride-based compound is less than 6.7, 1-6.5, 2-6.4, or 3-6.2.
The boride-based compound has a 3D quality factor of 7.5 or less, 3-7.5, or 4.5-7.5. When the values of the 1D and 3D quality factors of the boride-based compound are within the above ranges, an increase in resistivity of a wiring formed therefrom due to a decrease in line width is reduced as compared with a copper wiring, and thus excellent reliability can be maintained even if a semiconductor device is miniaturized.
In the present specification, according to the first principle based on quantum mechanics, a value of 1D or 3D quality factor is obtained from a head simulation package (Vienna Ab initio simulation package) (VASP) and Boltzmann transport properties (Boltzmann transport properties) (boltztrapp) using a simulation program Vienna. For the figure of merit evaluation, the disclosure in the document entitled "Metals for low-resistance interconnects", Daniel Gall, 2018IEEE 157 & 159 is incorporated herein by reference.
The boride-based compound can have a melting point of 1300 ℃ or greater, such as 2000 ℃ or greater.
According to embodiments, the melting point of the boride-based compound is 1350-. When the melting point of the boride-based compound is within the above range, an increase in resistivity of a wiring formed therefrom due to a decrease in line width of the wiring is reduced as compared with a copper wiring, and the melting point thereof is high, thereby maintaining excellent reliability even if a semiconductor device is miniaturized.
The boride-based compound used as a wiring material according to an aspect may be a compound having, for example, a layered crystal structure.
The boride-based compound according to an aspect, which is a compound of boron and at least one metal element, generally has properties of an intermetallic compound, similar to the appearance of a metal, a considerably high rigidity, and a high melting point of 1300 ℃ or more, for example, 2000 ℃ or more, and is chemically inert and superior in thermal and electrical conductivity. In addition, such compounds are chemically inert and, in particular, ZrB is among the boride-based compounds2And TiB2Have a rather high thermal and electrical conductivity, i.e. about 10 times the thermal and electrical conductivity of metals.
As described above, most of the wiring materials according to the embodiments have a high melting point while having a 1D or 3D quality factor equal to or lower than Cu currently used as a wiring material.
Among the boride-based compounds, boride-based compounds containing a group 5 or 6 element have a better quality factor and a higher melting point than Cu. In addition, an increase in resistivity due to a reduction in the line width of the wiring is reduced, and thus excellent reliability can be maintained even if the semiconductor device is miniaturized.
The boride-based compound according to an embodiment may be prepared by: a metal boride target having a desired composition is formed and then sputtered to form a thin film, followed by heat treatment at a crystallization temperature. The temperature and time of the heat treatment may vary depending on the kind of metal or composition of the boride-based compound desired.
Commercially available boride-based compounds may be used as the boride-based compounds, or compounds prepared using a metal precursor and a boron precursor as raw materials may be used as the boride-based compounds.
According to an embodiment, the boride-based compound may be prepared by a deposition process, a sputtering process, an arc melting process, a solid state reaction process, or a quartz ampoule process using a metal precursor and a boron precursor as raw materials.
As the metal precursor, a metal powder, a metal compound, or a mixture thereof including W, Mo, Ta, Nb, Cr, V, Fe, Ni, Co, Ti, Zr, Hf, U, Mg, Mn, Al, Dy, Er, La, Ce, Al, Ga, In, or a combination thereof may be used. As the metal compound, a metal oxide or the like can be used. In addition, as the boron precursor, boron powder, boron oxide, or the like can be used.
According to the solid state reaction process, a target product can be prepared by: the raw material powders are mixed to produce a sheet, and then the obtained sheet is subjected to heat treatment, or the raw material powder mixture is subjected to heat treatment to form a sheet, and then the sheet is sintered. Additionally, according to the quartz ampoule process, a target product may be prepared by: the raw material elements are introduced into a quartz tube or a metal ampoule, sealed in a vacuum, and subjected to heat treatment for solid state reaction or melting.
When the boride-based compound is prepared by the arc melting process, raw material elements are introduced into a chamber, arc discharge is performed in an inert gas (e.g., nitrogen, argon, etc.) atmosphere to melt the raw material elements, and then solidified.
The feedstock may be a powder or a bulk material (e.g., a sheet). If necessary, the raw material powder may be uniaxially pressed to be formed into a block material. The arc melting process may include performing arc melting two or more times while turning the top and bottom surfaces of the sheet so as to be uniformly heat-treated. The intensity of the current applied during the arc melting process is not particularly limited, and may be 50A or more, for example, 200A or more, but is not limited thereto. The intensity of the current applied during the arc melting process may be 350A or less, such as 300A or less, but is not limited thereto.
According to another aspect, a wiring for a semiconductor device including the wiring material according to the embodiment is provided.
The wiring may have a layered (layered) structure and may include a single layer or a plurality of layers. The layer can have a thickness of, for example, 50nm or less, 30nm or less, 20nm or less, 10nm or less, 1nm to 10nm, or 1nm to 5 nm.
The wiring for a semiconductor device according to the embodiment has low resistivity.
According to still another aspect, there is provided a semiconductor device including a wiring including the wiring material according to the embodiment.
The semiconductor device may include: a semiconductor substrate; and an interconnect structure disposed on the semiconductor substrate. The interconnect structure may include: a dielectric layer disposed on the semiconductor substrate and having at least one trench; and a wiring provided to fill the inside of the trench.
The wire may include a boride-based compound including boron and at least one of a group 2 to 14 metal.
The interconnect structure further includes a barrier layer disposed to cover the wire within the trench. In addition, the trench of the interconnect structure is formed to contact the substrate or not to contact the substrate.
The interconnect structure may further include a liner layer disposed to cover the wiring within the trench. The cushion layer may have a single-layer or multi-layer structure.
The interconnect structure may further include a barrier layer disposed to cover the wiring within the trench, and the barrier layer may have a single-layer or multi-layer structure.
The barrier layer is disposed to expose a top surface of the wiring.
A semiconductor device according to an embodiment includes a logic device disposed on the semiconductor substrate.
A semiconductor device according to an embodiment includes: a wire, a pad layer, and a dielectric layer including a wiring material including a boride-based compound according to an embodiment. The liner layer may function as both a metal seed layer and a diffusion prevention layer. Therefore, the semiconductor device does not require a barrier layer.
Hereinafter, a semiconductor device according to an embodiment will be described in detail with reference to the accompanying drawings.
Fig. 1 shows a semiconductor device 100 including an interconnect structure 120 according to an embodiment.
Referring to fig. 1, a semiconductor device 100 includes a semiconductor substrate 110 and an interconnect structure 120 disposed on the semiconductor substrate 110. Here, the interconnect structure 120 may include a dielectric layer 121, a wiring 125, a liner layer 127, and a barrier layer 126.
The semiconductor substrate 110 may include, for example, a group 4 semiconductor material, a group 3/5 semiconductor compound, or a group 2/6 semiconductor compound. In particular, the semiconductor substrate 110 may include Si, Ge, SiC, SiGe, SiGeC, Ge alloy, GaAs, InAs, InP, and the like. However, this is merely an example, and a variety of other semiconductor materials may be used as the substrate 110.
The semiconductor substrate 110 may include multiple layers or a single layer in which different materials are stacked. The semiconductor substrate 110 may include, for example, a silicon-on-insulator (SOI) substrate or a silicon germanium-on-insulator (SGOI) substrate. In addition, the substrate 110 may include an undoped semiconductor material or a doped semiconductor material.
The substrate 110 may include at least one semiconductor device (not shown). Here, the semiconductor device may include at least one of a transistor, a capacitor, a diode, and a resistor, for example. However, examples of the semiconductor device are not limited thereto.
The dielectric layer 121 is formed on the semiconductor substrate 110. The dielectric layer 121 may have a multi-layer structure or a single-layer structure in which different materials are stacked. The dielectric layer 121 may include a dielectric material used in a typical semiconductor manufacturing process. For example, the dielectric layer 121 may include silicon oxide, silicon nitride, silicon carbide, silicates, and the like. However, this is merely an example, and other various dielectric materials may be used as the dielectric layer 121. The dielectric layer 121 may also include an organic dielectric material.
At least one trench 121a is formed in the dielectric layer 121 to a certain depth. The at least one groove 121a may be formed not to contact the substrate 110 or to contact the substrate 110. Two trenches 121a are formed in the dielectric layer 121 in fig. 1, wherein one of the trenches 121a is formed not to contact the substrate 110 and the other is formed to contact the substrate 110.
The wiring 125 is provided to fill the inside of the trench 121 a. The wire 125 may include a boride-based compound according to an embodiment.
The wiring 125 according to the embodiment may reduce resistance, thereby improving electromigration resistance. The barrier layer 126 is disposed on the inner wall of the trench 121 a. A barrier layer 126 may be disposed between the dielectric layer 121 and the wiring 125 to cover the wiring 125. In particular, the barrier layer 126 may be disposed on the inner wall of the trench 121a to cover the side and bottom surfaces of the wire 125. The top surface of wire 125 may be exposed by barrier layer 126. Barrier layer 126 may serve to limit and/or prevent diffusion of the material forming wire 125. Meanwhile, the barrier layer 126 may additionally serve as an adhesion layer between the dielectric layer 121 and the wiring 125.
The barrier layer 126 may have a multilayer structure or a single layer structure in which different materials are stacked. The barrier layer 126 may comprise, for example, a metal alloy, or a metal nitride. In particular, the barrier layer 126 may include Ta, Ti, Ru, RuTa, IrTa, W, TaN, TiN, RuN, TuTaN, IrTaN, or WN. However, this is merely an example, and a variety of other materials may be used as barrier layer 126.
The liner layer 127 is disposed on the barrier layer 126 disposed on the inner wall of the trench 121 a. Here, a pad layer 127 may be disposed between the dielectric layer 121 and the wiring 125 to cover the wiring 125. In particular, the pad layer 127 may be disposed on an inner wall of the trench 121a to cover side and bottom surfaces of the wiring 125.
The liner layer 127 may comprise, for example, titanium nitride (TiN), titanium Tungsten (TiW), tungsten nitride (WN), tantalum nitride (TaN), Ti, Ta, or combinations thereof. The liner layer 127 may be formed of a plurality of layers or a single layer in which different materials are stacked. In addition, the liner layer 127 may be formed by Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or Metal Organic Chemical Vapor Deposition (MOCVD).
A top surface of the wiring 125 may be exposed by the pad layer 127. The liner layer 127 may limit and/or prevent diffusion of a boride-based compound forming the wire 125, and may act as a plating seed layer. In addition, the liner layer 127 may also serve as an adhesion layer between the dielectric layer 121 and the wiring 125, as with the barrier layer 126.
Fig. 2 shows a semiconductor device 100 including an interconnect structure 120 according to another embodiment.
Referring to fig. 2, a liner layer 127 is disposed on an inner wall of the trench 121 a. Here, a pad layer 127 may be disposed between the dielectric layer 121 and the wiring 125 to cover the wiring 125. The liner layer 127 may comprise, for example, titanium nitride (TiN), titanium Tungsten (TiW), tungsten nitride (WN), tantalum nitride (TaN), Ti, Ta, or combinations thereof.
Unlike fig. 1, the device shown in fig. 2 does not necessarily use a barrier layer. That is, the barrier layer may not be formed because the liner layer 127 is capable of limiting and/or preventing the diffusion of boron of the boride-based compound.
Fig. 3A and 3B are diagrams of an example of a method of manufacturing the semiconductor device 100 shown in fig. 1 including the interconnect structure 120. Fig. 3A and 3C are diagrams of an example of a method of manufacturing the semiconductor device 100 shown in fig. 2 including the interconnect structure 120.
Referring to fig. 3A, a dielectric layer 221 including at least one trench 221a is formed on a semiconductor substrate 210. Specifically, the dielectric layer 221 is first formed on the semiconductor substrate 210. Here, the dielectric layer 221 may be formed by a deposition process used in a typical semiconductor manufacturing process, such as Chemical Vapor Deposition (CVD), plasma enhanced CVD (pecvd), or spin coating.
For example, the semiconductor substrate 210 may include a group 4 semiconductor material, a group 3/5 semiconductor compound, or a group 2/6 semiconductor compound. The semiconductor substrate 210 may include multiple layers or a single layer in which different materials are stacked. In addition, the semiconductor substrate 210 may include, for example, a silicon-on-insulator (SOI) substrate or a silicon germanium-on-insulator (SGOI) substrate. The semiconductor substrate 210 may include an undoped semiconductor material or a doped semiconductor material.
The semiconductor substrate 210 may include at least one semiconductor device (not shown). Here, the semiconductor device may include, for example, at least one of a transistor, a capacitor, a diode, and a resistor, but is not limited thereto.
The dielectric layer 221 may include a dielectric material used in a typical semiconductor manufacturing process. For example, the dielectric layer 221 may include silicon oxide, silicon nitride, silicon carbide, silicates, and the like. However, this is merely an example, and other various dielectric materials may be used as the dielectric layer 221. The dielectric layer 221 may also include an organic dielectric material. The dielectric layer 221 may have a multi-layer structure or a single-layer structure in which different materials are stacked.
Next, at least one trench 221a is formed in the dielectric layer 221 to a certain depth. The at least one trench 121a may be formed by, for example, a photolithography process or an etching process. Here, the at least one groove 121a may be formed not to contact the substrate 210 or to contact the substrate 210. Two trenches 221a are formed in the dielectric layer 221 in fig. 3A, wherein one of the trenches 221a is formed not to contact the substrate 210 and the other is formed to contact the substrate 210.
Next, a wiring 225, a liner layer 227, and a barrier layer 226 are formed inside at least one trench 221a formed in the dielectric layer 221. First, a barrier layer 226 and a liner layer 227 are sequentially formed on a surface of the dielectric layer 221. Here, the barrier layer 226 and the liner layer 227 may be formed through a deposition process used in a typical semiconductor manufacturing process.
The barrier layer 226 and the liner layer 227 may comprise, for example, a metal alloy, or a metal nitride. However, examples of the barrier layer 226 and the liner layer 227 are not limited thereto. The barrier layer 226 and the liner layer 227 may have a multilayer structure or a single layer structure in which different materials are stacked.
Next, a wiring 225 is formed on the surface of the pad layer 227 to fill the inside of the at least one trench 221 a. The wiring 225 may be formed using a boride-based compound according to an embodiment by, for example, Chemical Vapor Deposition (CVD), plasma enhanced CVD (pecvd), Physical Vapor Deposition (PVD), electroplating, chemical solution deposition, or electroless plating.
When the wiring 225 is formed by electroplating, a plating seed layer (not shown) for facilitating the electroplating may be formed on the surface of the pad layer 227 before the wiring 225 is formed. When the pad layer 227 serves as a plating seed layer, the plating seed layer may not be formed.
The plating seed layer may include, for example, copper (Cu), a copper alloy, iridium (Ir), an iridium alloy, ruthenium (Ru), or a ruthenium alloy, but this is merely an example.
The wiring 225 may include a boride-based compound according to an embodiment.
The wiring 225 may further include a metal or a metal alloy having excellent conductivity, if necessary. For example, the wiring 225 may include Cu, Ru, Al, Co, W, Mo, Ti, Ta, Ni, Pt, Cr, or an alloy thereof. However, the embodiment is not limited thereto, and other various metals may be used as the wiring 125.
Next, the top surface of the dielectric layer 221, the top surface of the liner layer 227, the top surface of the barrier layer 226, and the top surface of the wiring 225 are processed to be coplanar through a planarization process. The planarization process may include, for example, a Chemical Mechanical Polishing (CMP) process or a grinding process, but is not limited thereto.
The semiconductor device of fig. 1 is completed by the manufacturing process.
A method of manufacturing the semiconductor device of fig. 2 will now be described with reference to fig. 3A and 3C.
The semiconductor device of fig. 2 can be manufactured in the same manner as the semiconductor device of fig. 1, except that: the barrier layer is not formed in the method of manufacturing the semiconductor device of fig. 1.
Referring to fig. 3C, a dielectric layer 221 is formed on the semiconductor substrate 210.
Next, at least one trench 221a is formed in the dielectric layer 221 to a certain depth. Here, the at least one trench 121a may be formed not to contact the semiconductor substrate 210 or to contact the semiconductor substrate 210. Two trenches 221a are formed in the dielectric layer 221 in fig. 3C, wherein one of the trenches 221a is formed not to contact the substrate 210 and the other is formed to contact the substrate 210.
Next, a wiring 225 and a liner layer 227 are formed inside at least one trench 221a formed in the dielectric layer 221. First, a pad layer 227 is formed on a surface of the dielectric layer 221.
Next, a wiring 225 is then formed on the surface of the pad layer 227 to fill the inside of the at least one trench 221 a.
The wiring 225 includes a boride-based compound according to an embodiment.
The pad layer 227 may have a multi-layer structure or a single-layer structure in which different materials are stacked. The pad layer 227 may limit and/or prevent diffusion of boride-based compounds of the wiring, and may also serve as a plating seed layer.
Next, the top surface of the dielectric layer 221, the top surface of the liner layer 227, and the top surface of the wiring 225 are processed to be coplanar through a planarization process, thereby completing the semiconductor device of fig. 2.
A semiconductor device according to an embodiment may include a logic device disposed on a semiconductor substrate. The logic device may be, for example, a Metal Oxide Semiconductor (MOS) transistor. For example, as shown in fig. 4, in an embodiment, the first logic device LD1 may be connected to the wiring 125 through a plug P1, and the second logic device LD2 may be connected to the wiring 125 through a plug P2. Plugs P1 and P2 may include a conductive material, such as a metal, a metal alloy, or one of the boride-based compounds according to embodiments of the present inventive concept. Each of the logic devices LD1 and LD2 may be MOS transistors, but example embodiments are not limited thereto, and other types of devices such as capacitors may be provided instead of the logic devices LD1 and LD 2.
Hereinafter, the quality factor of the boride-based compound according to the embodiment will be described.
The value of the 1D or 3D quality factor of the boride-based compound according to the embodiment is a typical parameter representing the dimensional effect of resistivity, and may be obtained by the following equations 1 and 2.
[ equation 1]
1D quality factor ρ λ ═ ρ X λ1D
[ equation 2]
3D quality factor ρ λ ═ ρ X λ3D
In equations 1 and 2, ρ represents the bulk resistivity, and λ represents the mean free path, λ1DDenotes the mean free path in one direction, and3Drepresents the mean free path in 3D (i.e., bulk).
1D quality factor ρ λ (ρ X λ)1D) Expressing the figure of merit in the in-plane direction, and the 3D figure of merit ρ λ (ρ X λ)3D) Representing the figure of merit for the isotropic state.
The lower the value of the quality factor of the boride-based compound, i.e., the lower the bulk resistivity (ρ 0) of the material and the shorter the mean free path (λ), the more advantageous in maintaining the resistivity, even if the device size is reduced. In addition, this also means that the material can become insensitive to dimensional effects that occur as the size of the device is reduced.
The composition of the boride-based compound is now listed in table 1 below.
[ TABLE 1]
Figure BDA0003174899290000171
Figure BDA0003174899290000181
In this specification, the term "figure of merit" is based on the principle of first sex based on quantum mechanics using a simulation program dimensionAlso receives values obtained from a head simulation package (VASP) and BoltzTrap transmission properties (BoltzTrap), and the figure of merit ρ0λ is obtained by model analysis of the electronic band (band) structure in space and fermi surfaces.
The electronic structure of the material used to measure the quality factor was calculated by projecting imposed planar wave potentials (pbe) using per Burke-ernzerhof (pbe) generalized gradient approximation, setting 500eV to the planar wave energy cutoff, and sampling with 60 x 60K-points.
For a specific Simulation methodology for providing the figure of merit, reference may be further made to the literature entitled "Vienna Ab-inito geometry Package" (written by Georg Kresse and Jurgen Furthmuller, Institut fur materials physics, Universal Wien, Sensenegasse 8, A-1130Wien, Austria, 24.8.2005). The disclosure in this document is incorporated herein by reference in its entirety.
The quality factor can be obtained from the crystal structures of various metal diboride compounds by calculating the density of states (DOS) and the band structure around the fermi level.
The simulation procedure described above can be summarized in table 2 below.
[ TABLE 2]
Figure BDA0003174899290000182
Figure BDA0003174899290000191
In Table 2, DFT is an abbreviation of density functional theory,. tau.is relaxation time,. sigma.tIs the conductivity for the direction t, [ rho ] is the specific resistivity for the direction t, [ dS ] is the differential area of the Fermi surface, [ v ]n，t(k) And | vn(k) L is the fermi velocity for the direction t and the norm of the fermi velocity, respectively, for the crystal momentum k. Alternatively, v can be obtained from the E-k plotn(k)。
In equation 3 of Table 2, τ is the relaxation time, σtIs to forConductivity in the direction t, ptIs the specific resistivity for the direction t, dS is the differential area of the Fermi surface, vn，t(k) And | vn(k) L is the fermi velocity for the direction t and the norm of the fermi velocity, respectively, for the crystal momentum k. Then, using equation 4, the figure of merit ρ0λ may be expressed by the semi-classical boltzmann equation of equation 5.
The description of table 2 will now be explained in further detail.
To calculate the quantum mechanical state of a material, the electron density function based on Density Functional Theory (DFT) is used to describe the distribution of electrons, rather than the wave function. According to this mode, the quantum-mechanical state of the electrons for the material is calculated by: first principle calculations are performed based on a method for solving quantum mechanical equations. The first principle calculation is a calculation using a basic equation having no external parameter.
The electronic state of the material is calculated using VASP (vienna de novo simulation package) code, which is the first principle DFT code. Then, a candidate material group including a two-dimensional electron gas (2DEG) was selected using an Inorganic Crystal Structure Database (ICSD), information on the atomic Structure thereof was input, and then the energy level for electrons was calculated by simulation. Next, for such electrons, an energy density function and a state density function on k-space are calculated.
The electronic structure calculated by DFT computer simulation provides information about the E-k diagram (band structure) and DOS (density of states: density of electronic states, density of electronic states function per energy unit). Depending on the presence of DOS on the maximum (achievable) energy level (E) available for electrons, it can be determined whether a given material is a metallic conductive material (DOS (E) >0) or a semiconductor material (DOS (E) ═ 0).
In order to predict the quality factor of the boride-based compound as the metal conductive material, a semi-classical boltzmann transmission model may be introduced, and the quality factor of the boride-based compound may be analyzed using equations 3 to 5 of table 1.
The evaluation results of the 1D quality factor, the 3D quality factor, and the melting point of the boride-based compound obtained in the above manner are shown in table 3. The melting point of the boride-based compound is measured by Differential Scanning Calorimetry (DSC) and/or Differential Thermal Analysis (DTA). Information about the melting point of boride-based compounds can be found in the known literature.
[ TABLE 3]
Figure BDA0003174899290000201
Referring to table 3, the results show that the boride-based compounds of examples 1-8 have a reduced value of 1D quality factor compared to the copper of comparative example 1.
As shown in table 3, the boride-based compounds of examples 1 to 8 have slightly higher values of 3D quality factor, i.e., 7.5 or less, compared to copper of comparative example 1, but their high melting points may allow semiconductor devices including wires formed therefrom to have improved reliability.
[ TABLE 4 ]
Figure BDA0003174899290000202
Referring to table 4, the boride-based compounds of examples 10 to 12 and 16 have a lower value of 1D quality factor and a higher melting point than copper of comparative example 1, and a semiconductor device including a wire using the same may have improved reliability.
The boride-based compounds of examples 9 and 13 to 15 have equal or higher values of 1D quality factor and higher melting points than the copper of comparative example 1, and semiconductor devices including wires using the same may have improved reliability.
A wiring material for a semiconductor device according to an aspect has a reduced ρ λ or a reduced increment of resistivity due to a reduction in the line width of a wiring, and a melting point thereof can be high, as compared with a copper wiring, thereby maintaining excellent reliability even if the semiconductor device is miniaturized.
Descriptions of features or aspects in various embodiments should typically be considered as available for other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the following claims.

Claims (25)

1. A wiring material for a semiconductor device, the wiring material comprising:
a boride-based compound comprising boron and at least one metal selected from elements of groups 2 to 14.
2. The wiring material according to claim 1, wherein the at least one metal is a group 5 element, a group 6 element, or a combination thereof.
3. The wiring material according to claim 1, wherein the metal is tungsten (W), molybdenum (Mo), tantalum (Ta), niobium (Nb), chromium (Cr), vanadium (V), iron (Fe), nickel (Ni), cobalt (Co), titanium (Ti), zirconium (Zr), hafnium (Hf), uranium (U), magnesium (Mg), manganese (Mn), aluminum (Al), dysprosium (Dy), erbium (Er), lanthanum (La), cerium (Ce), indium (In), gallium (Ga), or a combination thereof.
4. The wiring material according to claim 1, wherein the metal is tungsten (W), tantalum (Ta), chromium (Cr), molybdenum (Mo), vanadium (V), or a combination thereof.
5. The wiring material according to claim 1, wherein the amount of boron in the boride-based compound ranges from 25 atomic% to 88 atomic%.
6. The wiring material according to claim 1, wherein the amount of boron in the boride-based compound ranges from 50 atomic% to 70 atomic%.
7. The wiring material according to claim 1, wherein the boride-based compound is a compound represented by formula 1:
[ formula 1]
MaBb
Wherein M in formula 1 is W, Mo, Ta, Nb, Cr, V, or a combination thereof,
a is a number from 1 to 5, and
b is a number from 1 to 10.
8. The wiring material according to claim 1, wherein the boride-based compound is a compound represented by formula 2:
[ formula 2]
M1aM2cBb
Wherein in the formula 2, the first and second groups,
m1 is W, Mo, Ta, Nb, Cr, Mn, V, Fe, Zr, Ti, Hf, or a combination thereof,
m2 is Al, Ga, In, or a combination thereof,
a is a number from 1 to 5,
b is a number from 1 to 5, and
c is a number from 1 to 10.
9. The wiring material as claimed in claim 1, wherein the boride-based compound is WB2、MoB2、TaB2、NbB2、CrB2、CrB、MoB、VB2、FeB、NiB、Fe2B、Co2B、Ni2B、TiB2、ZrB2、HfB2、UB2、MgB2、MnB2、AlB2、DyB2、ErB2、Mn3B4、DyB4、ErB4、UB4、Mo2B5、W2B5、LaB6、CeB6、DyB6、ErB6、MoAlB、WAlB、Hf2AlB、Hf2GaB、Hf2InB、Ti2AlB、Ti2GaB、Ti2InB、Zr2AlB、Zr2GaB、Zr2InB、Cr2AlB2、Mn2AlB2、Fe2AlB2、Cr4AlB6Or a combination thereof.
10. The wiring material of claim 1, wherein the boride-based compound has a 1D quality factor of 6.7 or less.
11. The wiring material according to claim 1, wherein the boride-based compound has a 1D quality factor of 3-6.2.
12. The wiring material of claim 1, wherein the boride-based compound has a 3D quality factor of 7.5 or less.
13. The wiring material according to claim 1, wherein the boride-based compound has a 3D quality factor of 4.5-7.5.
14. The wiring material according to claim 1, wherein the boride-based compound has a melting point of 1300 ℃ or more.
15. The wiring material according to claim 1, wherein the boride-based compound has a melting point of 2000 ℃ or more.
16. A wiring for a semiconductor type device, the wiring comprising:
the wiring material as claimed in any one of claims 1 to 15.
17. A semiconductor-type device, comprising:
a wiring comprising the wiring material as claimed in any one of claims 1 to 15.
18. The semiconductor device of claim 17, further comprising:
a semiconductor substrate; and
an interconnect structure on the semiconductor substrate, wherein
The interconnect structure includes a dielectric layer on the semiconductor substrate,
the dielectric layer has at least one trench formed therein,
the interconnect structure includes the wiring, an
The wiring is in the trench.
19. The semiconductor device of claim 18, wherein the interconnect structure further comprises a barrier layer covering the wire in the trench.
20. The semiconductor device of claim 18, wherein the trench of the interconnect structure extends through a thickness of the interconnect structure, or
Wherein a depth of the trench is less than a thickness of the interconnect structure.
21. The semiconductor device of claim 18, wherein the interconnect structure further comprises a liner layer covering the wire within the trench.
22. The semiconductor device of claim 21, wherein the liner layer exposes a top surface of the wiring.
23. The semiconductor device of claim 21, wherein the liner layer comprises titanium nitride (TiN), titanium Tungsten (TiW), tungsten nitride (WN), tantalum nitride (TaN), Ti, Ta, or combinations thereof.
24. The semiconductor device of claim 18, wherein the interconnect structure further comprises a barrier layer covering the wire within the trench, and the barrier layer has a single layer structure or a multilayer structure, and the barrier layer exposes a top surface of the wire.
25. The semiconductor device of claim 18, further comprising: a logic device on the semiconductor substrate.
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