CN114121608A

CN114121608A - Semiconductor structure, forming method thereof and film deposition method

Info

Publication number: CN114121608A
Application number: CN202111403864.4A
Authority: CN
Inventors: 贾彩艳; 沈超; 李磊
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2021-11-24
Filing date: 2021-11-24
Publication date: 2022-03-01

Abstract

The invention relates to a semiconductor structure, a forming method thereof and a film deposition method. The forming method of the semiconductor structure comprises the following steps: forming a base, wherein the base comprises a substrate, a dielectric layer positioned on the substrate and a first through hole positioned in the dielectric layer; and forming an isolation layer comprising doping elements on the inner wall of the first through hole, wherein the doping elements are used for increasing the compactness of the isolation layer. The invention is beneficial to prolonging the service life of the semiconductor structure which can be repeatedly used, reducing the manufacturing cost of a semiconductor device and improving the productivity of a semiconductor machine.

Description

Semiconductor structure, forming method thereof and film deposition method

Technical Field

The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor structure, a forming method thereof and a film deposition method.

Background

With the development of the planar flash memory, the manufacturing process of the semiconductor has been greatly improved. In recent years, however, the development of planar flash memories has met with various challenges: physical limits, existing development technology limits, and storage electron density limits, among others. In this context, to solve the difficulties encountered by flat flash memories and to pursue lower production costs of unit memory cells, various three-dimensional (3D) flash memory structures, such as 3D NOR (3D NOR) flash memory and 3D NAND (3D NAND) flash memory, have come into force.

The film deposition process is one of the important process steps in the manufacturing process of 3D NAND and other semiconductor devices. When performing film deposition on a batch of product wafers in a furnace, in order to avoid the influence of Loading Effect (Loading Effect) on the quality of the deposited film, a semiconductor structure for reducing the Loading Effect is placed in the furnace in addition to the batch of product wafers. However, the current semiconductor structure for reducing the loading effect has a short lifetime, a complicated manufacturing process and a high manufacturing cost, which undoubtedly increases the film deposition cost of the product wafer and reduces the throughput of the semiconductor machine.

Therefore, how to increase the lifetime of the semiconductor structure and reduce the manufacturing cost of the semiconductor device is a technical problem to be solved.

Disclosure of Invention

The invention provides a semiconductor structure, a forming method thereof and a film deposition method, which are used for solving the problem of short service life of the semiconductor structure in the prior art, thereby reducing the manufacturing cost of a semiconductor device and improving the productivity of a semiconductor machine.

In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising the steps of:

forming a base, wherein the base comprises a substrate, a dielectric layer positioned on the substrate and a first through hole positioned in the dielectric layer;

and forming an isolation layer comprising doping elements on the inner wall of the first through hole, wherein the doping elements are used for increasing the compactness of the isolation layer.

Optionally, the first through hole is a channel hole; the specific steps of forming the substrate include:

providing a substrate;

forming a dielectric layer on the substrate, wherein the dielectric layer comprises a sacrificial layer and an interlayer insulating layer which are stacked in a direction perpendicular to the substrate;

and forming the channel hole penetrating through the dielectric layer.

Optionally, the specific step of forming the isolation layer including the doping element on the inner wall of the first through hole includes:

and transmitting a mixed gas including a reactant gas for forming the spacer layer and a dopant source gas for forming the dopant element into the first through hole.

Optionally, the volume percentage of the doping source gas in the mixed gas is 1% to 30%.

Optionally, the material of the isolation layer is a crystalline material, and the doping element is used to reduce the grain size of the isolation layer.

Optionally, the isolation layer is made of polysilicon, and the doping element is a carbon element.

Optionally, the isolation layer is of a single-layer structure; alternatively, the first and second electrodes may be,

the isolation layer comprises a plurality of sub-isolation layers which are stacked along the radial direction of the first through hole, and the doping elements can at least increase the compactness of the sub-isolation layer at the outermost layer.

In order to solve the above problem, the present invention also provides a semiconductor structure comprising:

the substrate comprises a substrate, a dielectric layer positioned on the substrate and a first through hole positioned in the dielectric layer;

the isolation layer covers in the inner wall of first through-hole, including the doping element in the isolation layer, the doping element is used for the increase the density of isolation layer.

Optionally, the dielectric layer includes a sacrificial layer and an interlayer insulating layer stacked in a direction perpendicular to the substrate;

the first through hole is a channel hole, and the channel hole penetrates through the dielectric layer.

In order to solve the above problems, the present invention also provides a film layer deposition method, comprising the steps of:

forming a semiconductor structure, wherein the semiconductor structure comprises a base, the base comprises a substrate, a dielectric layer positioned on the substrate and a first through hole positioned in the dielectric layer, an isolation layer covers the inner wall of the first through hole, the isolation layer comprises a doping element, and the doping element is used for increasing the density of the isolation layer;

placing a batch of wafers to be processed and a plurality of semiconductor structures in a reaction chamber, wherein the wafers to be processed comprise second through holes;

forming the functional layer on the inner wall of the second through hole and the surface of the isolation layer at the same time;

and removing the functional layer on the surface of the isolation layer, wherein the semiconductor structure exposing the isolation layer is used for being placed in the reaction chamber together with the wafers to be processed in the next batch.

Optionally, the specific step of removing the functional layer on the surface of the isolation layer includes:

and removing the functional layer by adopting a wet etching process.

Optionally, the functional layer is of a single-layer or multi-layer structure, and the doping element can also increase the etching selection ratio of the isolation layer to each layer in the functional layer.

According to the semiconductor structure, the forming method thereof and the film deposition method provided by the invention, the isolation layer comprising the doping elements is arranged, the density of the isolation layer is increased through the doping elements, the probability that the isolation layer is oxidized by oxygen in the air can be reduced, and the damage to the isolation layer caused by a subsequent treatment process is reduced and even avoided, so that the service life of the semiconductor structure which can be reused is prolonged, the manufacturing cost of a semiconductor device is reduced, and the productivity of a semiconductor machine is improved.

Drawings

FIG. 1 is a flow chart of a method of forming a semiconductor structure in accordance with an embodiment of the present invention;

FIGS. 2A-2B are schematic diagrams of the principal processing structures in forming a semiconductor structure in accordance with embodiments of the present invention;

FIG. 3 is a schematic diagram of a semiconductor structure in accordance with an embodiment of the present invention;

FIG. 4 is a flow chart of a method of film layer deposition in accordance with an embodiment of the present invention;

FIGS. 5A-5E are schematic cross-sectional views of embodiments of the present invention during deposition of a film layer;

FIG. 6 is a schematic view of the structure of the interior of the reaction chamber during deposition of a film layer;

FIGS. 7A-7B are electron micrographs of a prior art barrier layer before and after etching;

FIG. 8 is a graph illustrating the relationship between different concentrations of dopant elements and the grain size of the spacer layer in accordance with one embodiment of the present invention.

Detailed Description

The following detailed description of the semiconductor structure, the forming method thereof, and the film deposition method according to the present invention will be made with reference to the accompanying drawings.

Fig. 6 is a schematic view of the structure of the inside of the reaction chamber during the deposition of the film. Referring to fig. 6, in order to improve the film deposition quality, a semiconductor structure 52 for reducing the loading effect is disposed in the film deposition chamber 50 in addition to a batch of production wafers 53. The semiconductor structure 52 has a via and an isolation layer covering the inner wall of the via. The inner walls of the through holes of the semiconductor structure 52 and the product wafer 53 are subjected to a film deposition process simultaneously. After the film deposition process is finished, the film formed on the inner wall of the through hole is removed, so that the semiconductor structure 52 can be reused. The presence of the isolation layer can prevent damage to the topography of the via or the semiconductor structure 52 when the film layer on the inner wall of the via is removed. The inventors of the present invention have found that the isolation layer is damaged when the film layer on the inner wall of the via hole is removed, thereby reducing the number of times the semiconductor structure 52 can be reused, i.e., reducing the lifetime of the semiconductor structure. Fig. 7A-7B are electron micrographs of a prior art post-etch spacer layer. As shown in fig. 7A and 7B, after the semiconductor structure 52 is reused several times, the isolation layer and the sidewall of the via hole of the semiconductor structure 52 may be damaged during the etching process. However, the production of the semiconductor structure 52 also requires the use of semiconductor equipment and a variety of semiconductor materials, and the shortened lifetime of the semiconductor structure 52 will inevitably increase the production cost of the semiconductor device and reduce the throughput of the semiconductor equipment for processing product wafers.

In order to prolong the service life of the semiconductor structure and reduce the production cost of the semiconductor device, the embodiment provides a method for forming the semiconductor structure, fig. 1 is a flow chart of the method for forming the semiconductor structure in the embodiment of the invention, and fig. 2A-2B are main process structure schematic diagrams in the process of forming the semiconductor structure in the embodiment of the invention. As shown in fig. 1 and fig. 2A to 2B, the method for forming the semiconductor structure includes the following steps:

step S11, forming a base, where the base includes a substrate 20, a dielectric layer 21 located on the substrate 20, and a first through hole 22 located in the dielectric layer 21, as shown in fig. 2A.

Optionally, the first through hole 22 is a trench hole; the specific steps of forming the substrate include:

providing a substrate 20;

forming a dielectric layer 21 on the substrate 20, wherein the dielectric layer 21 comprises a sacrificial layer and an interlayer insulating layer which are stacked in a direction perpendicular to the substrate 20;

forming the channel hole penetrating through the dielectric layer 21.

Specifically, the substrate 20 may be a Si substrate, a Ge substrate, a SiGe substrate, an SOI (Silicon On Insulator) substrate, a GOI (Germanium On Insulator) substrate, or the like. In this embodiment, the substrate 20 is preferably a Si substrate for supporting device structures thereon. The dielectric layer 21 includes the sacrificial layers and the interlayer insulating layers alternately stacked in a direction perpendicular to the top surface of the substrate 20 (i.e., a direction in which the substrate 20 points to the dielectric layer 21). The first through hole is the channel hole penetrating through the dielectric layer 21 in a direction perpendicular to the top surface of the substrate 20. The material of the sacrificial layer may be, but is not limited to, a nitride material (e.g., silicon nitride), and the material of the interlayer insulating layer may be, but is not limited to, an oxide material (e.g., silicon dioxide).

The present embodiment is described by taking an example in which the dielectric layer 21 has a multilayer structure and the first through hole 22 penetrates through the dielectric layer 21. In other specific embodiments, the dielectric layer 21 may have a single-layer structure, and the first through hole 22 may not penetrate through the dielectric layer 21.

Step S12, forming an isolation layer 23 including a doping element on an inner wall of the first via 22, wherein the doping element is used to increase the compactness of the isolation layer 23, as shown in fig. 2B.

The compactness refers to the volume percentage of atoms in a unit cell, namely the ratio of the volume of atoms contained in the unit cell to the volume of the unit cell. In the present embodiment, by increasing the density of the isolation layer 23, on one hand, the probability that the isolation layer 23 is oxidized by oxygen in the air can be reduced, thereby ensuring the performance and structural stability of the semiconductor structure; on the other hand, the isolation layer 23 with high density can effectively prevent an etching agent (e.g., an etchant used in removing a functional layer on the surface of the isolation layer 23) used in a subsequent process from damaging a pattern structure (e.g., the first through hole 22 in the semiconductor structure) in the semiconductor structure, which is equivalent to improving an etching selection ratio between the isolation layer 23 and a functional layer formed on the surface of the isolation layer 23 later. The two aspects of functions can improve the service life of the semiconductor structure, thereby reducing the manufacturing cost of the semiconductor device and improving the productivity of a semiconductor machine for processing product wafers.

The isolation layer 23 may be deposited by a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process. Optionally, the specific step of forming the isolation layer 23 including the doping element on the inner wall of the first via hole 22 includes:

a mixed gas including a reactant gas for forming the spacer layer 23 and a dopant source gas for forming the dopant element is transferred into the first through hole 22.

For example, when the isolation layer 23 is formed by a chemical vapor deposition process, the reaction gas and the dopant source gas may be simultaneously delivered into the first through hole 22, and the reaction gas chemically reacts to form the isolation layer 23 covering the inner wall of the first through hole 22 and the top surface of the dielectric layer 21 (i.e., the surface of the dielectric layer 21 facing away from the substrate 20). Meanwhile, the dopant source gas is doped to the isolation layer 23 with the dopant element generated by plasma formation, forming the isolation layer 23 with the dopant element. A person skilled in the art may select a specific type of the doping element according to actual needs, for example, according to a material selection of the isolation layer 23, which is not particularly limited in this embodiment, as long as the compactness of the isolation layer 23 can be increased.

The ratio of the dopant source gases in the mixed gas is not suitable to be too large because the first via hole 22 in the semiconductor structure has a high aspect ratio, and the too large ratio of the dopant source gases affects the adhesion of the isolation layer 23 on the inner wall of the first via hole 22 (especially on the bottom of the first via hole 22), so that the isolation layer 23 cannot sufficiently cover the inner wall of the first via hole 22. Optionally, the volume percentage of the doping source gas in the mixed gas is 1% to 30%.

Optionally, the material of the isolation layer 23 is a crystalline material, and the doping element is used to reduce the grain size of the isolation layer 23.

Optionally, the isolation layer 23 is made of polysilicon, and the doping element is carbon.

The material of the isolation layer 23 is polysilicon, the doping element is carbon, and the source gas is C₂H₄The description is given for the sake of example. The reaction gas is transferred into the first through hole 22 to generate amorphous silicon, and the doping element generated by the doping source gas is doped into the amorphous silicon. Then, the amorphous silicon is crystallized to form the isolation layer 23 having the doping element and made of polysilicon. In the process of forming the isolation layer 23, the grain size of the finally produced polysilicon can be adjusted by adjusting the proportion of the dopant source gas in the mixed gas. FIG. 8 is a graph illustrating the relationship between different concentrations of dopant elements and the grain size of the spacer layer in accordance with one embodiment of the present invention. For example, as shown in fig. 8, when the dopant source gas occupies 0 volume percent of the mixed gas (i.e., when the dopant source gas is not included), the grain size of the generated polysilicon is 314 nm; when the volume percentage of the doping source gas in the mixed gas is 2%, the grain size of the generated polycrystalline silicon is 278 nm;when the volume percentage of the doping source gas in the mixed gas is 10%, the grain size of the generated polycrystalline silicon is 67 nm; when the volume percentage of the doping source gas in the mixed gas is 20%, the grain size of the generated polysilicon is 19 nm. This is because the doping element (e.g., carbon element) can slow down the deposition rate of the isolation layer 23 (e.g., silicon film layer), so as to reduce the size of the grains (e.g., polysilicon grains) in the isolation layer 23, and increase the compactness of the isolation layer (e.g., polysilicon film layer).

In the present embodiment, the doping element is a carbon element, and the diffusion of the carbon element into the dielectric layer 21 can be avoided due to the weak diffusion property of the carbon element. In other embodiments, a person skilled in the art may also select other elements as the doping element according to actual needs.

Optionally, the isolation layer 23 is a single-layer structure; alternatively, the first and second electrodes may be,

the isolation layer 23 comprises a plurality of sub-isolation layers stacked in the radial direction of the first via 33, and the doping element can increase the density of at least the outermost sub-isolation layer.

Specifically, the isolation layer 23 may have a single-layer structure, so as to simplify the process of the isolation layer, and the doping element is used to increase the compactness of the single-layer isolation layer 23. Alternatively, the isolation layer 23 is a multilayer structure, that is, the isolation layer 23 includes a plurality of sub-isolation layers sequentially stacked in a direction (i.e., the radial direction) in which the inner wall of the first via hole 22 points to the center of the first via hole 22. The doping element may be doped in one or more of the sub-isolation layers, so that at least the density of the outermost sub-isolation layer (i.e. the sub-isolation layer farthest from the inner wall of the first via hole 22 in the radial direction of the first via hole 22) can be increased. When the isolation layer 23 includes a plurality of sub-isolation layers, the materials of the plurality of sub-isolation layers may be different, and the protection of the sidewall of the first via 22 is enhanced by the plurality of sub-isolation layers. The plurality of the present embodiment means two or more.

Moreover, the present embodiments also provide a semiconductor structure. Fig. 3 is a schematic diagram of a semiconductor structure in accordance with an embodiment of the present invention. The semiconductor structure provided by this embodiment mode can be formed by using the method for forming a semiconductor structure shown in fig. 1 and fig. 2A to 2B. As shown in fig. 3, the semiconductor structure includes:

the substrate comprises a substrate 20, a dielectric layer 21 positioned on the substrate 20, and a first through hole 22 positioned in the dielectric layer 21;

the isolation layer 23 covers the inner wall of the first through hole 22, the isolation layer 23 includes a doping element, and the doping element is used for increasing the density of the isolation layer 23.

Optionally, the dielectric layer 21 includes a sacrificial layer and an interlayer insulating layer stacked alternately in a direction perpendicular to the substrate 20 (the sacrificial layer and the interlayer insulating layer stacked alternately are not shown in the figure);

the first through hole 22 is a trench hole, and the trench hole penetrates through the dielectric layer 21.

the isolation layer 23 comprises a plurality of sub-isolation layers stacked in a radial direction of the first via hole 22, and the doping element can increase the density of at least the outermost sub-isolation layer.

Furthermore, the invention also provides a film layer deposition method. Fig. 4 is a flow chart of a film deposition method according to an embodiment of the present invention, fig. 5A to 5E are schematic cross-sectional views of the embodiment of the present invention during film deposition, and fig. 6 is a schematic structural view of the interior of a reaction chamber during film deposition according to the embodiment of the present invention. The semiconductor structure in this embodiment may be formed by using the method for forming the semiconductor structure shown in fig. 1 and fig. 2A to 2B, and the schematic diagram of the semiconductor structure in this embodiment may be shown in fig. 3. As shown in fig. 1, fig. 2A to fig. 2B, fig. 3, fig. 5A to fig. 5E, and fig. 6, the film deposition method includes the following steps:

step S41, forming a semiconductor structure 52, where the semiconductor structure 52 includes a base, the base includes a substrate 20, a dielectric layer 21 located on the substrate 20, and a first through hole 22 located in the dielectric layer 21, an isolation layer 23 covers an inner wall of the first through hole 22, as shown in fig. 5A, the isolation layer 23 includes a doping element, and the doping element is used to increase the density of the isolation layer 23;

step S42, placing a batch of wafers 53 to be processed and a plurality of semiconductor structures 52 in the reaction chamber 50, wherein the wafers 53 to be processed include second through holes;

step S43, forming the functional layer 60 on the inner wall of the second through hole and the surface of the isolation layer 23 at the same time, as shown in fig. 5B;

step S44, removing the functional layer 60 on the surface of the isolation layer 23, as shown in fig. 5C, exposing the semiconductor structure of the isolation layer 23 for being placed in the reaction chamber 50 together with the wafers to be processed in the next batch.

Specifically, the reaction chamber 50 may be a furnace chamber. The reaction chamber 50 has at least two support columns 51 therein, and the support columns 51 have wafer slots therein for receiving wafers. In order to reduce the loading effect on the film deposition process of the wafer 53 to be processed, the wafer 53 to be processed is placed in the middle of the reaction chamber 50, and the semiconductor structures 52 are placed at the bottom and the top of the reaction chamber (i.e. the semiconductor structures 52 are placed at the opposite ends of the wafer 53 to be processed in a batch), as shown in fig. 5.

After the film deposition process in the reaction chamber 50 is completed, the wafer 53 to be processed enters the next process flow, the functional layer 60 generated in the semiconductor structure 52 is removed, and the isolation layer 23 on the inner wall of the first through hole 22 is exposed, so that the semiconductor structure 52 enters the reaction chamber 50 with the wafer to be processed of the next batch when the next film deposition process is performed, so as to reduce the loading effect in the film deposition process of the wafer to be processed of the next batch, that is, the steps in fig. 5A to 5C are performed in a cycle. After performing the circulation steps of fig. 5A to 5C a plurality of times, the thickness of the isolation layer 23 may become thin or the structure of the isolation layer 23 may be damaged, and at this time, the isolation layer 23 may be removed by an etching process, as shown in fig. 5D. Then, the isolation layer 23 is formed on the inner wall of the first via 22 of the semiconductor structure 52 again, as shown in fig. 5E, so as to perform the circulation steps again as shown in fig. 5A-5C.

In the present embodiment, by increasing the density of the isolation layer 23, on one hand, the probability that the isolation layer 23 is oxidized by oxygen in the air can be reduced, thereby ensuring the performance and structural stability of the semiconductor structure; on the other hand, the inner wall of the first through hole 22 can be effectively prevented from being damaged by the etchant used in removing the functional layer 60. Moreover, the doping element can also improve the etching selectivity between the isolation layer 23 and the functional layer 60, and reduce the probability that the isolation layer 23 is removed by an etchant for etching the functional layer 60. The three aspects of functions can improve the service life of the semiconductor structure, thereby reducing the manufacturing cost of the semiconductor device and improving the productivity of a semiconductor machine for processing product wafers.

Optionally, the specific step of removing the functional layer 60 on the surface of the isolation layer 23 includes:

the functional layer 60 is removed by a wet etching process.

In other embodiments, a person skilled in the art may select a dry etching process or other processes to remove the functional layer 60 according to actual needs.

Optionally, the functional layer 60 has a single-layer or multi-layer structure, and the doping element can also increase the etching selection ratio of each of the isolation layer 23 and the functional layer 60.

For example, the first via 22 may be a channel hole, and the functional layer 60 at least includes an electron blocking layer (the material may be an oxide material, such as silicon dioxide) covering the surface of the isolation layer 23, an electron trapping layer (the material may be a nitride material, such as silicon nitride) covering the surface of the electron blocking layer, and a tunneling layer (the material may be an oxide material, such as silicon dioxide) covering the surface of the electron trapping layer, that is, the functional layer 60 forms an ONO structure. The doping of the carbon element (i.e., the doping element) can improve the etching selection ratio between the polysilicon layer (i.e., the isolation layer 23) and the ONO structure and improve the density of the polysilicon layer, thereby reducing the probability of damage to the polysilicon layer when the ONO structure is etched. Moreover, the doping of the carbon element can reduce the deposition rate of the polycrystalline silicon, improve the density of the polycrystalline silicon and reduce the probability of oxidizing the polycrystalline silicon by oxygen in the air.

The present embodiment is described by taking the functional layer 60 as an ONO structure as an example

In the semiconductor structure and the forming method thereof and the film deposition method provided by the present embodiment, by providing the isolation layer including the doping element, the density of the isolation layer is increased by the doping element, so that on one hand, the probability of the isolation layer being oxidized by oxygen in the air can be reduced, and on the other hand, the etching selection ratio of the isolation layer to the functional layer formed on the surface of the isolation layer subsequently can be increased, thereby reducing or even avoiding damage to the isolation layer in the process of removing the functional layer. Both of the two aspects contribute to prolonging the service life of the semiconductor structure which can be repeatedly used, reducing the manufacturing cost of the semiconductor device and improving the productivity of the semiconductor machine.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims

1. A method for forming a semiconductor structure, comprising the steps of:

2. The method of claim 1, wherein the first via is a channel hole; the specific steps of forming the substrate include:

providing a substrate;

and forming the channel hole penetrating through the dielectric layer.

3. The method as claimed in claim 1, wherein the step of forming the isolation layer including the dopant element on the inner wall of the first via hole comprises:

4. The method as claimed in claim 3, wherein the dopant source gas is present in the mixed gas in an amount of 1-30 vol%.

5. The method as claimed in claim 1, wherein the material of the isolation layer is a crystalline material, and the doping element is used to reduce the grain size of the isolation layer.

6. The method as claimed in claim 1, wherein the spacer is made of polysilicon and the dopant element is carbon.

7. The method of claim 1, wherein the isolation layer is a single layer structure; alternatively, the first and second electrodes may be,

8. A semiconductor structure, comprising:

9. The semiconductor structure of claim 8, wherein the dielectric layer comprises a sacrificial layer and an interlayer insulating layer stacked in a direction perpendicular to the substrate;

the first through hole is a channel hole which penetrates through the dielectric layer.

10. The semiconductor structure of claim 8, wherein the isolation layer is a single layer structure; alternatively, the first and second electrodes may be,

11. The semiconductor structure of claim 8, wherein the material of the isolation layer is a crystalline material, and the doping element is configured to reduce a grain size of the isolation layer.

12. The semiconductor structure of claim 8, wherein the material of the spacer layer is polysilicon and the dopant element is carbon.

13. A film layer deposition method, comprising the steps of:

14. The film deposition method of claim 13, wherein the step of removing the functional layer from the surface of the barrier layer comprises:

and removing the functional layer by adopting a wet etching process.

15. The film deposition method of claim 13, wherein the functional layer is a single-layer or multi-layer structure, and the doping element can also increase the etching selectivity of each of the isolation layer and the functional layer.

16. The film deposition method as claimed in claim 13, wherein the material of the isolation layer is a crystalline material, and the doping element is used to reduce the grain size of the isolation layer.

17. The film deposition method of claim 13, wherein the material of the isolation layer is polysilicon, and the doping element is carbon.