CN114121069A - Mixed writing structure and writing method for STT-MRAM - Google Patents

Mixed writing structure and writing method for STT-MRAM Download PDF

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CN114121069A
CN114121069A CN202111337304.3A CN202111337304A CN114121069A CN 114121069 A CN114121069 A CN 114121069A CN 202111337304 A CN202111337304 A CN 202111337304A CN 114121069 A CN114121069 A CN 114121069A
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stt
write
mram
writing
mtj
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姜岩峰
成关壹
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Jiangnan University
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Jiangnan University
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1653—Address circuits or decoders
    • G11C11/1655—Bit-line or column circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1675—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1697—Power supply circuits

Abstract

The invention relates to a mixed type write-in structure and a write-in method for STT-MRAM, and belongs to the technical field of computer storage. The hybrid write structure of the present invention increases the lifetime of the STT-MTJ by connecting two transistors in parallel and adjusting the width of the transistors to properly control the reduced magnitude of the current flowing through the MTJ. Further, since the lifetime of the MTJ device is greatly affected by the voltage, the higher the voltage is, the shorter the lifetime is, the hybrid write structure using the dual power supplies according to the present invention provides different write voltages at different write operations of the STT-MRAM, and by making the first write voltage greater than the second write voltage at the write operation of the STT-MRAM, the current flowing through the STT-MTJ is smaller at the write "0" operation of the STT-MRAM, and simultaneously, the low voltage write is realized, so that the lifetime of the STT-MTJ can be further increased.

Description

Mixed writing structure and writing method for STT-MRAM
Technical Field
The invention relates to a mixed type write-in structure and a write-in method for STT-MRAM, and belongs to the technical field of computer storage.
Background
Spin-transfer torque Magnetic random access memory (Spin-transfer torque Magnetic RAM, STT-MRAM) is a new type of nonvolatile Magnetic random access memory that enables information writing by Spin current. The core of the STT-MRAM memory cell is a Magnetic Tunnel Junction (MTJ). STT-MRAM is considered to be one of the most potential new memories replacing Flash, and has wide application prospect in the fields related to computer storage.
Information storage for STT-MRAM relies on write operationsTo do so, the study of the write operation is critical to STT-MRAM. The memory cell in STT-MRAM consists of a transistor (denoted T) for access control of the memory cell and a non-volatile memory device (denoted R) for storing binary data, called 1T1R non-volatile memory cell. FIG. 1 shows a conventional 1T1R type write structure for STT-MRAM, in which the bidirectional write operation is performed by the same STT-MTJ and transistor, and the resistance of the STT-MTJ is switched according to different current magnitudes and directions, so that when writing current IWThe STT-MRAM can only complete the write operation correctly when the critical switching current is larger than that of the STT-MTJ and the duration is larger than the switching delay time. The writing principle of the writing structure is shown in fig. 1 as follows: a write voltage is applied across the STT-MRAM, generating a write current. When the Source Line (SL) of STT-MRAM is connected with the writing voltage VWWhen the Bit Line (BL) is connected with GND, the current flowing through the STT-MTJ is from the fixed layer to the free layer, and on the premise of meeting the size and duration of the overturning current, the resistance value of the STT-MTJ is switched to a high-resistance AP state, and the STT-MRAM writes information '1'; when the bit line receives the write voltage VWWhen the source line is grounded, writing current flows from BL to SL of the STT-MRAM, the current flowing through the STT-MTJ flows from the free layer to the fixed layer, on the premise of meeting the size and duration of the flip current, the resistance value of the STT-MTJ is switched to the low-resistance P state, and the STT-MRAM writes information '0'.
The write operation of STT-MRAM requires a bidirectional current in order to program information to the magnetization direction of the MTJ free layer. When current flows from BL to SL, the overdrive voltage is V due to the source ground of transistor MW-Vth(i.e., Vov ═ V)W-VthIn which V isthIs the transistor threshold voltage); when the current flows from SL to BL, the MTJ acts as a negative feedback to limit the current, and the bulk effect (V) is present in this caseSB<0) Also reduces the overdrive voltage of the transistor, so that the overdrive voltage (V) of the transistor is now the same with respect to the above operationOV＝VW-(Vth+ΔVth_Body)-VOS) And becomes smaller. The bi-directional current requirements must be met when designing the width of the transistor. On-goingIn conventional circuit designs, the width of the access transistor is usually the worst case width, i.e. the maximum current supply. Meanwhile, since the write current needs to be larger than the critical flip current to complete the write operation, a high write current is required, directly increasing the dynamic power consumption and the total write energy cost.
In the conventional 1T1R structure, STT-MRAM suffers from write asymmetry in the bi-directional write operation due to the effect of process variations on the STT-MTJ and the transistor. In order to ensure the writing capability of the memory cell, the size of the access transistor is usually selected to be the largest, and this selection criterion may be referred to as the "worst case" criterion. Thus, the conventional 1T1R structure can cause the problem of excessive write current in one direction for STT-MRAM.
Disclosure of Invention
In order to solve the problem of excessive writing current caused by the asymmetry of writing in the conventional 1T1R structure, the invention provides a novel dual-power hybrid writing structure applied to STT-MRAM, which adopts an on-demand standard when the size of a transistor is set.
The invention provides a mixed type writing structure for STT-MRAM, which is a writing operation structure of the mixed type structure with the on-demand selection standard. When the STT-MRAM writes a "0", the access transistor selects transistor M1, which is smaller in size, to provide the write current because the write current required is smaller, and when writing a "1", the transistor M1 is used to provide the write current in parallel with transistor M2 because the write current required is larger. In the hybrid write structure of the present invention, WM1、WM2Respectively representing the widths of transistor M1, transistor M2, and transistor M3.
According to the technical scheme of the invention, the purpose of adjusting the current can be achieved by adjusting the width-to-length ratio of the transistor so as to meet the requirement of turning over the current. At the same voltage, the larger the width-to-length ratio of the transistor, the larger the corresponding current. In addition, in circuit analysis, the resistance of the MTJ device is generally considered to be invariant with current changes, and is a passive element, so that the current flowing through the MTJ is the sum of the currents of the transistors.
According to the technical solution of the present invention, a hybrid write structure for STT-MRAM is first proposed, as shown in fig. 2, the write structure includes: an STT-MTJ, a first transistor M1 and a second transistor M2, the first transistor M1 and the second transistor M2 being connected in parallel and connected to the STT-MTJ.
When the write structure executes write operation, the source lines SL1 and SL2 of STT-MRAM are terminated with write voltage VWWhen a bit line BL is terminated with GND, a write current flows from a fixed layer to a free layer of the STT-MTJ, and the STT-MRAM carries out write 1 operation;
when bit line BL of STT-MRAM is terminated with write voltage VWWhen the source line SL1 of the STT-MRAM is connected with GND, the second transistor M2 is in a cut-off state, the writing current flows from the free layer to the fixed layer of the STT-MTJ, and the STT-MRAM writes to '0'.
According to the technical scheme of the invention, when the write operation is executed, the SL1 and SL2 of the STT-MRAM are terminated by the write voltage VWAnd when the BL is terminated with GND, the STT-MRAM carries out writing 1 operation. The write current I flowing through the MTJ at this timeW1Are commonly provided by transistors M1 and M2, in circuit analysis, two parallel transistors are simply equivalent to a width-to-length ratio that becomes a superposition of two transistors, or twice that of the same single transistor, since the width W of the parallel transistors is WM1+WM2And is thus IW1＝IM1+IM2. Thereby writing voltage VWAs such, the STT-MRAM of FIGS. 1 and 2 has equal current flow through the MTJ during the write of a "1". When the STT-MRAM writes a "0", the BL terminal of the STT-MRAM is connected to the write voltage VWSL1 is connected to GND, transistor M2 is turned off by the control of the enable terminal, and the write current I is then appliedW0Provided by transistor M1. In the hybrid write architecture shown in FIG. 2IW0＝IM1And in FIG. 1IW0＝IM1+IM2>IM1Therefore, in the hybrid write structure of fig. 2, at the time of writing "0", the current flowing through the MTJ is smaller, achieving a reduction in writing at the time of writing "0"The purpose of the incoming current.
Fig. 3 is a resistance model diagram of the hybrid write structure of fig. 2 according to the present invention. In FIG. 3, when the STT-MRAM is ready to write data "1", the resistance R of the STT-MTJ isMTJ＝RAPResistance value R of transistorON1＝RM1//RM2Write current IW1＝VW/(RAP+RM1//RM2). In FIG. 3, when the STT-MRAM is ready to write data "0", the resistance R of the STT-MTJ isMTJ＝RPResistance value R of transistorON0＝RM1Write current IW0＝VW/(RP+RM1). Due to RAP>RP，RAP+RM1>RP+RM1//RM2Whereby RP+RM1And RAP+RM1//RM2The magnitude between the two is not determinable, and therefore, at the same write voltage VWIn the case, I cannot be necessarily satisfiedW1>IW0。
In view of the above problems, the inventors have considered the TMR value of MTJ devices in STTM-RAM when designing the above hybrid write structure for STT-MRAM, TMR ═ RP/(RP+RAP) When the TMR value is greater than 150%, the hybrid write architecture of the present invention can satisfy IW1>IW0The requirements of (1).
Furthermore, because the service life of the MTJ device is greatly influenced by voltage, the higher the voltage is, the shorter the service life is, the invention also provides a hybrid write structure adopting double power supplies, which provides different write voltages for the hybrid write structure for the STT-MRAM, namely, the consistent write voltage is formulated for write operations in different directions, so as to realize low write voltage and improve the service life of the MTJ device.
According to the technical scheme of the invention, the hybrid writing structure adopting double power supplies comprises: an STT-MTJ, a first transistor M1 and a second transistor M2, the first transistor M1 and the second transistor M2 being connected in parallel and connected to the STT-MTJ; when the writing structure executes a writing operation, when source lines SL1 and SL2 of an STT-MRAM are terminated with a first writing voltage, a bit line BL of the STT-MRAM is terminated with GND, a writing current flows from a fixed layer of the STT-MTJ to a free layer, and the STT-MRAM performs a writing '1' operation; when the bit line BL of the STT-MRAM is terminated by writing a second write voltage, the source line SL1 of the STT-MRAM is terminated by GND, the second transistor M2 is in an OFF state, and a write current flows from the free layer of the STT-MTJ to the fixed layer, the STT-MRAM performing a write "0" operation.
According to the technical scheme of the invention, in the hybrid writing structure adopting the dual power supplies, the first voltage is greater than the second voltage.
The present invention further provides a hybrid write method for STT-MRAM, the write method employing the hybrid write structure of the present invention, the write method comprising:
when the writing structure executes a writing operation, when source lines SL1 and SL2 of the STT-MRAM are terminated to write a first writing voltage, and a bit line BL is terminated to GND, a writing current flows from a fixed layer to a free layer of the STT-MTJ, and the STT-MRAM carries out a writing '1' operation;
when the bit line BL of the STT-MRAM is terminated by the second write voltage, the source line SL1 of the STT-MRAM is connected to GND, the second transistor M2 is placed in the OFF state, a write current flows from the free layer to the fixed layer of the STT-MTJ, and the STT-MRAM performs a write "0" operation.
According to the writing method of the present invention, the first writing voltage is the same as the second writing voltage or the first writing voltage is greater than the second writing voltage.
According to the write structure and the write method of the invention, the STT-MRAM further increases the useful life of the STT-MTJ at the time of write operation by making the first write voltage greater than the second write voltage so that the current flowing through the STT-MTJ is smaller at the time of write "0" operation of the STT-MRAM while enabling low voltage writing.
The invention has the beneficial effects that:
since the voltage applied to the MTJ is determined by the voltage divider formed by the transistor and the MTJ, the hybrid write architecture and method of the present invention properly controls the magnitude of the decrease in current through the MTJ by connecting the two transistors in parallel and adjusting the width of the transistors. The reduction of excess current and voltage on the STT-MTJ relieves the stress condition of the tunneling oxide, which is very effective in increasing the lifetime of the STT-MTJ.
Because the service life of the MTJ device is greatly influenced by voltage, the higher the voltage is, the shorter the service life is, the hybrid write structure adopting the dual power supplies provided by the invention provides different write voltages for the write operation of the STT-MRAM, namely, the consistent write voltage is formulated for the write operation in different directions, and the low write voltage is realized.
According to the dual-power hybrid type writing structure and the writing method, the first writing voltage is larger than the second writing voltage when the STT-MRAM is in writing operation, so that the current flowing through the STT-MTJ is smaller when the STT-MRAM is in writing 0 operation, low-voltage writing is realized, the writing power consumption is reduced, and meanwhile, the service life of the STT-MTJ can be further prolonged.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of a conventional 1T1R type write structure;
FIG. 2 is a schematic diagram of a hybrid write architecture of the present invention;
FIG. 3 is a resistance model diagram of a hybrid write structure of the present invention;
FIG. 4 is a schematic diagram of a dual power hybrid write architecture of the present invention;
FIG. 5 is a comparison graph of transient simulations of a 1T1R type write structure and a hybrid write structure of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
The first embodiment is as follows:
according to the technical solution of the present invention, a hybrid write structure for STT-MRAM is proposed in this embodiment as shown in fig. 2, where the write structure includes: an STT-MTJ, a first transistor M1 and a second transistor M2, the first transistor M1 and the second transistor M2 being connected in parallel and connected to the STT-MTJ.
When the write structure executes write operation, the source lines SL1 and SL2 of STT-MRAM are terminated with write voltage VWWhen a bit line BL is terminated with GND, a write current flows from a fixed layer to a free layer of the STT-MTJ, and the STT-MRAM carries out write 1 operation;
when bit line BL of STT-MRAM is terminated with write voltage VWWhen the source line SL1 of the STT-MRAM is connected with GND, the second transistor M2 is in a cut-off state, the writing current flows from the free layer to the fixed layer of the STT-MTJ, and the STT-MRAM writes to '0'.
The write structure shown in FIG. 2 is used to perform a write operation when the SL1 and SL2 of the STT-MRAM are terminated by a write voltage VWWhen BL is connected with GND, current flows from the fixed layer of STT-MTJ to the free layer, and the memory carries out write '1'. The write current I flowing through STT-MTJ at this timeW1Are commonly provided by transistors M1 and M2, therefore, IW1＝IM1+IM2. Therefore, at the writing voltage VWAs such, the STT-MRAM of FIGS. 1 and 2 flow equal current through the STT-MTJ during the write of a "1".
When the STT-MRAM writes "0", the BL terminal is connected to the write voltage VWSL1 is connected to GND, transistor M2 is in cut-off state by enabling end control, current flows from BL end to SL1 end, and write current I is in this caseW0The write current flows from the free layer to the fixed layer of the MTJ, provided by transistor M1. In the write structure of FIG. 2IW0＝IM1And in FIG. 1IW0＝IM1+IM2>IM1So in a write "0" operation, the write structure of FIG. 2 flows throughThe current of STT-MTJ is smaller, and the purpose of reducing the writing voltage is achieved.
Since the voltage applied to the STT-MTJ is determined by the voltage divider formed by the transistor and the STT-MTJ, the reduced magnitude of the current through the STT-MTJ can be appropriately controlled by adjusting the width of the transistor. The reduction of excess current and voltage on the STT-MTJ relieves the stress condition of the tunneling oxide, very effectively increasing the lifetime of the STT-MTJ.
Fig. 3 is a resistance model diagram of a novel hybrid write structure proposed in this patent. In FIG. 3, when the STT-MRAM is ready to write data "1", the resistance R of the STT-MTJ isMTJ＝RAPResistance value R of transistorON1＝RM1//RM2Write current IW1＝VW/(RAP+RM1//RM2). The left side of FIG. 3 shows the operation of writing a "1", the resistance R of the STT-MTJMTJOriginally RPResistance R of STT-MTJ by writing "1" operationMTJ＝RAP. In FIG. 3, when the STT-MRAM writes a "0" operation, the resistance R of the STT-MTJ isMTJ＝RPResistance value R of transistorON0＝RM1Write current IW0＝VW/(RP+RM1). Due to RAP>RP，RAP+RM1>RP+RM1//RM2Whereby RP+RM1And RAP+RM1//RM2The magnitude between the two is not determinable, and therefore, at the same write voltage VWIn the case, I cannot be necessarily satisfiedW1>IW0。
In view of the above problems, the inventors have considered the TMR value of MTJ devices in STTM-RAM when designing the above hybrid write structure for STT-MRAM, TMR ═ RP/(RP+RAP) When the TMR value is greater than 150%, the hybrid write structure of this embodiment can satisfy IW1>IW0The requirements of (1).
Example two:
because the service life of the MTJ device is greatly affected by the voltage, the higher the voltage is, the shorter the service life is, the embodiment provides a hybrid write structure using dual power supplies to provide different write voltages for the above hybrid write structure for STT-MRAM, that is, a consistent write voltage is formulated for write operations in different directions, so as to implement a low write voltage, and further improve the service life of the MTJ device.
In this embodiment, a dual power supply structure is adopted to provide different write voltages for the hybrid write structure of the present invention, that is, a consistent write voltage is formulated for write operations in different directions, so as to implement a low write voltage and further reduce write power consumption.
The hybrid write structure using dual power supplies includes: an STT-MTJ, a first transistor M1, and a second transistor M2; the first transistor M1 and the second transistor M2 are connected in parallel and are connected with the STT-MTJ; when the writing structure executes a writing operation, when source lines SL1 and SL2 of an STT-MRAM are terminated with a first writing voltage, a bit line BL of the STT-MRAM is terminated with GND, a writing current flows from a fixed layer of the STT-MTJ to a free layer, and the STT-MRAM performs a writing '1' operation; when the bit line BL of the STT-MRAM is terminated by writing a second write voltage, the source line SL1 of the STT-MRAM is terminated by GND, the second transistor M2 is in an OFF state, and a write current flows from the free layer of the STT-MTJ to the fixed layer, the STT-MRAM performing a write "0" operation.
According to the technical scheme of the embodiment, in the hybrid writing structure adopting the dual power supplies, the first voltage is greater than the second voltage.
Fig. 4 shows a dual power hybrid writing structure proposed in this embodiment. In this structure, a low voltage V is used when the STT-MRAM writes a "1"LAs the write voltage, a high voltage V is used when writing "0HThe writing voltage is used, so that when the STT-MRAM is used for writing '0', the current flowing through the STT-MTJ is smaller, low-voltage writing in the writing '0' operation is realized, the writing power consumption is reduced, and the service life of the MTJ device is further prolonged.
Example three:
the present embodiment further provides a hybrid writing method for STT-MRAM, the writing method using the hybrid writing structure according to the first embodiment or the second embodiment of the present invention, the writing method including:
when the writing structure executes a writing operation, when source lines SL1 and SL2 of the STT-MRAM are terminated to write a first writing voltage, and a bit line BL is terminated to GND, a writing current flows from a fixed layer to a free layer of the STT-MTJ, and the STT-MRAM carries out a writing '1' operation;
when the bit line BL of the STT-MRAM is terminated by the second write voltage, the source line SL1 of the STT-MRAM is connected to GND, the second transistor M2 is placed in the OFF state, a write current flows from the free layer to the fixed layer of the STT-MTJ, and the STT-MRAM performs a write "0" operation.
According to the writing method of the present invention, the first writing voltage is the same as the second writing voltage or the first writing voltage is greater than the second writing voltage.
According to the writing method of the invention, the STT-MRAM enables a smaller current to flow through the STT-MTJ when writing '0' by making the first writing voltage larger than the second writing voltage when writing, and simultaneously realizes low voltage writing, reduces writing power consumption and can further increase the service life of the STT-MTJ.
Example four:
FIG. 5 is a comparison graph of transient simulation of the 1T1R type write structure of FIG. 1 and the hybrid write structure proposed by the present invention. Assuming the initial state of the STT-MRAM is "0," each write has a duration of 10 ns. The conventional mode of construction shown in fig. 1 employs a write voltage of 0.9V. When the STT-MRAM carries out the writing process from '0' to '1', the writing currents of the two structures are kept equal, but because the access transistor of the novel structure is formed by connecting two transistors in parallel, the overall resistance of the access transistor is smaller than that of the access transistor of the traditional structure, and therefore, the required writing voltage is smaller under the requirement of the same writing circuit. Write voltage V for writing "1" of final hybrid structureLIt was 0.6V. Write voltage of conventional structure during STT-MRAM from 1 to 0Still 0.9V.
Since the present invention adopts the mixed type write structure, the write voltage can be properly selected according to the current required for writing '0', so that the write voltage V for writing '0' is selected at this positionHAnd was 0.68V. As can be seen from FIG. 5, when the STT-MRAM goes from "0" to "1", the write current is about 120 μ A, and the write delay is about 1.6 ns; when the STT-MRAM is going from "1" to "0", the write voltage for the new structure is 72.59 μ A, while the write voltage for the conventional structure is about 107.67 μ A, which reduces the write current by 30%. However, since the delay is inversely proportional to the magnitude of the current, the write delay of the hybrid structure of the present invention is about 0.4ns, about 2.3ns greater than that of the conventional structure. In the normal writing operation process, in order to ensure successful writing, a larger margin is usually set for the duration of the writing voltage, at this time, after the writing operation from "1" to "0" is successful, the writing current becomes larger, and if the writing operation is not terminated in time, a larger energy loss will be caused, as can be seen from fig. 5, the hybrid writing structure proposed by the present invention, even after the writing is successful, the writing current still remains within 100 μ a, and can save at least thirty percent of power consumption for the whole writing operation.
Some steps in the embodiments of the present invention may be implemented by software, and the corresponding software program may be stored in a readable storage medium, such as an optical disc or a hard disk.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims (10)

1. A hybrid write structure for STT-MRAM, the write structure comprising: an STT-MTJ, a first transistor M1, and a second transistor M2; wherein the first transistor M1 and the second transistor M2 are connected in parallel and are connected to the STT-MTJ;
when the write structure is used for performing write operation, when the source line SL1 of STT-MRAM is connected with the source line SL1 of STT-MRAMSL2 termination write voltage VWWhen a bit line BL is terminated with GND, a write current flows from a fixed layer to a free layer of the STT-MTJ, and the STT-MRAM carries out write 1 operation;
when bit line BL of STT-MRAM is terminated with write voltage VWWhen the source line SL1 of the STT-MRAM is connected with GND, the second transistor M2 is in a cut-off state, the writing current flows from the free layer to the fixed layer of the STT-MTJ, and the STT-MRAM writes to '0'.
2. The hybrid write structure for an STT-MRAM of claim 1, wherein the STT-MRAM writes a write current I when writing a "0" operationW0Provided by the first transistor M1, IW0＝IM1。
3. The hybrid write structure for an STT-MRAM of claim 1, wherein the STT-MRAM writes a current I when writing a "1" operationW1Provided in common by the first transistor M1 and the second transistor M2, IW1＝IM1+IM2。
4. The hybrid write structure for an STT-MRAM of any of claims 1-3, wherein the STT-MRAM has a write current I for a write "0" operationW0Less than the write current I of the STT-MRAM for a write "1" operationW1。
5. A hybrid write structure for STT-MRAM, the write structure comprising: an STT-MTJ, a first transistor M1, and a second transistor M2; wherein the first transistor M1 and the second transistor M2 are connected in parallel and are connected to the STT-MTJ;
when the writing structure executes a writing operation, when source lines SL1 and SL2 of an STT-MRAM are terminated with a first writing voltage, a bit line BL of the STT-MRAM is terminated with GND, a writing current flows from a fixed layer to a free layer of the STT-MTJ, and the STT-MRAM carries out a writing '1' operation;
when the bit line BL of the STT-MRAM is terminated by the write second write voltage, the source line SL1 of the STT-MRAM is terminated by GND, the second transistor M2 is in the OFF state, the write current flows from the free layer to the fixed layer of the STT-MTJ, and the STT-MRAM performs the write "0" operation.
6. The hybrid write structure for an STT-MRAM of claim 5, wherein the first write voltage is greater than the second write voltage.
7. A hybrid write method for STT-MRAM, the write method employing the hybrid write structure of any of claims 1 or 5, the write method comprising:
when the writing structure executes a writing operation, when source lines SL1 and SL2 of the STT-MRAM are terminated with a first writing voltage, a bit line BL is terminated with GND, a writing current flows from a fixed layer to a free layer of the STT-MTJ, and the STT-MRAM carries out a writing '1' operation;
when the bit line BL of the STT-MRAM is terminated by the second write voltage, the source line SL1 of the STT-MRAM is connected to GND, the second transistor M2 is placed in the OFF state, a write current flows from the free layer to the fixed layer of the STT-MTJ, and the STT-MRAM performs a write "0" operation.
8. The hybrid write method for an STT-MRAM of claim 7, wherein the first write voltage is the same as the second write voltage.
9. The hybrid write method for an STT-MRAM of claim 7, wherein the first write voltage is greater than the second write voltage.
10. The hybrid writing method for an STT-MRAM of claim 7, wherein the STT-MRAM is written by making a first write voltage greater than the second write voltage such that the STT-MRAM has less current flow through the STT-MTJ and enables low voltage writing when writing a "0" operation.
CN202111337304.3A 2021-11-12 2021-11-12 Mixed writing structure and writing method for STT-MRAM Pending CN114121069A (en)

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