CN114116594A - Multi-interface compatible extension system based on SRIO bus and communication method - Google Patents

Abstract

The application belongs to the technical field of data processing, and particularly relates to a multi-interface compatible extension system based on an SRIO bus and a communication method. The system comprises a CPU (central processing unit) and an FPGA (field programmable gate array) chip, wherein the CPU is connected with the FPGA through an SRIO (serial input/output) interface, and a plurality of external devices are connected to pins of the FPGA through an interface bus; the CPU comprises at least one OUTBOUND space, a plurality of interface intervals are divided in the space, each interface interval corresponds to a register list, protocol parameters of bus communication between the FPGA and each external device are recorded in the register list, the FPGA maps control data to corresponding external device interface IPs according to the interface interval distribution information of the OUTBOUND space, and register configuration and data receiving and sending control of various bus interfaces are completed by each interface IP core according to the control data. According to the method and the device, the interface resource requirements of the target CPU are reduced, the type selection range of the CPU is widened, the requirements of the radar information processing system on different interfaces are greatly met by utilizing FPGA logic development, and the development efficiency of the radar processing module is improved.

Description

Multi-interface compatible extension system based on SRIO bus and communication method

Technical Field

The application belongs to the technical field of data processing, and particularly relates to a multi-interface compatible extension system based on an SRIO bus and a communication method.

Background

The radar is the eyes of an airplane, and is a civil aviation system or military equipment, and the radar system is required to have high information processing speed, high precision and good real-time performance from the aspects of safety, reliability, quick response, accurate fighting and striking and the like. Therefore, the selection of high performance CPU, high speed data communication bus, and high reliability communication node is an important design consideration for technical experts.

At present, the development of embedded products is greatly promoted by the operation speed, the operation power consumption, the interface types and the like of PowerPC series CPUs of the Feichale company, DSPs of the TI company, domestic Loongson CPUs, Feiteng CPUs and the like, but the interfaces of the CPUs are single generally and cannot meet the requirements of radar information processing on various interfaces and bus protocols of different types. On the other hand, the rapid development of programmable logic devices (FPGAs), such as Xilinx, national microelectronics, etc., provides a large number of general IO and high-speed GTP for design, and can be used for compatible design of various interfaces, but the logic programming is complex, the software flow control difficulty is high, and certain trouble is brought to engineering implementation.

In the prior art, a CPU is usually connected to an external device through a local bus, or connected to an FPGA through the local bus, and the FPGA preprocesses radar data of the external device and transmits the data to the CPU through the local bus. However, the external device or the FPGA is connected through the local bus, the local bus needs to be changed along with the replacement of the external device, and in the process of processing the radar signal, the number of the local bus is increased to twenty-three along with the increase of the external device, so that the subsequent interface compatible expansion becomes more and more difficult.

Disclosure of Invention

In order to solve at least one of the above technical problems, the present application provides a multi-interface compatible extension system and a communication method based on SRIO bus. According to the method, the CPU and the FPGA are subjected to extended design through high-speed bus docking, so that the design requirements of the radar on different interfaces can be met, and great convenience is brought to flexible development of system control software.

The application provides a multi-interface compatible extension system based on an SRIO bus, which comprises a processor CPU and an FPGA chip, wherein the processor CPU is connected with the FPGA chip through the SRIO interface, and a plurality of external devices are connected to pins of the FPGA chip through an interface bus; the processor CPU comprises at least one OUTBOUND space, a plurality of interface intervals are divided in the OUTBOUND space, each interface interval corresponds to a register list, protocol parameters of bus communication between the FPGA and each external device are recorded in the register list, the FPGA chip is configured to map control data to corresponding external device interface IPs according to the interface interval distribution information of the OUTBOUND space, and each interface IP core completes register configuration and data receiving and sending control of various bus interfaces according to the control data.

Preferably, the size of the interface section is 1MB to 4 MB.

Preferably, the processor CPU performs SRIO communication with the FPGA chip by using write operation NWRITE, stream write operation switch, or read operation NREAD through OUTBOUND address mapping.

Preferably, the FPGA chip communicates data with an external bus interface of an external device through its GPIO pin.

Preferably, the FPGA chip communicates data with an external bus interface of an external device through its GTP pin.

Preferably, the external device includes an SRIO device, a PCIe device, a PLB device, an SPI device, an IIC device, and a UART device, the FPGA chip communicates with the SRIO device through an SRIO bus, communicates with the PLB device through a PLB bus, communicates with the SPI device through an SPI bus, communicates with the IIC device through an IIC bus, and communicates with the UART device through a UART bus, correspondingly, an SRIO interface section, a PCIe interface section, a PLB interface section, an SPI interface section, an IIC interface section, and a UART interface section are disposed in an outband space of the processor CPU, a register list in the SRIO interface section records configuration parameters and transceiving control parameters of SRIO bus communication, a register list in the PCIe interface section records configuration parameters and transceiving control parameters of PCIe bus communication, a register list in the PLB interface section records configuration parameters and transceiving control parameters of PLB bus communication, the register list in the SPI interface interval records configuration parameters and transceiving control parameters of SPI bus communication, the register list in the IIC interface interval records configuration parameters and transceiving control parameters of IIC bus communication, and the register list in the UART interface interval records configuration parameters and transceiving control parameters of UART bus communication.

A second aspect of the present application provides a communication method for a multi-interface compatible extension system based on an SRIO bus, where the communication method is performed by using the multi-interface compatible extension system based on the SRIO bus, and includes:

determining external equipment and an interface bus which need to be communicated, and writing interface configuration data associated with the interface bus into a corresponding address of an OUTBOUND space of a CPU (central processing unit) of a processor to form SRIO data;

sending SRIO data of corresponding addresses to the FPGA chip;

after receiving SRIO data of a CPU (central processing unit) of the processor, the FPGA chip maps the SRIO data into control instructions and data read-write instructions of various interfaces according to a protocol and controls an IP (Internet protocol) core of a corresponding interface in the FPGA to complete interface initialization;

and sending the instruction and the data to each interface through an interface bus protocol IP core so as to control the external equipment to perform read-write operation.

Preferably, the FPGA chip is configured to complete development and packaging of various interface bus protocol IP cores.

The SRIO bus-based multi-interface compatible expansion method reduces the interface resource requirements of the target CPU, widens the model selection range of the CPU, improves the development efficiency of the CPU, greatly meets the requirements of the radar information processing system on different interfaces by utilizing FPGA logic development, improves the development efficiency of a radar processing module, and is beneficial to the promotion of the triplex work of a radar processing platform. The method and the device can be applied to the hardware interface compatible extension of various systems and can be applied to three-system types of various processing platforms.

Drawings

Fig. 1 is a system block diagram of a preferred embodiment of the SRIO bus-based multi-interface compatible extension system of the present application.

Fig. 2 is a schematic diagram of OUTBOUND space division and corresponding mapping between OUTBOUND space division and various interface bus protocol IP cores according to the embodiment shown in fig. 1.

Detailed Description

In order to make the implementation objects, technical solutions and advantages of the present application clearer, the technical solutions in the embodiments of the present application will be described in more detail below with reference to the accompanying drawings in the embodiments of the present application. In the drawings, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The described embodiments are some, but not all embodiments of the present application. The embodiments described below with reference to the drawings are exemplary and intended to be used for explaining the present application, and should not be construed as limiting the present application. All other embodiments obtained by a person of ordinary skill in the art without any inventive work based on the embodiments in the present application are within the scope of protection of the present application. Embodiments of the present application will be described in detail below with reference to the drawings.

The application provides a multi-interface compatible extension system based on an SRIO bus, which comprises a processor CPU and an FPGA chip, wherein the processor CPU is connected with the FPGA chip through the SRIO interface, and a plurality of external devices are connected to pins of the FPGA chip through an interface bus; the processor CPU comprises at least one OUTBOUND space, a plurality of interface intervals are divided in the OUTBOUND space, each interface interval corresponds to a register list, protocol parameters of bus communication between the FPGA and each external device are recorded in the register list, the FPGA chip is configured to map control data to corresponding external device interface IPs according to the interface interval distribution information of the OUTBOUND space, and each interface IP core completes register configuration and data receiving and sending control of various bus interfaces according to the control data.

The system comprises a CPU chip, an FPGA chip and various bus interface devices, wherein the CPU receives and transmits data with the external bus interface devices through an SRIO bus to complete initialization configuration of each interface, software protocol transmission and control processing of the devices. The CPU is connected with the FPGA through an SRIO bus, the CPU controls an IP core in the FPGA to complete interface initialization by sending SRIO data of corresponding addresses according to divided interface spaces, interface data are sent and received, the FPGA completes development and packaging of IP cores of various interface bus protocols, the FPGA receives the SRIO data of the CPU and then maps the SRIO data into control instructions and data read-write instructions of various interfaces according to protocols, the instructions and the data are sent to the interfaces through the IP cores of the interface bus protocols, the FPGA is compatible with the interfaces and can exist at the same time, and the number of interface devices can be expanded.

For example, the 0x 300000-0 x3FFFFF interface interval of the CPU corresponds to a register list of the SPI bus, the first data in the register indicates that the baud rate of the SPI bus is designed, the second data is data to be sent to the SPI bus, the FPGA reads the first data of the 0x200000 start address according to a predetermined convention, updates the baud rate in the SPI bus interface protocol, and sends the second data to the SPI bus interface according to the baud rate if the second data is read. In another embodiment, the 0x 500000-0 x5FFFFF interface interval of the CPU corresponds to a register list of the UART bus, the first data in the register is 1 to indicate communication through an RS422 serial port, the second data in the register is 1 to indicate communication through an RS485 serial port, the third data in the register is 1 to indicate communication through an RS232 serial port, the fourth data is data to be sent to the UART bus, the FPGA sets the serial port in the UART bus interface protocol to RS485 according to a predetermined convention, assuming that the first three data read with the 0x500000 start address are 010, and sends the fourth data to the UART bus interface based on the RS485 serial port after reading the fourth data.

In some optional embodiments, the size of the interface interval is 1MB to 4MB, and the interface interval is customized according to needs. In a specific embodiment, as shown in fig. 2, each interface allocates 1MB space (SRIO access space is allocated in 0-0 x0FFFFF, PCIe access space is allocated in 0x 100000-0 x1 fffffff, … …), each interface allocates register lists according to a standard bus protocol, and can occupy multiple OUTBOUND spaces according to port number and port type, and only one interface in a certain OUTBOUND space can be allocated according to needs, or multiple bus interfaces are allocated in the same OUTBOUND space

In some optional embodiments, the processor CPU performs SRIO communication with the FPGA chip by using OUTBOUND address mapping and applying write operation NWRITE, stream write operation stride, or read operation NREAD.

In some optional embodiments, the FPGA chip communicates data with an external bus interface of an external device through its GPIO pin.

In some alternative embodiments, the FPGA chip communicates data with an external bus interface of an external device through its GTP pin.

In the embodiment, the external equipment is connected to the FPGA through the external bus, various bus types and the number can be flexibly configured and adjusted according to the system requirements, and various bus interfaces are compatible and have no conflict.

In some optional embodiments, the external device includes an SRIO device, a PCIe device, a PLB device, an SPI device, an IIC device, and a UART device, the FPGA chip communicates with the SRIO device through an SRIO bus, communicates with the PLB device through a PLB bus, communicates with the SPI device through an SPI bus, communicates with the IIC device through an IIC bus, and communicates with the UART device through a UART bus, and correspondingly, an SRIO interface section, a PCIe interface section, a PLB interface section, an SPI interface section, an IIC interface section, and a UART interface section are disposed in an OUTBOUND space of the processor CPU, a register list in the SRIO interface section records configuration parameters and transceiving control parameters of SRIO bus communication, a register list in the PCIe interface section records configuration parameters and transceiving control parameters of PCIe bus communication, and a register list in the PLB interface section records configuration parameters and transceiving control parameters of PLB bus communication, the register list in the SPI interface interval records configuration parameters and transceiving control parameters of SPI bus communication, the register list in the IIC interface interval records configuration parameters and transceiving control parameters of IIC bus communication, and the register list in the UART interface interval records configuration parameters and transceiving control parameters of UART bus communication.

Each bus interface type of this application includes SRIO bus interface, PCIE bus interface, PLB bus interface, SPI bus interface, IIC bus interface, UART bus interface and other radar signal processing interface commonly used, and each interface connection is at FPGA's GPIO or GTP pin, mutual noninterference.

A second aspect of the present application provides a communication method for a multi-interface compatible extension system based on an SRIO bus, where the communication method is performed by using the multi-interface compatible extension system based on the SRIO bus, and includes:

determining external equipment and an interface bus which need to be communicated, and writing interface configuration data associated with the interface bus into a corresponding address of an OUTBOUND space of a CPU (central processing unit) of a processor to form SRIO data;

sending SRIO data of corresponding addresses to the FPGA chip;

after receiving SRIO data of a CPU (central processing unit) of the processor, the FPGA chip maps the SRIO data into control instructions and data read-write instructions of various interfaces according to a protocol and controls an IP (Internet protocol) core of a corresponding interface in the FPGA to complete interface initialization;

and sending the instruction and the data to each interface through an interface bus protocol IP core so as to control the external equipment to perform read-write operation.

In some optional embodiments, the FPGA chip is configured to complete development and packaging of various types of interface bus protocol IP cores.

According to the method and the device, the interface resource requirements of the target CPU are reduced, the type selection range of the CPU is widened, the requirements of the radar information processing system on different interfaces are greatly met by utilizing FPGA logic development, and the development efficiency of the radar processing module is improved.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present application should be covered within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (8)

1. A multi-interface compatible extension system based on an SRIO bus is characterized by comprising a processor CPU and an FPGA chip, wherein the processor CPU is connected with the FPGA chip through the SRIO interface, and a plurality of external devices are connected to pins of the FPGA chip through an interface bus; the processor CPU comprises at least one OUTBOUND space, a plurality of interface intervals are divided in the OUTBOUND space, each interface interval corresponds to a register list, protocol parameters of bus communication between the FPGA and each external device are recorded in the register list, the FPGA chip is configured to map control data to corresponding external device interface IPs according to the interface interval distribution information of the OUTBOUND space, and each interface IP core completes register configuration and data receiving and sending control of various bus interfaces according to the control data.

2. The SRIO bus-based multi-interface compatible extension system of claim 1, wherein the size of the interface interval is 1MB to 4 MB.

3. The SRIO bus-based multi-interface compatible extension system of claim 1, wherein the processor CPU performs SRIO communication with the FPGA chip by using address mapping of OUTBOUND, applying write operation NWRITE, stream write operation switch, or read operation NREAD.

4. The SRIO bus based multi-interface compatible extension system of claim 1, wherein the FPGA chip communicates data with an external bus interface of an external device through its GPIO pin.

5. The SRIO bus based multi-interface compatible extension system of claim 1, wherein the FPGA chip communicates data with an external bus interface of an external device through its GTP pin.

6. The SRIO bus-based multi-interface compatible expansion system of claim 1, wherein the external devices comprise SRIO devices, PCIe devices, PLB devices, SPI devices, IIC devices and UART devices, the FPGA chip communicates with the SRIO devices through SRIO buses, communicates with the PLB devices through PLB buses, communicates with the SPI devices through SPI buses, communicates with the IIC devices through IIC buses, and communicates with the UART devices through UART buses, correspondingly, SRIO interface intervals, PCIe interface intervals, PLB interface intervals, SPI interface intervals, IIC interface intervals and UART interface intervals are arranged in OUTBOUTBOUTBOUTBOUND space of the CPU, register lists in the SRIO interface intervals record configuration parameters and transceiving control parameters of SRIO bus communication, register lists in the PCIe interface intervals record configuration parameters and transceiving control parameters of PCIe bus communication, the register list in the PLB interface interval records configuration parameters and receiving and transmitting control parameters of PLB bus communication, the register list in the SPI interface interval records configuration parameters and receiving and transmitting control parameters of SPI bus communication, the register list in the IIC interface interval records configuration parameters and receiving and transmitting control parameters of IIC bus communication, and the register list in the UART interface interval records configuration parameters and receiving and transmitting control parameters of UART bus communication.

7. A communication method for SRIO bus based multi-interface compatible extension system, wherein the SRIO bus based multi-interface compatible extension system of claim 1 is used for communication, and the communication method comprises:

determining external equipment and an interface bus which need to be communicated, and writing interface configuration data associated with the interface bus into a corresponding address of an OUTBOUND space of a CPU (central processing unit) of a processor to form SRIO data;

sending SRIO data of corresponding addresses to the FPGA chip;

after receiving SRIO data of a CPU (central processing unit) of the processor, the FPGA chip maps the SRIO data into control instructions and data read-write instructions of various interfaces according to a protocol and controls an IP (Internet protocol) core of a corresponding interface in the FPGA to complete interface initialization;

and sending the instruction and the data to each interface through an interface bus protocol IP core so as to control the external equipment to perform read-write operation.

8. The communication method of the SRIO bus based multi-interface compatible extension system of claim 7, wherein the FPGA chip is configured to complete development and encapsulation of various types of interface bus protocol IP cores.

Images